Envelope tracking circuit and related power amplifier apparatus

Abstract

An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.

Description

FIELD OF THE DISCLOSURE

The technology of the disclosure relates generally to an envelope tracking (ET) power amplifier apparatus and an ET circuit therein.

BACKGROUND

Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by wireless communication technologies, such as fifth-generation new-radio (5G-NR) technology configured to communicate a millimeter wave (mmWave) radio frequency (RF) signal(s) in an mmWave spectrum located above 12 GHz frequency. To achieve the higher data rates, a mobile communication device may employ a power amplifier(s) to increase output power of the mmWave RF signal(s) (e.g., maintaining sufficient energy per bit). However, the increased output power of mmWave RF signal(s) can lead to increased power consumption and thermal dissipation in the mobile communication device, thus compromising overall performance and user experiences.

Envelope tracking (ET) is a power management technology designed to improve efficiency levels of the power amplifier(s) to help reduce power consumption and thermal dissipation in the mobile communication device. As the name suggests, an ET circuit(s) can be configured to keep track of a time-variant power envelope(s) of the mmWave RF signal(s) communicated by the mobile communication device. As such, the ET circuit(s) can constantly adjusts a voltage(s) supplied to the power amplifier(s) based on instantaneous power level of the mmWave RF signal(s) to improve linearity and efficiency of the power amplifier(s).

Notably, the mmWave RF signal(s) can be susceptible to attenuation and interference resulting from various sources. As such, the mobile communication device may employ multiple transmitters/antennas to simultaneously transmit a number of mmWave RF signals via a technique known as RF beamforming. Given that the mmWave RF signals may be associated with different time-variant power envelopes, it may be necessary to multiple power amplifiers for amplifying simultaneously the multiple mmWave RF signals. Accordingly, it may also be necessary to employ multiple ET circuits to supply simultaneously multiple voltages to the multiple power amplifiers. As a result, the mobile communication device may require a larger footprint for accommodating the multiple ET circuits. Furthermore, the increased number of ET circuits may also lead to increased complexity and heat dissipation in the mobile communication device. Hence, it may be desired to support RF beamforming in the mobile communication device without increasing number of the ET circuits.

SUMMARY

Embodiments of the disclosure relate to an envelope tracking (ET) circuit and related power amplifier apparatus. In one aspect, an ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals to respective power levels. In another aspect, the ET circuit is configured to include a target voltage circuit, a supply voltage circuit, and an ET voltage circuit. The target voltage circuit is configured to generate a number of ET target voltages adapted to the respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits. The supply voltage circuit is configured to generate a number of constant voltages. The ET voltage circuit is configured to generate the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. As such, it may be possible to adapt the ET modulated voltages to the respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, thus helping to improve linearity and efficiency of the amplifier circuits. Further, by providing the ET modulated voltages from a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.

In one aspect, an ET voltage circuit is provided. The ET voltage circuit includes a number of voltage selection circuits each configured to receive a number of constant voltages. The ET voltage circuit also includes a number of voltage controllers coupled to the voltage selection circuits, respectively. The voltage controllers are configured to receive a number of ET target voltages, respectively. The voltage controllers are also configured to control the voltage selection circuits to output a number of selected constant voltages based on the ET target voltages, respectively. The voltage controllers are also configured to cause a number of ET modulated voltages to be generated based on the ET target voltages and the selected constant voltages, respectively.

In another aspect, a target voltage circuit is provided. The target voltage circuit is configured to receive a reference target voltage corresponding to a dynamic voltage range. The target voltage circuit is also configured to offset the reference target voltage to a baseline reference voltage corresponding to the dynamic voltage range. The target voltage circuit is also configured to determine a number of slope factors. The target voltage circuit is also configured to multiply the slope factors with the dynamic voltage range to generate a number of ET target voltages, respectively. The target voltage circuit is also configured to adjust the ET target voltages based on a number of offset factors, respectively.

In another aspect, a supply voltage circuit is provided. The supply voltage circuit includes an inductor-based voltage circuit configured to generate a direct current (DC) voltage based on a battery voltage. The supply voltage circuit also includes a number of output ports configured to output a number of constant voltages, respectively. A first selected output port among the output ports is coupled to the inductor-based voltage circuit to output the DC voltage as a first selected constant voltage among the constant voltages. One or more second selected output ports among the output ports are configured to output one or more second selected constant voltages among the constant voltages different from the first selected constant voltage. The supply voltage circuit also includes a capacitor-based voltage circuit coupled to the inductor-based voltage circuit. The capacitor-based voltage circuit is configured to generate the one or more second selected constant voltages at the one or more second selected output ports, respectively. The supply voltage circuit also includes a controller. The controller is configured to receive a feedback signal indicative of a preselected constant voltage among the constant voltages. The controller is also configured to control the inductor-based voltage circuit to adjust the DC voltage based on the preselected constant voltage.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of an exemplary envelope tracking (ET) power amplifier apparatus configured according to an embodiment of the present disclosure to support a number of amplifier circuits based on a single ET circuit;

FIG. 2 is a schematic diagram providing an exemplary illustration of a target voltage circuit in the ET circuit of FIG. 1 configured according to an embodiment of the present disclosure to generate a number of ET target voltages;

FIG. 3 is a schematic diagram providing an exemplary illustration of a supply voltage circuit in the ET circuit of FIG. 1 configured according to an embodiment of the present disclosure to generate a number of constant voltages;

FIG. 4A is a schematic diagram of an exemplary ET voltage circuit, which can be configured according to one embodiment of the present disclosure to function as an ET voltage circuit in the ET circuit of FIG. 1 to generate a number of ET modulated voltages based on the ET target voltages of FIG. 2 and the constant voltages of FIG. 3;

FIG. 4B is a schematic diagram of an exemplary ET voltage circuit, which can be configured according to another embodiment of the present disclosure to function as an ET voltage circuit in the ET circuit of FIG. 1 to generate a number of ET modulated voltages based on the ET target voltages of FIG. 2 and the constant voltages of FIG. 3; and

FIG. 4C is a schematic diagram of an exemplary ET voltage circuit, which can be configured according to another embodiment of the present disclosure to function as an ET voltage circuit in the ET circuit of FIG. 1 to generate a number of ET modulated voltages based on the ET target voltages of FIG. 2 and the constant voltages of FIG. 3.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the disclosure relate to an envelope tracking (ET) circuit and related power amplifier apparatus. In one aspect, an ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals to respective power levels. In another aspect, the ET circuit is configured to include a target voltage circuit, a supply voltage circuit, and an ET voltage circuit. The target voltage circuit is configured to generate a number of ET target voltages adapted to the respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits. The supply voltage circuit is configured to generate a number of constant voltages. The ET voltage circuit is configured to generate the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. As such, it may be possible to adapt the ET modulated voltages to the respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, thus helping to improve linearity and efficiency of the amplifier circuits. Further, by providing the ET modulated voltages from a single ET circuit, it may be possible to reduce a footprint and improve heat dissipation of the ET power amplifier apparatus.

In this regard, FIG. 1 is a schematic diagram of an exemplary ET power amplifier apparatus 10 configured according to an embodiment of the present disclosure to support a number of amplifier circuits 12(1)-12(N) based on an ET circuit 14. The amplifier circuits 12(1)-12(N) may be configured to amplify a number of RF signals 16(1)-16(N) from input powers P_IN-1-P_IN-N to output powers P_OUT-1-P_OUT-N, respectively. In a non-limiting example, the amplifier circuits 12(1)-12(N) are coupled to a signal processing circuit 18. The signal processing circuit 18 may be configured to receive a digital signal 20, which may include a digital in-phase (I) signal 20I and a digital quadrature (Q) signal 20Q. Accordingly, the digital signal 20 corresponds to a time-variant signal envelope √{square root over (I²+Q²)}, wherein I and Q represent time-variant in-phase amplitude and quadrature amplitude of the digital signal 20, respectively.

The signal processing circuit 18 is configured to convert the digital signal 20 into the RF signals 16(1)-16(N). More specifically, the signal processing circuit 18 may be configured to pre-process the RF signal 16(1)-16(N) to the input powers P_IN-1-P_IN-N and/or phase angles θ₁-θ_N, respectively, such that the RF signals 16(1)-16(N) can be transmitted coherently via RF beamforming.

The ET circuit 14 is configured to generate and provide a number of ET modulated voltages V_CC-1-V_CC-N to the amplifier circuits 12(1)-12(N), respectively. In examples discussed herein, the ET modulated voltages V_CC-1-V_CC-N may be generated in accordance to the input powers P_IN-1-P_IN-N of the RF signals 16(1)-16(N) and/or load impedances Z_LOAD-1-Z_LOAD-N as seen from the amplifier circuits 12(1)-12(N) into the ET circuit 14. As such, it may be possible to improve linearity and efficiency of the amplifier circuits 12(1)-12(N). Further, by employing only the ET circuit 14 for generating the ET modulated voltages V_CC-1-V_CC-N, as opposed to employing multiple ET circuits, it may be possible to reduce footprint and heat dissipation in the ET power amplifier apparatus 10.

The ET circuit includes a target voltage circuit 22, a supply voltage circuit 24, and an ET voltage circuit 26. The target voltage circuit 22 is configured to receive a reference target voltage V_TARGET and generate a number of ET target voltages V_TARGET-1-V_TARGET-N based on the reference target voltage V_TARGET. The target voltage circuit 22 will be further discussed in detail in reference to FIG. 2 below.

The supply voltage circuit 24 is configured to generate a number of constant voltages V_DC1-V_DC-M. The supply voltage circuit 24 will be further discussed in detail in reference to FIG. 3 below.

The ET voltage circuit 26 is coupled to the target voltage circuit 22 and the supply voltage circuit 24. The ET voltage circuit 26 is configured to receive the ET target voltages V_TARGET-1-V_TARGET-N from the target voltage circuit 22 and the constant voltages V_DC-1-V_DC-N from the supply voltage circuit 24. As discussed in detail in FIGS. 4A-4C, the ET voltage circuit 26 can be configured according to various embodiments of the present disclosure to generate the ET modulated voltages V_CC-1-V_CC-N based on the ET target voltages V_TARGET-1-V_TARGET-N and a selected constant voltage among the constant voltages V_DC-1-V_DC-N.

FIG. 2 is a schematic diagram providing an exemplary illustration of the target voltage circuit 22 of FIG. 1 configured according to an embodiment of the present disclosure to generate the ET target voltages V_TARGET-1-V_TARGET-N. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

The target voltage circuit 22 may be coupled to a voltage processing circuit 28, which is further coupled to the signal processing circuit 18. In this regard, the voltage processing circuit 28 receives the digital signal 20 that corresponds to the time-variant amplitude envelope √{square root over (I²+Q²)}. The voltage processing circuit 28 includes an ET look-up table (LUT) 30 configured to store predetermined correlations between the time-variant amplitude envelope √{square root over (I²+Q²)} and a time-variant voltage envelope 32 associated with a digital target voltage signal 34. The voltage processing circuit 28 may include a digital-to-analog converter (DAC) 36 for converting the digital target voltage signal 34 into the reference target voltage V_TARGET, which corresponds to a time-variant target voltage envelope 38 that tracks (e.g., rises and falls) the time-variant voltage envelope 32 as well as the time-variant amplitude envelope √{square root over (I²+Q²)}. In this regard, the reference target voltage V_TARGET corresponds to a dynamic voltage range defined by a maximum level target voltage V_MAX-TARGET and a minimum level target voltage V_MIN-TARGET (dynamic voltage range=V_MAX-TARGET−V_MIN-TARGET) of the time-variant voltage envelope 32.

In a non-limiting example, the reference target voltage V_TARGET can be a differential voltage signal. As such, the target voltage circuit 22 may include a voltage converter 40 for converting the differential target voltage signal to the reference target voltage V_TARGET. The target voltage circuit 22 may also include an anti-alias filter (AAF) 42 for aliasing the reference target voltage V_TARGET.

The target voltage circuit 22 includes a first offset converter 44 configured to convert the reference target voltage V_TARGET to a baseline reference voltage V′_TARGET (e.g., 0 V) corresponding to the dynamic voltage range (V_MAX-TARGET−V_MIN-TARGET). The target voltage circuit 22 includes a number of multipliers 46(1)-46(N) coupled in parallel to the first offset converter 44 to receive the baseline reference voltage V′_TARGET. The multipliers 46(1)-46(N) can be configured to multiply a dynamic voltage range with a number of slope factors S₁-S_N to generate the ET target voltages V_TARGET-1-V_TARGET-N, respectively. In a non-limiting example, the slope factors S₁-S_N can be determined based on the equation (Eq. 1) below.S_i=(V_MAX-TARGET-i−V_MIN-TARGET-i)/(V_MAX-TARGET−V_MIN-TARGET)(1≤i≤N)  (Eq. 1)

In the equation above, V_MAX-TARGET-i and V_MIN-TARGET-i represent a maximum level and a minimum level of the ET target voltage V_TARGET-i (1≤i≤N) as defined in the ET LUT 30, respectively. (V_MAX-TARGET−V_MIN-TARGET) represents the dynamic voltage range of the reference target voltage V_TARGET. The target voltage circuit 22 includes a number of second offset converters 48(1)-48(N) coupled to the multipliers 46(1)-46(N), respectively. The second offset converters 48(1)-48(N) are configured to adjust the ET target voltages V_TARGET-1-V_TARGET-N based on a number of offset factors f₁-f_N, respectively. In this regard, each of the ET target voltages V_TARGET-1-V_TARGET-N may be generated based on the equation (Eq. 2) below.V_TARGET-i=S_i*(V_MAX-TARGET−V_MIN-TARGET)+f_i(1≤i≤N)  (Eq. 2)

FIG. 3 is a schematic diagram providing an exemplary illustration of the supply voltage circuit 24 of FIG. 1 configured according to an embodiment of the present disclosure to generate the constant voltages V_DC-1-V_Dc-M. Common elements between FIGS. 1 and 3 are shown therein with common element numbers and will not be re-described herein.

The supply voltage circuit 24 includes an inductor-based voltage circuit 50 (denoted as “μLBB”), which is configured to generate a direct current (DC) voltage V_DC based on a battery voltage V_BAT. The inductor-based voltage circuit 50 is coupled to an inductor 52, which is configured to induce a DC current I_DC based on the DC voltage V_DC. In a non-limiting example, the inductor-based voltage circuit 50 can be a buck-boost circuit configured to operate in a buck mode to generate the DC voltage V_DC as being less than or equal to the battery voltage V_BAT or in a boost mode to generate the DC voltage V_DC as being greater than the battery voltage V_BAT. In this regard, the supply voltage circuit 24 may include a controller 54, which can be a pulse width modulation (PWM) controller for example, configured to control the inductor-based voltage circuit 50. Specifically, the controller 54 may control the inductor-based voltage circuit 50 to operate in the buck mode and the boost mode based on a first control signal 56 and a second control signal 58, respectively.

The inductor-based voltage circuit 50 is coupled to a capacitor-based voltage circuit 60 (denoted as “μCBB”). A capacitor 62 may be provided in between the inductor-based voltage circuit 50 and the capacitor-based voltage circuit 60. The capacitor 62 has one end coupled to a ground GND and another end coupled in between the inductor-based voltage circuit 50 and the capacitor-based voltage circuit 60.

The supply voltage circuit 24 includes a number of output ports 64(1)-64(M) configured to output the constant voltages V_DC-1-V_DC-M, respectively. In one exemplary embodiment, a first selected output port 64(M) is coupled to the inductor-based voltage circuit 50 via a conductive line 66 directly. Accordingly, the first selected output port 64(M) outputs the DC voltage V_DC as a first selected constant voltage V_DC-M among the constant voltages V_DC-1-V_DC-M. According to the exemplary embodiment, one or more second selected output ports 64(1)-64(M−1) are coupled to the capacitor-based voltage circuit 60. Accordingly, the second selected output ports 64(1)-64(M−1) are configured to output one or more second selected constant voltages V_DC-1-V_DC-M-1, respectively.

In this regard, the capacitor-based voltage circuit 60 is configured to generate the second selected constant voltages V_DC-1-V_DC-M-1 based on the DC voltage V_DC. In a non-limiting example, the capacitor-based voltage circuit 60 can generate the second selected constant voltages V_DC-1-V_DC-M-1 by multiplying the DC voltage V_DC with one or more predefined scaling factors f_S-1-f_S-M-1, respectively. In this regard, each of the second selected constant voltages V_DC-1-V_DC-M-1 can be determined based on the equation (Eq. 3) below.V_DC-i=V_DC*f_S-i(1≤i≤M−1)  (Eq. 3)

In one embodiment, each of the predefined scaling factors f_S-1-f_S-M-1 can be a fractional scaling factor lesser than one (1). In this regard, each of the second selected constant voltages V_DC-1-V_DC-M-1 is lesser than the first selected constant voltage V_DC-M. Accordingly, the capacitor-based voltage circuit 60 can be configured to operate exclusively in the buck mode. In a non-limiting example, the constant voltages V_DC-1-V_DC-M can be outputted from the output ports 64(1)-64(M) based on ascending voltage values (V_DC-1≤V_DC-2≤ . . . ≤V_DC-M-1≤V_DC-M).

In one embodiment, each of the predefined scaling factors f_S-1-f_S-M-1 can be greater than 1. In this regard, each of the second selected constant voltages V_DC-1-V_DC-M-1 is greater than the first selected constant voltage V_DC-M. Accordingly, the capacitor-based voltage circuit 60 can be configured to operate exclusively in the boost mode.

In one embodiment, each of the predefined scaling factors f_S-1-f_S-M-1 can be either greater than 1 or lesser than 1. In this regard, each of the second selected constant voltages V_DC-1-V_DC-M-1 can be greater than the first selected constant voltage V_DC-M or lesser than the first selected constant voltage V_DC-M. Accordingly, the capacitor-based voltage circuit 60 can be configured to operate in both the buck mode and the boost mode (buck-boost mode).

The supply voltage circuit 24 includes a voltage feedback line 68 coupled from one of the second selected output ports 64(1)-64(M−1) to the controller 54. The voltage feedback line 68 is configured to carry a voltage feedback signal 70 indicative of a preselected constant voltage among the second selected constant voltages V_DC-1-V_DC-M-1. In a non-limiting example, the voltage feedback line 68 can be coupled from the output port 64(1) to the controller 54. The voltage feedback line 68 is configured to carry the voltage feedback signal 70 indicative of the preselected constant voltage V_DC-1. Since all of the second selected constant voltages V_DC-1-V_DC-M are related to the DC voltage V_DC, the voltage feedback signal 70 can be used to further indicate all of the second selected constant voltages V_DC-1-V_DC-M. Accordingly, the controller 54 may control the inductor-based voltage circuit 50 to adjust the DC voltage V_DC based on the voltage feedback signal 70.

The supply voltage circuit may include a clock generator 72 configured to generate an operating clock 74 for the capacitor-based voltage circuit 60. In a non-limiting example, the clock generator 72 can generate the operating clock 74 based on a reference clock CLK that is also configured to operate the controller 54.

FIG. 4A is a schematic diagram of an exemplary ET voltage circuit 26A, which can be configured according to one embodiment of the present disclosure to function as the ET voltage circuit 26 in the ET circuit 14 of FIG. 1 to generate the ET modulated voltages V_CC-1-V_CC-N based on the ET target voltages V_TARGET-1-V_TARGET-N of FIG. 2 and the constant voltages V_CC-1-V_DC-M of FIG. 3. Common elements between FIGS. 1 and 4A are shown therein with common element numbers and will not be re-described herein.

The ET voltage circuit 26A includes a number of voltage controllers 76(1)-76(N) coupled to a number of voltage selection circuits 78(1)-78(N), respectively. Each of the voltage controllers 76(1)-76(N) can be a microcontroller or a field programmable gate array (FPGA), for example. Each of the voltage selection circuits 78(1)-78(N) is configured to receive the constant voltages V_DC-1-V_DC-M from the supply voltage circuit 24. In a non-limiting example, the voltage selection circuits 78(1)-78(N) can be configured to include a number of switching circuits 80(1)-80(N). Each of the switching circuits 80(1)-80(N) can be controlled by a respective voltage controller to output a selected constant voltage among the constant voltages V_DC-1-V_DC-M as a respective ET modulated voltage among the ET modulated voltages V_CC-1-V_CC-N. For example, the voltage controller 76(1) can control the switching circuit 80(1) in the voltage selection circuit 78(1) to output a selected one of the constant voltages V_DC-1-V_DC-M as the ET modulated voltage V_CC-1. In this regard, the voltage selection circuits 78(1)-78(N) collectively output a number of selected constant voltages as the ET modulated voltages V_CC-1-V_CC-N, respectively.

Each of the voltage controllers 76(1)-76(N) can be configured to determine a selected constant voltage V_DC-S among the constant voltages V_DC-1-V_DC-M for a respective voltage selection circuit among the voltage selection circuits 78(1)-78(N) based on the equation (Eq. 4) below.V_DC-S=minimize[V_DC-j≥(V_TARGET-i+V_Headroom)](1≤i≤N)(1≤j≤M)  (Eq. 4)

In the equation above, V_DC-j represents any of the constant voltages V_DC-1-V_DC-M, V_TARGET-i represents a respective ET target voltage among the ET target voltages V_TARGET-1-V_TARGET-N, and V_Headroom represents a predefined headroom voltage (e.g., 0.9 V). In this regard, each of the voltage controllers 76(1)-76(N) can be configured to control the respective voltage selection circuit to output the selected constant voltage as being a smallest constant voltage among the constant voltages V_DC-1-V_DC-M that is greater than or equal to the respective ET target voltage among the ET target voltages V_TARGET-1-V_TARGET-N. For example, the voltage controller 76(1) can control the voltage selection circuit 78(1) to output the smallest constant voltage among the constant voltages V_DC-1-V_DC-M that is greater than or equal to the ET voltage V_TARGET-1 as the ET modulated voltage V_CC-1. Notably, the ET voltage circuit 26A is configured to generate the ET modulated voltages V_CC-1-V_CC-N corresponding to a number of non-continuous voltage envelopes 82(1)-82(N), respectively.

FIG. 4B is a schematic diagram of an exemplary ET voltage circuit 26B, which can be configured according to one embodiment of the present disclosure to function as the ET voltage circuit 26 in the ET circuit 14 of FIG. 1 to generate the ET modulated voltages V_CC-1-V_CC-N based on the ET target voltages V_TARGET-1-V_TARGET-N of FIG. 2 and the constant voltages V_DC-1-V_DC-M of FIG. 3. Common elements between FIGS. 1 and 4B are shown therein with common element numbers and will not be re-described herein.

The ET voltage circuit 26B includes a number of voltage controllers 84(1)-84(N) coupled to a number of voltage selection circuits 86(1)-86(N), respectively. Each of the voltage controllers 84(1)-84(N) can be a microcontroller or a field programmable gate array (FPGA), for example. The ET voltage circuit 26B includes a number of voltage amplifiers 88(1)-88(N) configured to output the ET modulated voltages V_CC-1-V_CC-N based on the ET target voltages V_TARGET-1-V_TARGET-N and a number of supply voltages V_SUP-1-V_SUP-N.

Each of the voltage selection circuits 86(1)-86(N) includes a number of field-effect transistors (FETs) 90(1)-90(M) provided in a serial arrangement. The FETs 90(1)-90(M) in each of the voltage selection circuits 86(1)-86(N) include a number of gate electrodes 92(1)-92(M) coupled to a respective voltage controller among the voltage controllers 84(1)-84(N). The FETs 90(1)-90(M) in each of the voltage selection circuits 86(1)-86(N) include a number of drain electrodes 94(1)-94(M) coupled to the supply voltage circuit 24 to receive the constant voltages V_DC-1-V_DC-M, respectively. The FETs 90(1)-90(M) in each of the voltage selection circuits 86(1)-86(N) include a number of source electrodes 96(1)-96(M) coupled to a respective voltage amplifier among the voltage amplifiers 88(1)-88(N) to provide a respective supply voltage among the supply voltages V_SUP-1-V_SUP-N. The ET voltage circuit 26B includes a number of second FETs 98(1)-98(N) coupled respectively between the voltage selection circuits 86(1)-86(N) and the ground GND.

Each of the voltage controllers 84(1)-84(N) is configured to control a respective voltage selection circuit among the voltage selection circuits 86(1)-86(N) to output a selected constant voltage among the constant voltages V_DC-1-V_DC-M to a respective voltage amplifier among the voltage amplifiers 88(1)-88(N) as a respective supply voltage among the supply voltages V_SUP-1-V_SUP-N. For example, the voltage controller 84(1) is configured to control the voltage selection circuit 86(1) to output any of the constant voltages V_DC-1-V_DC-M to the voltage amplifier 88(1) as the supply voltage V_SUP-1. In this regard, the voltage selection circuits 86(1)-86(N) collectively output a number of selected constant voltages as the supply voltages V_SUP-1-V_SUP-N, respectively. Each of the voltage controllers 84(1)-84(N) may determine the respective constant voltage to be outputted from the respective voltage selection circuit based on the equation (Eq. 4) above.

By determining the supply voltages V_SUP-1-V_SUP-N based on the ET target voltages V_TARGET-1-V_TARGET-N, it may be possible to cause the voltage amplifiers 88(1)-88(N) to operate with improved efficiency. Notably, the ET voltage circuit 26B is configured to generate the ET modulated voltages V_CC-1-V_CC-N corresponding to a number of continuous voltage envelopes 100(1)-100(N), respectively.

FIG. 4C is a schematic diagram of an exemplary ET voltage circuit 26C, which can be configured according to one embodiment of the present disclosure to function as the ET voltage circuit 26 in the ET circuit 14 of FIG. 1 to generate the ET modulated voltages V_CC-1-V_CC-N based on the ET target voltages V_TARGET-1-V_TARGET-N of FIG. 2 and the constant voltages V_DC-1-V_DC-M of FIG. 3. Common elements between FIGS. 1, 4B, and 4C are shown therein with common element numbers and will not be re-described herein.

The ET voltage circuit 26C further includes a number of linear FETs 102(1)-102(N), which can be p-type FETs (PFETs) for example. The linear FETs 102(1)-102(N) include a number of gate terminals 104(1)-104(N) coupled to the voltage amplifiers 88(1)-88(N), respectively. The linear FETs 102(1)-102(N) include a number of source terminals 106(1)-106(N) coupled to the voltage selection circuits 86(1)-86(N), respectively. The linear FETs 102(1)-102(N) include a number of drain terminals 108(1)-108(N) coupled to the second FETs 98(1)-98(N), respectively. The linear FETs 102(1)-102(N) are configured to output the ET modulated voltages V_CC-1-V_CC-N respectively from the drain terminals 108(1)-108(N) with improved linearity.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. An envelope tracking (ET) voltage circuit comprising: a plurality of voltage selection circuits each configured to receive a plurality of constant voltages; anda plurality of voltage controllers coupled to the plurality of voltage selection circuits, respectively, and configured to: receive a plurality of ET target voltages, respectively;control the plurality of voltage selection circuits to output a plurality of selected constant voltages based on the plurality of ET target voltages, respectively; andcause a plurality of ET modulated voltages to be generated based on the plurality of ET target voltages and the plurality of selected constant voltages, respectively.

2. The ET voltage circuit of claim 1 wherein: the plurality of voltage selection circuits comprises a plurality of switching circuits each configured to receive the plurality of selected constant voltages; andthe plurality of voltage controllers coupled to the plurality of switching circuits, respectively, the plurality of voltage controllers each configured to: determine a respective selected constant voltage to be outputted by a respective switching circuit among the plurality of switching circuits based on a respective ET target voltage among the plurality of ET target voltages; andcontrol the respective switching circuit to output the respective selected constant voltage as a respective ET modulated voltage among the plurality of ET modulated voltages.

3. The ET voltage circuit of claim 2 wherein each of the plurality of voltage controllers is further configured to determine the respective selected constant voltage as being equal to minimize [VDC-j≥(VTARGET-i+VHeadroom)] (1≤i≤N) (1≤j≤M), wherein: VDC-j represents any of the plurality of constant voltages;VTARGET-i represents the respective ET target voltage among the plurality of ET target voltages;VHeadroom represents a predefined headroom voltage;i represents any one of the plurality of ET target voltages;N represents a count of the plurality of ET target voltages;j represents any one of the plurality of constant voltages; andM represents a count of the plurality of constant voltages.

4. The ET voltage circuit of claim 1 further comprising a plurality of voltage amplifiers coupled to the plurality of voltage controllers and the plurality of voltage selection circuits, respectively, the plurality of voltage amplifiers is configured to generate the plurality of ET modulated voltages based on the plurality of ET target voltages and a plurality of supply voltages, respectively.

5. The ET voltage circuit of claim 4 wherein each of the plurality of voltage controllers is further configured to: determine a respective selected constant voltage to be outputted by a respective voltage selecting circuit among the plurality of voltage selection circuits based on a respective ET target voltage among the plurality of ET target voltages; andcontrol the respective voltage selection circuit to output the respective selected constant voltage to a respective voltage amplifier among the plurality of voltage amplifiers as a respective supply voltage among the plurality of supply voltages.

6. The ET voltage circuit of claim 5 wherein the plurality of voltage selection circuits each comprises a plurality of field-effect transistors (FETs) disposed according to a serial arrangement, the plurality of FETs comprising: a plurality of drain electrodes configured to receive the plurality of constant voltages, respectively;a plurality of gate electrodes coupled to a respective voltage controller among the plurality of voltage controllers; anda plurality of source electrodes coupled to a respective second FET among a plurality of second FETs.

7. The ET voltage circuit of claim 6 wherein the ET voltage circuit further comprises a plurality of linear FETs, each of the plurality of linear FETs comprising: a gate terminal coupled to a respective voltage amplifier among the plurality of voltage amplifiers;a source terminal coupled to a respective voltage selection circuit among the plurality of voltage selection circuits; anda drain terminal coupled to a respective second FET among the plurality of second FETs and configured to output a respective ET modulated voltage among the plurality of ET modulated voltages.