Envelope tracking integrated circuit supporting multiple types of power amplifiers

Abstract

An envelope tracking (ET) integrated circuit (ETIC) supporting multiple types of power amplifiers. The ETIC includes a pair of tracker circuits configured to generate a pair of low-frequency currents at a pair of output nodes, respectively. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages at the output nodes, respectively. In various embodiments disclosed herein, the ETIC can be configured to generate the low-frequency currents independent of what type of power amplifier is coupled to the output nodes. Concurrently, the ETIC can also generate the ET voltages in accordance with the type of power amplifier coupled to the output nodes. As such, it is possible to support multiple types of power amplifiers based on a single ETIC, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ETIC and the multiple types of power amplifiers.

Description

FIELD OF THE DISCLOSURE

The technology of the disclosure relates generally to an envelope tracking (ET) integrated circuit (ETIC) capable of supporting multiple types of power amplifiers.

BACKGROUND

Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

A fifth-generation new radio (5G-NR) wireless communication system is widely regarded as a technological advancement that can achieve significantly higher data throughput, improved coverage range, enhanced signaling efficiency, and reduced latency compared to the existing third-generation (3G) and fourth-generation (4G) communication systems. A 5G-NR mobile communication device usually transmits and receives a radio frequency (RF) signal(s) in a millimeter wave (mmWave) RF spectrum that is typically above 6 GHz. Notably, the RF signal(s) transmitted in the mmWave RF spectrum may be more susceptible to propagation attenuation and interference that can result in substantial reduction in data throughput. To help mitigate propagation attenuation and maintain desirable data throughput, the 5G-NR mobile communication device may be configured to transmit the RF signal(s) based on such spatial multiplexing/diversity schemes as multiple-input multiple-output (MIMO) and RF beamforming. As such, the 5G-NR mobile communication device typically employs a power management circuit(s) to drive a power amplifier(s) for amplifying the RF signal(s) before feeding the RF signal(s) to an antenna(s).

Notably, the 5G-NR mobile communication device may include multiple types of power amplifiers (e.g., differential power amplifier, single-stage power amplifier, multi-stage power amplifier, balanced power amplifier, etc.), each adapted to and/or optimized for a specific type of application and/or transmission scheme. For example, a differential power amplifier or a multi-stage power amplifier is more efficient for amplifying a same RF signal for transmission based on a spatial diversity scheme, while a balanced power amplifier will be better suited for amplifying different RF signals for transmission based on a spatial multiplexing scheme. In this regard, it is desirable to configure the 5G-NR mobile communication device to efficiently support a variety of power amplifiers based on as lesser number of power management circuits as possible.

SUMMARY

Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (ETIC) supporting multiple types of power amplifiers. The ETIC includes a pair of tracker circuits configured to generate a pair of low-frequency currents at a pair of output nodes, respectively. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages at the output nodes, respectively. In various embodiments disclosed herein, the ETIC can be configured to generate the low-frequency currents independent of what type of power amplifier is coupled to the output nodes. In the meantime, the ETIC can also be configured to generate the ET voltages in accordance with the type of power amplifier that is coupled to the output nodes. As such, it is possible to support multiple types of power amplifiers based on a single ETIC, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ETIC and the multiple types of power amplifiers.

In one aspect, an ETIC is provided. The ETIC includes a first output node and a second output node coupled to a power amplifier. The ETIC also includes a first tracker circuit configured to generate a first low-frequency current at the first output node. The ETIC also includes a second tracker circuit configured to generate a second low-frequency current at the second output node. The ETIC also includes a first ET voltage circuit configured to generate a first ET voltage at the first output node based on a first ET target voltage. The ETIC also includes a second ET voltage circuit configured to generate a second ET voltage at the second output node based on a second ET target voltage. The ETIC also includes a control circuit. The control circuit is configured to determine a type of the power amplifier. The control circuit is also configured to cause the first tracker circuit and the second tracker circuit to generate the first low-frequency current and the second low-frequency current, respectively, independent of the type of the power amplifier. The control circuit is also configured to cause the first ET voltage circuit and the second ET voltage circuit to generate the first ET voltage and the second ET voltage, respectively, in accordance with the type of the power amplifier.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of an exemplary envelope tracking (ET) integrated circuit (ETIC) that can be configured according to various embodiments of the present disclosure to support different types of power amplifiers;

FIGS. 2A-2D are schematic diagrams providing exemplary illustrations of various types of power amplifiers that can be coupled to the ETIC in FIG. 1 to receive the ET voltages; and

FIGS. 3A and 3B are schematic diagram providing exemplary illustrations of different configurations of a tracker circuit in the ETIC of FIG. 1.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (ETIC) supporting multiple types of power amplifiers. The ETIC includes a pair of tracker circuits configured to generate a pair of low-frequency currents at a pair of output nodes, respectively. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages at the output nodes, respectively. In various embodiments disclosed herein, the ETIC can be configured to generate the low-frequency currents independent of what type of power amplifier is coupled to the output nodes. In the meantime, the ETIC can also be configured to generate the ET voltages in accordance with the type of power amplifier that is coupled to the output nodes. As such, it is possible to support multiple types of power amplifiers based on a single ETIC, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ETIC and the multiple types of power amplifiers.

In this regard, FIG. 1 is a schematic diagram of an exemplary ETIC 10 that can be configured according to various embodiments of the present disclosure to support a power amplifier 12 (denoted as “PA1”) of different types. Although FIG. 1 shows only one power amplifier 12, it should be appreciated that the ETIC 10 can support more than one power amplifier 12, either concurrently or independently. The ETIC 10 can be configured to include at least a first tracker circuit 14A and a second tracker circuit 14B. The first tracker circuit 14A is configured to generate a first low-frequency current I_DCA (e.g., a constant current) at a first output node 16A. The second tracker circuit 14B is configured to generate a second low-frequency current I_DCB (e.g., a constant current) at a second output node 16B. In a non-limiting example, both the first output node 16A and the second output node 16B are coupled to the power amplifier 12.

The ETIC 10 also includes at least a first ET voltage circuit 18A and a second ET voltage circuit 18B. The first ET voltage circuit 18A is configured to generate a first ET voltage V_CCA at the first output node 16A based on a first ET target voltage V_TGTA. The second ET voltage circuit 18B is configured to generate a second ET voltage V_CCB at the second output node 16B based on a second ET target voltage V_TGTB.

The ETIC 10 further includes a control circuit 20, which can be any type of microcontroller, microprocessor, and field-programmable gate array (FPGA), as an example. The control circuit 20 can be configured to determine a type of the power amplifier 12 being coupled to the first output node 16A and the second output node 16B (e.g., based on stored configuration information). Accordingly, the control circuit 20 can control the ETIC 10 to generate the first low-frequency current I_DCA, the second low-frequency current I_DCB, the first ET voltage V_CCA, and the second ET voltage V_CCB that are appropriate for the determined type of the power amplifier 12.

Specifically, the control circuit 20 controls the first tracker circuit 14A and the second tracker circuit 14B (e.g., via a control signal 22) to generate the first low-frequency current I_DCA and the second low-frequency current I_DCB, respectively, independent of the type of the power amplifier 12. In a non-limiting example, the first tracker circuit 14A and the second tracker circuit 14B each generates one-half (½) of a total low-frequency current required by the power amplifier 12. In other words, the first low-frequency current I_DCA is identical to the second low-frequency current I_DCB (I_DCA=I_DCB).

In contrast, the control circuit 20 controls the first ET voltage circuit 18A and the second ET voltage circuit 18B (e.g., via the control signal 22) to generate the first ET voltage V_CCA and the second ET voltage V_CCB, respectively, in accordance with the determined type of the power amplifier 12. In addition, the control circuit 20 may further cause the first ET voltage circuit 18A and the second ET voltage circuit 18B (e.g., via the control signal 22) to source a first high-frequency current I_ACA (e.g., an alternating current) and a second high-frequency current I_ACB (e.g., an alternating current), respectively, in accordance with the determined type of the power amplifier 12. As such, it is possible to support the power amplifier 12 of different types based on a single one of the ETIC 10, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device (e.g., a wireless communication device) employing the ETIC 10 and the power amplifier 12.

The first tracker circuit 14A includes a first multi-level charge pump (MCP) 24A configured to generate a first low-frequency voltage V_DCA (e.g., a constant voltage) at multiple levels. The first tracker circuit 14A also includes a first power inductor 26A coupled between the first MCP 24A and the first output node 16A. The first power inductor 26A is configured to induce the first low-frequency current I_DCA based on the first low-frequency voltage V_DCA.

Likewise, the second tracker circuit 14B includes a second MCP 24B configured to generate a second low-frequency voltage V_DCB (e.g., a constant voltage) at multiple levels. The second tracker circuit 14B also includes a second power inductor 26B coupled between the second MCP 24B and the second output node 16B. The second power inductor 26B is configured to induce the second low-frequency current I_DCB based on the second low-frequency voltage V_DCB. Notably, since the first power inductor 26A and the second power inductor 26B each induces ½ of the total low-frequency current required by the power amplifier 12, each of the first power inductor 26A and the second power inductor 26B can be significantly smaller (e.g., 2.2 μH) than a power inductor required to induce the total low-frequency current required by the power amplifier 12.

The first ET voltage circuit 18A includes a first voltage amplifier 28A. The first voltage amplifier 28A is biased by one of a lower supply voltage V_SUPL and a higher supply voltage V_SUPH and configured to generate a first initial ET voltage V′_CCA that tracks (rises and falls) the first ET target voltage V_TGTA. The first ET voltage circuit 18A also includes a first offset capacitor 30A coupled between the first voltage amplifier 28A and the first output node 16A. The first offset capacitor 30A is configured to raise the first initial ET voltage V′_CCA by a first offset voltage V_OFFA to generate the first ET voltage V_CCA (V_CCA=V′_CCA+V_OFFA) at the first output node 16A. The first ET voltage circuit 18A further includes a first feedback loop 32A configured to provide a feedback of the first ET voltage V_CCA to the first voltage amplifier 28A, thus making the first ET voltage circuit 18A a closed-loop ET voltage circuit.

Similarly, the second ET voltage circuit 18B includes a second voltage amplifier 28B. The second voltage amplifier 28B is biased by one of the lower supply voltage V_SUPL and the higher supply voltage V_SUPH and configured to generate a second initial ET voltage V′_CCB that tracks (rises and falls) the second ET target voltage V_TGTB. The second ET voltage circuit 18B also includes a second offset capacitor 30B coupled between the second voltage amplifier 28B and the second output node 16B. The second offset capacitor 30B is configured to raise the second initial ET voltage V′_CCB by a second offset voltage V_OFFB to generate the second ET voltage V_CCB (V_CCB=V′_CCB+V_OFFB) at the second output node 16B. The second ET voltage circuit 18B further includes a second feedback loop 32B configured to provide a feedback of the second ET voltage V_CCB to the second voltage amplifier 28B, thus making the second ET voltage circuit 18B a closed-loop ET voltage circuit.

The ETIC 10 includes a supply voltage circuit 34 configured to generate the lower supply voltage V_SUPL and the higher supply voltage V_SUPH based on a battery voltage V_BAT. In a non-limiting example, the supply voltage circuit 34 is configured to generate the lower supply voltage V_SUPL that equals the battery voltage V_BAT (V_SUPL=V_BAT) and the higher supply voltage V_SUPH that equals two times the battery voltage V_BAT (V_SUPH=2*V_BAT). The ETIC 10 also includes a target voltage circuit 36 configured to generate the first ET target voltage V_TGTA and the second ET target voltage V_TGTB.

The ETIC 10 may include an auxiliary node 38 configured to output an auxiliary ET voltage V_CCAUX to a second power amplifier 40 (denoted as “PA2”), which may be a different type of power amplifier from the power amplifier 12. Although FIG. 1 shows only one of the second power amplifier 40, it should be appreciated that the ETIC 10 can support more than one of the second power amplifier 40, either concurrently or independently. The ETIC 10 may include a switch circuit 42, which can be controlled by the control circuit 20 via the control signal 22. In a non-limiting example, the switch circuit 42 includes switches S1, S2, and S3, which can be any type of switch as appropriate. The switch S1 is provided between the first output node 16A and a coupling node 44. The switch S2 is provided between the second output node 16B and the coupling node 44. The switch S3 is provided between the auxiliary node 38 and the coupling node 44.

The ETIC 10 may also include a first hybrid circuit 46A (denoted as “SW/LDO”) and a second hybrid circuit 46B (denoted as “SW/LDO”). Each of the first hybrid circuit 46A and the second hybrid circuit 46B can be controlled to operate in a switch mode as a switch or a low-dropout (LDO) mode as an LDO regulator. The first hybrid circuit 46A is provided between the first ET voltage circuit 18A and the first output node 16A. The second hybrid circuit 46B is provided between the second ET voltage circuit 18B and the second output node 16B. Accordingly, the switch S1 is coupled to the first output node 16A via the first hybrid circuit 46A and the switch S2 is coupled to the second output node 16B via the second hybrid circuit 46B.

The ETIC 10 can be configured to support a variety of types of power amplifiers via the first output node 16A, the second output node 16B, and/or the auxiliary node 38. In this regard, FIGS. 2A-2D are schematic diagrams providing exemplary illustrations of various types of power amplifiers that can be supported by the ETIC 10 in FIG. 1. Common elements between FIGS. 1 and 2A-2D are shown therein with common element numbers and will not be re-described herein.

FIG. 2A is a schematic diagram of an exemplary differential power amplifier 48 (also referred to as “first type power amplifier”), which can be coupled to the first output node 16A and the second output node 16B as the power amplifier 12 in FIG. 1. The differential power amplifier 48 includes a first voltage input 50 and a second voltage input 52. The first voltage input 50 is coupled to the first output node 16A in FIG. 1 to receive the first ET voltage V_CCA, the first low-frequency current I_DCA, and the first high-frequency current I_ACA. The second voltage input 52 is coupled to the second output node 16B in FIG. 1 to receive the second ET voltage V_CCB, the second low-frequency current I_DCB, and the second high-frequency current I_ACB. The differential power amplifier 48 receives a radio frequency (RF) signal 54 and converts the RF signal 54 into a pair of differential RF signals 56M, 56P. Accordingly, the differential power amplifier 48 amplifies the differential RF signals 56M, 56P based on the first ET voltage V_CCA and the second ET voltage V_CCB, respectively.

With reference back to FIG. 1, when the control circuit 20 determines (e.g., based on stored configuration information) that the power amplifier 12 is the differential power amplifier 48 in FIG. 2A, the control circuit 20 can cause the first ET voltage circuit 18A and the second ET voltage circuit 18B (e.g., via the control signal 22) to generate the first ET voltage V_CCA and the second ET voltage V_CCB having substantially equal instantaneous amplitudes. Herein, the first ET voltage V_CCA and the second ET voltage V_CCB are said to have substantially equal instantaneous amplitudes when a difference between instantaneous amplitudes of the first ET voltage V_CCA and the second ET voltage V_CCB is less than ten percent (<10%). The control circuit 20 may further cause the first voltage amplifier 28A and the second voltage amplifier 28B to source the first high-frequency current I_ACA and the second high-frequency current I_ACB having substantially equal instantaneous peak amounts. Herein, the first high-frequency current I_ACA and the second high-frequency current I_ACB are said to have substantially equal instantaneous peak amounts when a difference between the first high-frequency current I_ACA and the second high-frequency current I_ACB is less than 10%.

FIG. 2B is a schematic diagram of an exemplary sigma-delta power amplifier 58 (also referred to as “second type power amplifier”), which can be coupled to the first output node 16A and the second output node 16B as the power amplifier 12 in FIG. 1. The sigma-delta power amplifier 58 includes a first signal output 60A and a second signal output 60B each coupled to a respective antenna(s) (not shown). The sigma-delta power amplifier 58 is configured to receive a pair of RF signals 62, 64 having different time-variant amplitudes A₁(t), A₂(t) and amplify the RF signals 62, 64 for concurrent radiation via the antennas coupled to the first signal output 60A and the second signal output 60B. In this regard, the sigma-delta power amplifier 58 may be employed to enable multiple-input multiple-output (MIMO) diversity and/or MIMO spatial multiplexing.

The sigma-delta power amplifier 58 can be configured to include an input circuit 66, a sigma voltage amplifier 68, a delta voltage amplifier 70, and an output circuit 72. The input circuit 66 is configured to receive the RF signals 62, 64 and generate a summed RF signal 74 and a differential RF signal 76 having an identical average amplitude √{square root over (A₁(t)²+A₂(t)²)}. The sigma voltage amplifier 68 is coupled to the first output node 16A in FIG. 1 to receive the first ET voltage V_CCA, the first low-frequency current I_DCA, and the first high-frequency current I_ACA. The delta voltage amplifier 70 is coupled to the second output node 16B in FIG. 1 to receive the second ET voltage V_CCB, the second low-frequency current I_DCB, and the second high-frequency current I_ACB. Accordingly, the sigma voltage amplifier 68 and the delta voltage amplifier 70 concurrently amplify the summed RF signal 74 and the differential RF signal 76, respectively. The output circuit 72 is configured to regenerate the RF signals 62, 64 from the summed RF signal 74 and the differential RF signal 76.

With reference back to FIG. 1, when the control circuit 20 determines (e.g., based on stored configuration information) that the power amplifier 12 is the sigma-delta power amplifier 58 in FIG. 2B, the control circuit 20 can cause the first ET voltage circuit 18A and the second ET voltage circuit 18B (e.g., via the control signal 22) to generate the first ET voltage V_CCA and the second ET voltage V_CCB having a substantially equal average amplitude √{square root over (A₁(t)²+A₂(t)²)}. Herein, the first ET voltage V_CCA and the second ET voltage V_CCB are said to have substantially equal average amplitudes when a difference between average amplitudes of the first ET voltage V_CCA and the second ET voltage V_CCB is less than 10%. The control circuit 20 may further cause the first voltage amplifier 28A and the second voltage amplifier 28B to source the first high-frequency current I_ACA and the second high-frequency current I_ACB having substantially equal average peak amounts. Herein, the first high-frequency current I_ACA and the second high-frequency current I_ACB are said to have substantially equal average peak amounts when a difference between the first high-frequency current I_ACA and the second high-frequency current I_ACB is less than 10%.

FIG. 2C is a schematic diagram of an exemplary multi-stage power amplifier 78 (also referred to as “third type power amplifier”), which can be coupled to the first output node 16A and the second output node 16B as the power amplifier 12 in FIG. 1. The multi-stage power amplifier 78 includes a driver stage amplifier 80 and one or more output stage amplifiers 82. The driver stage amplifier 80 is coupled to the first output node 16A to receive the first ET voltage V_CCA, the first low-frequency current I_DCA, and the first high-frequency current I_ACA. The output stage amplifiers 82 are all coupled to the second output node 16B to receive the second ET voltage V_CCB, the second low-frequency current I_DCB, and the second high-frequency current I_ACB.

With reference back to FIG. 1, when the control circuit 20 determines (e.g., based on stored configuration information) that the power amplifier 12 is the multi-stage power amplifier 78 in FIG. 2C, the control circuit 20 can close switches S1 and S2, while keeping switch S3 open, to couple the first output node 16A with the second output node 16B. In addition, the control circuit 20 can configure one of the first hybrid circuit 46A and the second hybrid circuit 46B to operate in the switch mode, and another one of the first hybrid circuit 46A and the second hybrid circuit 46B to operate in the LDO mode. For example, the control circuit 20 can configure (via the control signal 22) the first hybrid circuit 46A to operate in the switch mode and the second hybrid circuit 46B to operate in the LDO mode.

FIG. 2D is a schematic diagram of an exemplary power amplifier 84, which can be coupled to the auxiliary node 38 as the second power amplifier 40 in FIG. 1. The power amplifier 84 includes a voltage input 86 coupled to the auxiliary node 38 in FIG. 1 to receive the auxiliary ET voltage V_CCAUX, a sum of the first low-frequency current I_DCA and the second low-frequency current I_DCB, as well as a sum of the first high-frequency current I_ACA and the second high-frequency current I_ACB. The power amplifier 84 receives the RF signal 54 and converts the RF signal 54 into the differential RF signals 56M, 56P. Accordingly, the power amplifier 84 amplifies the differential RF signals 56M, 56P based on the auxiliary ET voltage V_CCAUX.

With reference back to FIG. 1, when the control circuit 20 determines (e.g., based on stored configuration information) that the second power amplifier 40 is the power amplifier 84 in FIG. 2D, the control circuit 20 can close switches S1, S2, and S3 (e.g., via the control signal 22). In this regard, the first tracker circuit 14A and the second tracker circuit 14B are coupled to the auxiliary node 38 to provide the sum of the first low-frequency current I_DCA and the second low-frequency current I_DCB to the second power amplifier 40. Additionally, the first ET voltage circuit 18A and the second ET voltage circuit 18B are also coupled to the auxiliary node 38 to provide the sum of the first high-frequency current I_ACA and the second high-frequency current I_ACB to the second power amplifier 40. By coupling the first ET voltage circuit 18A and the second ET voltage circuit 18B to the auxiliary node 38, the auxiliary ET voltage V_CCAUX is equal to the first ET voltage V_CCA and the second ET voltage V_CCB (V_CCAUX=V_CCA=V_CCB).

The ETIC 10 can be further configured to operate in an average power tracking (APT) mode. In this regard, the control circuit 20 can deactivate the first ET voltage circuit 18A and the second ET voltage circuit 18B. Instead, the control circuit 20 can control the first tracker circuit 14A and the second tracker circuit 14B to output any one of the first low-frequency voltage V_DCA and the second low-frequency voltage V_DCB as an APT voltage via any of the first output node 16A, the second output node 16B, and the auxiliary node 38.

FIG. 3A is a schematic diagram of an exemplary tracker circuit 88, which can replace the first tracker circuit 14A and the second tracker circuit 14B in the ETIC 10 of FIG. 1 to continuously supply an APT voltage V_APT. Common elements between FIGS. 1 and 3A are shown therein with common element numbers and will not be re-described herein.

The tracker circuit 88 may be configured to include a switch network 90 that includes switches S1, S2, and S3. The switch S1 is provided between the first tracker circuit 14A and the second tracker circuit 14B. The switch S2 is provided between the first MCP 24A and the first power inductor 26A. The switch S3 is provided between the second MCP 24B and the second power inductor 26B.

The control circuit 20 can control the switch network 90 (e.g., via the control signal 22) to alternately couple the first MCP 24A and the second MCP 24B to a selected one of the first power inductor 26A and the second power inductor 26B. For example, if the first tracker circuit 14A is configured to output the APT voltage V_APT via the first output node 16A in FIG. 1, the control circuit 20 will alternately couple the first MCP 24A (by closing S2 and opening S1, S3) and the second MCP 24B (by closing S1, S2 and opening S3) to the first power inductor 26A. In this regard, the second MCP 24B can be charged when the first MCP 24A is coupled to the first power inductor 26A and the first MCP 24A can be charged when the second MCP 24B is coupled to the first power inductor 26A. As a result, the ETIC 10 is able to continuously supply the APT voltage V_APT in the APT mode.

FIG. 3B is a schematic diagram of an exemplary tracker circuit 92, which can be provided in the ETIC 10 of FIG. 1 to replace the first tracker circuit 14A and the second tracker circuit 14B when the power amplifier 12 is not the second type power amplifier. Common elements between FIGS. 1 and 3B are shown therein with common element numbers and will not be re-described herein.

In a non-limiting example, the first power inductor 26A can be electrically coupled to the second power inductor 26B. As such, the first power inductor 26A and the second power inductor 26B can be integrated into a single package to help reduce footprint of the ETIC 10.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. An envelope tracking (ET) integrated circuit (ETIC) comprising: a first output node and a second output node coupled to a power amplifier;a first tracker circuit configured to generate a first low-frequency current at the first output node;a second tracker circuit configured to generate a second low-frequency current at the second output node;a first ET voltage circuit configured to generate a first ET voltage at the first output node based on a first ET target voltage;a second ET voltage circuit configured to generate a second ET voltage at the second output node based on a second ET target voltage; anda control circuit configured to: determine a type of the power amplifier;cause the first tracker circuit and the second tracker circuit to generate the first low-frequency current and the second low-frequency current, respectively, independent of the type of the power amplifier; andcause the first ET voltage circuit and the second ET voltage circuit to generate the first ET voltage and the second ET voltage, respectively, in accordance with the type of the power amplifier.

2. The ETIC of claim 1 wherein the control circuit is further configured to cause the first tracker circuit and the second tracker circuit to generate the first low-frequency current and the second low-frequency current that are identical.

3. The ETIC of claim 1 wherein the control circuit is further configured to cause the first ET voltage circuit and the second ET voltage circuit to generate the first ET voltage and the second ET voltage having substantially equal instantaneous amplitudes when the power amplifier is determined to be a first type power amplifier.

4. The ETIC of claim 3 wherein the first type power amplifier is a differential power amplifier configured to amplify a radio frequency (RF) signal based on the first ET voltage and the second ET voltage.

5. The ETIC of claim 3 wherein: the first ET voltage circuit is further configured to provide a first high-frequency peak current to the first output node;the second ET voltage circuit is further configured to provide a second high-frequency peak current to the second output node; andthe control circuit is further configured to cause the first ET voltage circuit and the second ET voltage circuit to generate the first high-frequency peak current and the second high-frequency peak current having substantially equal instantaneous peak amounts when the power amplifier is determined to be the first type power amplifier.

6. The ETIC of claim 1 wherein the control circuit is further configured to cause the first ET voltage circuit and the second ET voltage circuit to generate the first ET voltage and the second ET voltage having substantially equal average amplitudes when the power amplifier is determined to be a second type power amplifier.

7. The ETIC of claim 6 wherein the second type power amplifier is a sigma-delta power amplifier configured to concurrently amplify two different radio frequency (RF) signals based on the first ET voltage and the second ET voltage.

8. The ETIC of claim 7 wherein: the first ET voltage circuit is further configured to provide a first high-frequency peak current to the first output node;the second ET voltage circuit is further configured to provide a second high-frequency peak current to the second output node; andthe control circuit is further configured to cause the first ET voltage circuit and the second ET voltage circuit to generate the first high-frequency peak current and the second high-frequency peak current having substantially equal average peak amounts when the power amplifier is determined to be the second type power amplifier.

9. The ETIC of claim 1 further comprising a switch circuit coupled between the first output node and the second output node.

10. The ETIC of claim 9 further comprising: a first hybrid circuit coupled between the first ET voltage circuit and the first output node; anda second hybrid circuit coupled between the second ET voltage circuit and the second output node;wherein the first hybrid circuit and the second hybrid circuit are each configured to operate in a switch mode or a low-dropout (LDO) mode.

11. The ETIC of claim 10 wherein the control circuit is further configured to: control the switch circuit to couple the first output node with the second output node when the power amplifier is a third type power amplifier;control one of the first hybrid circuit and the second hybrid circuit to operate in the switch mode; andcontrol another one of the first hybrid circuit and the second hybrid circuit to operate in the LDO mode.

12. The ETIC of claim 11 wherein the third type power amplifier is a multi-stage power amplifier comprising: a driver stage amplifier coupled to the first output node to receive the first ET voltage; andone or more output stage amplifiers each coupled to the second output node to receive the second ET voltage;wherein the driver stage amplifier and the one or more output stage amplifiers are configured to collectively amplify a radio frequency (RF) signal.

13. The ETIC of claim 9 further comprising: an auxiliary node coupled to the switch circuit and a second power amplifier;wherein the control circuit is further configured to control the switch circuit to couple the first tracker circuit and the second tracker circuit to the auxiliary node such that the second power amplifier receives a sum of the first low-frequency current and the second low-frequency current.

14. The ETIC of claim 13 wherein the second power amplifier is a multi-stage power amplifier comprising a driver stage amplifier and an output stage amplifier each coupled to the auxiliary node and configured to collectively amplify a radio frequency (RF) signal.

15. The ETIC of claim 1 wherein each of the first tracker circuit and the second tracker circuit comprises: a multi-level charge pump (MCP) configured to generate a low-frequency voltage; anda power inductor coupled to the MCP and configured to induce a respective one of the first low-frequency current and the second low-frequency current based on the low-frequency voltage.

16. The ETIC of claim 15 further comprising a switch network coupled to the first tracker circuit and the second tracker circuit, wherein the control circuit is further configured to control the switch network to alternately couple the MCP in the first tracker circuit and the MCP in the second tracker circuit to the power inductor in a selected one of the first tracker circuit and the second tracker circuit.

17. The ETIC of claim 15 wherein the control circuit is further configured to deactivate the first ET voltage circuit and the second ET voltage circuit.

18. The ETIC of claim 15 wherein the power inductor in the first tracker circuit is electrically coupled to the power inductor in the second tracker circuit.

19. The ETIC of claim 1 wherein each of the first ET voltage circuit and the second ET voltage circuit comprises: a voltage amplifier configured to generate an initial ET voltage based on a respective one of the first ET target voltage and the second ET target voltage and a respective one of a lower supply voltage and a higher supply voltage; andan offset capacitor configured to raise the initial ET voltage by an offset voltage to generate a respective one of the first ET voltage and the second ET voltage.

20. The ETIC of claim 19 further comprising: a target voltage circuit configured to generate the first ET target voltage and the second ET target voltage; anda supply voltage circuit configured to generate the lower supply voltage and the higher supply voltage.