Patent Application
20100264391
Embodiments of the present invention are directed to micro-electromechanical system (MEMS) memories and, more particularly, to media layers for seek-scan probe (SSP) memory devices.
Seek-scan probe (SSP) memories are a type of memory that uses non-volatile storage media as the data storage mechanism and offers significant advantages in both cost and performance over conventional charge-storage memories. Typical SSP memories include storage media made of materials that can be electrically switched between two or more states having different electrical characteristics such as resistance, polarization dipole direction, or some other characteristic.
SSP memories are written to by passing an electric current through the storage media or applying an electric field to the storage media. Passing a current through the storage media, or applying an electric field to the media, is typically accomplished by applying a voltage between a sharp probe tip on one side of the storage media and an electrode on the other side of the storage media.
Current SSP memories use cantilever probe tips positioned on a free end of one or more MEMS probes. The cantilever probe is anchored to a substrate (the cantilever wafer), and can be actuated to contact or de-contact the storage media on a mover that carries a storage media and is positioned over the cantilever wafer. In an idle state each MEMS probe maintains the probe tip at a certain distance from the storage media, but before the electric field or current can be applied to the storage media the probe tip must usually be brought close to, or in some cases in direct contact with, the storage media. In order to fabricate an SSP memory device based on ferroelectric media, a high-quality media film must be deposited on the mover.
The foregoing and a better understanding of the present invention may become apparent from the following detailed description of arrangements and example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and the invention is not limited thereto.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
SSP memory device fabrication includes the formation of high quality crystalline PZT (Lead Zirconate Titanate) film on a template layer of strontium Titanium oxide/strontium ruthenium oxide (STO/SRO) grown on the front side of an Si substrate. The PZT film then comprises the read/write media on the front side of a mover wafer which can be scanned by the probes.
The mover wafer also gets move/sense circuitry that needs to be fabricated on the back side of this same wafer. The move/sense circuitry may be for example CMOS circuitry involving typical CMOS processing steps. Formation of this circuitry typically requires lower processing temperatures (<350° C.). Further, the mover circuitry generally requires low contact resistance to the substrate which necessitates use of high doping substrate with resistivity of 5-20 mohm-cm. Unfortunately, high doping of the substrate impacts growth of STO (insulator layer).
All of these restraints and conditions may be at odds with one another and make fabrication challenging. Current methods use a non-epitaxial (non-EPI) substrate and a compromise has to be made between low contact resistance on the wafer back-side and quality of STO/SRO/PZT growth on the front-side of the wafer. This may not be ideal.
Referring now to
Embodiments of the present invention use the low doping EPI layer 100 on a highly doped Si substrate 102. The low doping EPI layer 100 helps to promote high quality template STO layer 104 growth while the highly doped substrate 102 allows low contact resistance 104 on the wafer back-side which is beneficial for mover circuitry 106. While STO is shown in layer 104, SRO may also be used. The term “epitaxial” or EPI is directed to the growth of a single-crystal semiconductor film upon a single-crystal substrate. An epitaxial layer generally has the same crystallographic characteristics as the substrate material.
The EPI layer 100 provides a generally defect free layer for the STO layer 104 growth by, for example molecular beam epitaxy (MBE), because it is thought that the majority of the defects may be trapped at EPI/substrate interface 108.
As a further advantage, low doping in the EPI layer 100 may eliminate defect growth (high leakage regions) that may be formed if the low doped EPI layer 100 is not used. Low contact resistance 106 may still be made on the highly doped wafer 102 back-side even at temperatures <350° C. without formation of a high temperature salicide layer. This is beneficial since, back-side mover circuitry formation is typically limited to temperatures below 350° C.
Thus, according to embodiments described herein, this allows independent control of high quality STO growth by MBE while still being able to make low contact resistance to substrate at temperatures below <350° C.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
