Patent Application
20100194478
The present invention relates to the field of data communication. More particularly, the present invention relates to devices and corresponding methods for equalizer filtering in a line equalizer system, which restore attenuated signals transmitted over a communication or transmission channel for a wide variety of communication or transmission channels with an acceptable amount of jitter. The present invention also relates to the use of an equaliser in communications system, e.g. in a modem.
An equalizer system in general compensates frequency dependent losses that a signal experiences when passing through a transmission channel. Transmission channels include, but are not limited to, a wire, a pair of wires, an optical fibre, the reading and writing channels of a storage device like a hard-disc or optical disc, a wireless connection such as a point-to-point or diffuse infra-red or radio connection. A pair of wires includes a twisted pair, a twinax coax or a differential transmission line on a printed circuit board.
The compensation level of an equalizer system in general can be self-adaptive, fixed or programmable e.g. by a voltage or via a set of switches. A self-adaptive equalizer system continuously estimates the matching compensation level. It typically includes an adaptable filter, a control loop and an output reconstruction unit.
EP-1392001 describes how to organise a control loop in an equalizer system such that self-adaptation is achieved, independently from the transmit amplitude and the transmitted bit pattern. A feed-back control signal is generated from the equalised output of an equalizer filter. Depending on whether the output signal has been under- or over-compensated, the feed-back control signal increases or decreases, such that after a reasonable time the feed-back control signal converges to a value where matched compensation is reached. The control loop is formed by a first means for measuring a short-term-amplitude signal of the output signal, a second means for measuring a long-term-amplitude signal of the output signal and a comparator means for comparing the short-term-amplitude signal and the long-term-amplitude signal, and for determining the evolution of the feed-back control signal.
U.S. Pat. No. 7,180,941 discloses a way to regulate low and high frequency components by comparing low and high frequency components in the signals before and after a slicer digitizer circuit.
EP-1763188 also uses low pass and high pass filtering in its low- and high frequency gain regulation systems with increased precision due to a comparator current being adapted in time.
The above documents describe detectors for tuning low and high frequency gain that are using filters based on classical first and/or second order filters. When not using large chip-scale inductors these filters inevitably reduce signal amplitudes. These reduced signal amplitudes are then to be compared making the detection susceptible to mismatches in used comparator circuits.
The teachings of the present invention permits the design of improved equalizer filters and equalizer filtering methods for use in single or multistage equalizer systems which provide restoration of data signals transmitted over a communication channel showing high-frequency attenuation behaviour, high-frequency being defined with respect to the data rate of the transmitted signals. More in particular, structures and methods are provided that allow good detection mechanisms for lower and higher frequency gain loops that are very tolerant for transistor mismatches in the equalizer circuits.
Allowing mismatches in pairs of transistors in an equalizer circuit is important when aiming at high-speed operation.
Further, when aiming at low-voltage equalizers, given transistor mismatch voltages become relatively more important since inevitably one will have to work with smaller internal high-speed data signals. In this case, a higher tolerance to transistor mismatches increases the production yield significantly. Finally, combined high-speed and low-voltage operation is what many equalizers require in present day and future CMOS technologies, thereby operating at voltages smaller than—or equal to—1.2V and at high speed bit rates, i.e. at 100 Mbps to 100 Gbps.
In a first aspect, the present invention provides an equalizer filter, more particularly an adaptive equalizer filter, for compensating a received distorted or dispersive signal for frequency dependent signal modifications introduced by a transmission channel. The equalizer filter may be a single stage or multi-stage filter, i.e. it may comprise at least one compensation stage. A compensation stage has at least one gain parameter. Different compensation stages may have different gain parameters, e.g. one compensation stage may be tunable in high frequency while another compensation stage may be tunable in low frequency. The equalizer filter according to embodiments of the first aspect of the present invention may comprise at least one switch, the at least one switch being for changing at least one of the gain parameters in time in function of the compensated signal. In embodiments of the present invention, for every gain parameter a switch may be present in the equalizer filter.
An equalizer filter according to embodiments of the present invention may furthermore comprise a control circuit for controlling the actuation of the at least one switch so as to control when the at least one gain parameter is changed.
An equalizer filter according to embodiments of the present invention may furthermore comprise storage means for storing the gain parameters. The storage means may for example be a capacitor, e.g. a parasitic capacitance.
An equalizer filter according to embodiments of the present invention may furthermore comprise a detection circuit for detecting from the compensated signal mismatches in at least one of the gain parameters, and for generating a corresponding mismatch detection signal. The mismatch detection signal may instantaneously indicate a required increase or decrease of at least one of the gain parameters.
In an equalizer filter according to embodiments of the present invention, the at least one switch may be adapted to signal through or link through the mismatch detection signal, more particularly for example to a gain parameter storage means, thus updating the at least one gain parameter with the required increase or decrease. The signalling through may be a combination of multiplexing in time and low pass filtering.
The detection circuit may be a rectifying comparator circuit.
The detection circuit may comprise two differential inputs. Each differential input may comprise two input nodes. The detection circuit may be adapted to compare, from each differential input, signals on those input nodes which are highest in voltage.
The detection circuit may comprise a comparator.
The detection circuit may be adapted for comparing input and output signals of a limiting amplifier.
The detection circuit may furthermore comprise at least one rectifier.
In a second aspect, the present invention provides an equalizer filter, more particularly an adaptive equalizer filter, for compensating a received distorted or dispersive signal for frequency dependent signal modifications introduced by a transmission channel. The equalizer filter according to embodiments of the present invention comprises at least one compensation stage. There are at least two gain parameters for the compensation stages, and each compensation stage has at least one gain parameter. The equalizer filter according to embodiments of the present invention comprises a gain parameter updating circuit for updating the at least two gain parameters, and a detection circuit for detecting, from the compensated signal, mismatches in the gain parameters. The detection circuit may be adapted for generating a mismatch detection signal, the mismatch detection signal being common for the at least two gain parameters.
It is an advantage of embodiments of the present invention that, due to the detection signal being common for the at least two gain parameters, potential offsets, which may be introduced on the gain parameters e.g. by amplifying signals, are introduced equally for all gain parameters to be changed.
In an equalizer filter according embodiments of the present invention, the mismatch detection signal may instantaneously indicate a required increase or decrease of the gain parameters.
In an equalizer filter according to embodiments of the present invention, the detection circuit may comprise two differential inputs. Each differential input may comprise two input nodes, and the detection circuit may be adapted to compare, from each differential input, signals on those input nodes which are highest in voltage.
In an equalizer filter according to embodiments of the present invention, the detection circuit may furthermore comprise at least one rectifier for rectifying signals on the differential inputs.
The detection circuit may comprise a comparator for comparing signals on the differential inputs.
The detection circuit may be adapted for comparing input and output signals of a limiting amplifier.
An equalizer filter according to embodiments of the present invention may furthermore comprise at least one switch, the at least one switch being for changing at least one of the gain parameters in time in function of the compensated signal. The at least one switch may be adapted to signal through or link through the mismatch detection signal for updating the at least one gain parameter with the required increase or decrease.
In a third aspect, the present invention provides an equalizer system for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel. The equalizer system according to the third aspect comprises an equalizer filter according to any of the embodiments of the equalizer filters of the first or second aspects of the present invention.
In a fourth aspect, the present invention provides a method for compensating a distorted signal for frequency dependent signal modifications introduced by a transmission channel, the signal having an amplitude. The method comprises receiving a distorted signal, providing at least two gain parameters and compensating said distorted signal by amplifying the received signal in at least one amplifying compensation stage using the provided gain parameters, and outputting a compensated signal. The method according to embodiments of the present invention furthermore comprises, in function of the amplitude of the compensated signal, changing at least one of the gain parameters multiplexed in time. A plurality of gain parameters may be provided to the at least one at least one compensating stage, and each of the plurality of gain parameters may be changed multiplexed in time, e.g. they may be changed one after the other. In alternative embodiments, at least one of the gain parameters may be changed continuously, depending on the amplitude of the compensated signal, and at least another one of the gain parameters may be changed intermittently, multiplexed in time.
Changing the gain parameters may comprise generating a mismatch detection signal from the compensated signal and multiplexing that mismatch detection signal in time for adapting at least one of the gain parameters. The mismatch detection signal may instantaneously indicate a required increase or decrease of at least one of the gain parameters.
Generating a mismatch detection signal may comprise comparing the compensated signal with an amplified and/or saturated version of the compensated signal.
A method according to embodiments of the present invention may furthermore comprise using the mismatch detection signal for changing at least one of the gain parameters. Changing the gain parameters may comprise multiplexing at least one switch in time, for multiplexed signalling through the mismatch detection signal to at least one of the gain parameters.
A method according to embodiments of the present invention may furthermore comprise storing the at least two gain parameters in a memory element, e.g. a capacitor, such as for example a parasitic capacitance.
In a fifth aspect, the present invention provides a method for compensating a distorted signal for frequency dependent signal modifications introduced by a transmission channel, the signal having an amplitude. The method comprises receiving a distorted signal, providing at least two gain parameters and compensating said distorted signal by amplifying the received signal in at least one amplifying compensation stage using the provided gain parameters, outputting a compensated signal, and detecting from the compensated signal, mismatches in the gain parameters and updating the at least two gain parameters. Detecting mismatches in the gain parameters may be adapted in accordance with embodiments of the present invention for generating a mismatch detection signal common for the at least two gain parameters.
Updating the at least two gain parameters may comprise supplying the common detection signal to each of the at least two gain parameters, and multiplexing it in time for at least one of the gain parameters, i.e. applying or not applying it in time, so as to changing the gain parameters in time in function of the compensated signal. Updating the at least two gain parameters may comprise multiplexing the common detection signal between the at least two gain parameters.
The mismatch detection signal may instantaneously indicate a required increase or decrease of at least one of the gain parameters. Updating the at least two gain parameters may comprise signalling through the mismatch detection signal for updating the gain parameters with the required increase or decrease.
These and other characteristics, features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for the sake of example only, without limiting the scope of the invention. The reference figures quoted below refer to the attached drawings.
In the different figures, the same reference signs refer to the same or analogous elements.
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.
It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Similarly, it is to be noticed that the term “coupled” should not be interpreted as being restricted to direct connections only. Thus, the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device. B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.
The invention will be described by a detailed description of several embodiments of the invention. It is obvious that other embodiments of the invention can be configured by a person skilled in the art without departing form the true spirit or technical teaching of the invention, the invention therefore being limited only by the terms of the appended claims. It will be clear for a person skilled in the art that the present invention is also applicable to similar circuits that can be configured in any transistor technology, including for example, but not limited thereto, CMOS, BICMOS and SiGe BICMOS. It will furthermore be clear that similar merits of the invention can be obtained when single-ended signals are implemented as differential signals and vice-versa, without departing from the true spirit of the invention.
The adaptive equalizer 41 according to embodiments of the present invention shows at least one amplifying compensation stage. In the embodiment illustrated in
The signal to be recovered enters at the input of the first amplifying compensation stage 43, at the input node comprising input terminals inA, inB. Typically, a signal is supplied to the input node of the equalizer 41 that has more or less suffered from frequency attenuation from a transmission channel with limited bandwidth characteristics, whereby higher frequencies are more attenuated than lower frequencies. The input signal is input in the equalizer 41 at the input node, which serves as the differential input node of the amplifying compensation stage 43. Amplifying compensation stages 43, 44, 45, 46 are used to make an “as good as possible” digital data stream at the output node of the last amplifying compensation stage 46, also the entrance of the limiting amplifier 47, by analog inverse filtering. The amplifying compensation stages 43, 44, 45, 46 can be any type of suitable compensation stages, e.g. compensation stages with a fixed higher frequency gain compensation, programmable compensation stages, tunable compensation stages. Examples of amplifying compensation stages, and how they are driven can be found in literature by the person skilled in the art, including in WO 2004/73274, EP-1622285, EP-1763188. Such stages can be tuned sequentially, or in parallel. For some applications and depending on the bit rate of the envisaged equalizer it can also be sufficient to work with a single stage.
After having traveled through the compensation stages 43, 44, 45, 46, the signal arrives at the limiting amplifier 47 for amplifying and/or digitizing the output of the last amplifying compensation stage 46. This limiting amplifier 47 may itself have a fixed maximum output amplitude.
After the limiting amplifier 47, an output circuit 48 is provided. Output circuit 48 has an output node comprising differential output terminals outA, outB, and can include any useful stage following an equalizing filter in an equalizer system, including but not limited to a bit-slicer, a limiting amplifier, a DC-restoring system or a Schmitt-trigger, and possibly an output driver stage, all known by a person skilled in the art. The output circuit 48 together with the equalizer 41 are part of an equalizer system. This output circuit 48 may be provided to compensate amplitude variations obtained by equalizing, at the expense of very little or no additional jitter.
To obtain an equalizer 41 that is robust to transmit amplitude variations, the amplifying compensation stages 43, 44, 45, 46 preferably each have at least one gain parameter that tunes the low frequency gain, and another gain parameter that tunes the high frequency gain. In
This signal enters the limiting amplifier 47 where it is amplified by a pre-defined amplification factor over the full useful frequency band, e.g. by 4 to 6 dB. The limiting amplifier 47 has a limited capability of amplification: there is a limitation to the output amplitude, e.g. to 250 mV for a 1V technology, or to 700 mV for a 3.3V chip technology. This limiting amplifier 47 can be a current mode logic stage (CML-stage) whereby this limitation of the output amplitude gives a digitizing behaviour when the input waveform itself had already a large enough amplitude. Due to its limited output amplitude, possible overshoots present at the input of the limiting amplifier 47 will be clipped in the output signal when these overshoots would be too large to be accommodated by the limiting amplifier 47. It is advised to use a single stage limiting amplifier 47 for good operation of embodiments of the present invention, although the present invention is not limited thereto. The output signal of the limiting amplifier 47 is present between the nodes postA and postB. This signal may be further amplified, and brought to a node with lower impedance than any previous node in the signal path, in order to form the digital output of the equalizer 41. The bringing to a node with lower impedance may be done to match the impedance of attached transmission lines. An output driver may typically be needed in the output circuit 48 for driving low impedance transmission lines.
The at least one gain parameter is changed, in accordance with embodiments of the present invention, in function of the compensated signal at the output nodes preA, preB of the last compensation stage 46 and optionally in function of the signal at the output nodes postA, postB of the limiting amplifier stage 47. If the compensated signal amplitude is too high, the gain parameters will be lowered, and if the compensated signal amplitude is too low, the gain parameters will be raised correspondingly.
In order to determine the change of the gain parameters, a detection mechanism 42 for determining the required high frequency gain and low frequency gain is provided in accordance with embodiments of the present invention. The detection mechanism 42 may be a rectifying comparator mechanism. In the embodiment of the present invention illustrated in
The control of the gain parameters is performed in updating mechanism 40 as follows. During a pre-determined period after a zero-crossing of the data, e.g. on the node preA, preB, the signal on the output node adjust_gain of the detection circuit 42, in the embodiment illustrated in
The connect control block 33 generates the enable signals connect_HF and connect_LF for first and second switches 34, 35, based on the values of the compensated signal at the output nodes preA, preB of the last compensation stage 46. This is illustrated in
The HFgain and LFgain nodes are preferably capacitively coupled to the ground, by means of a (parasitic) capacitor CHF and CLF, respectively, to average out the impulses given to them through the first and second switches 34, 35. In that way, they become the dominant pole in the HFgain and LFgain tuning loops. The first and second switches 34, 35 may have a large resistive value in their conductive state (e.g. by using minimal area transistors), such that finding the optimal HFgain and LFgain values gets averaged out over more than 1 edge, e.g. 10 to 10000 edges. The lower this number of edges, the quicker the self adaptive equalizer 41 will converge to its final destination, however the more it can become dependent on single-event signal errors. Since in most applications, the start-up speed is not an issue, it is advised to rely on a larger set of edges, in other words, to average out over a longer period.
An alternative to the proposed system, as shown hereinabove, is to work with small currents that drive the voltages on the capacitors CHF and CLF upwards and/or downwards. The driving currents then have a duration determined by the duration of the just-crossed period 53, and have an amplitude dependent on the amplitude of the compensated signal at the output nodes preA, preB of the amplifying compensation stages.
Other detection circuits 42 providing similar merits can also be designed by a person skilled in the art, without departing from the scope of the invention as defined by the appended claims. However, the combination of comparing the highest of the signals in a double differential stage as in
Curve 16 is the connect_HF signal that shows when the switch 34 towards the HFgain node has to become conductive. Curve 17 is the connect_LF signal that shows when the switch 35 towards the LFgain node has to become conductive. As it is shown, the “just crossed period 19” is not precisely matching the periods when signal 15 on the node adjust_gain is digitally LOW. This shows that there is some crosstalk between the two error detectors for the high frequency gain and the low frequency gain. In this case, the high frequency gain HFgain updating is not only determined by the high frequency gain HFgain being too LOW, but also by the low frequency gain LFgain being too HIGH. This is not a problem, since after some time the low frequency gain error will go to zero, and by then, the high frequency gain detector will be depending solely on the its own high frequency gain error. The exact “just crossed period” length 19 is thus not so critical. It is suggested to be taken between 0.3 and 3 bits period, in particular cases between 0.5 and 1 bits period.
In general, this way of operating the detection for low frequency gain LFgain and high frequency gain HFgain updating is very robust with respect to mismatches in transistor pairs. This is due to the fact that the gain adjustment signals are split into error signals for high frequency gain and low frequency gain updating only late in the procedure: in the embodiments illustrated, signals are first rectified and amplified in the rectifying comparator circuit 42, before splitting them into error signals for the high frequency gain HFgain and low frequency gain LFgain updating. At the place the signals are split (at the first and second switches 34, 35) the signals are very large with respect to possible transistor offsets due to this prior amplification. Before the switches 34, 35, a mismatch, e.g. in the comparator 32, is not harming the balance between the low frequency gain LFgain and the high frequency gain HFgain: such mismatch will only result in a different amplitude of the EYE diagram before and after the limiting amplifier 47: both low frequency LFgain and high frequency gain HFgain will be tuned to a too HIGH or a too LOW value (depending on the sign of the offset mismatch), but low frequency gain LFgain and high frequency gain HFgain will be still in balance which each other.
An option is to make the “just crossed period” length 19 dependable on the features in the high-speed data signal e.g. “preA-preB” at the level of the input of the limiting amplifier 47. One can for example choose to make the period length 19 adapt to the shortest measured HIGH or LOW periods in this data signal. In that way a good equalizing precision can be obtained over a large frequency (or bit-) range of operation. Another option is to make the “just crossed period” length 19 dependable on internal signal values, including on HFgain, LFgain or bitrate. In the latter case, a sensor may be provided that measures the bit rate. Commercial broadband equalizers require that at lower bit rate also longer cable lengths can be equalized. One can thus anticipate that, when having high compensation levels (=a relative high high-frequency gain HFgain voltage), longer transmission cable is attached to the input of the equalizer 41, and that a lower bit rate is to be handled. The “just crossed period” length 19 can then be increased accordingly.
At high speed, with respect to the used chip-technology, the detection circuit 42, e.g. the rectifying comparator like in
Analogously to what is explained with respect to
For some less demanding applications, it can be sufficient to provide a limited number of switches in the updating mechanism 40, the limited number of switches being less than the number of gain parameters used in the compensation stages. As an example only, an equalizer 41 is illustrated in
In the update mechanism 40 a limited number of switches, the number being smaller than the number of gain parameters used in the amplifying compensation stage, e.g. only one switch 39, may be present, as for example illustrated in
It is to be understood that although preferred embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope and spirit of this invention.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/BE07/00090 | 7/20/2007 | WO | 00 | 1/19/2010 |
