Patent Grant
10732856
The disclosed embodiments relate generally to memory systems, and in particular, to ranking memory portions of a storage device (e.g., blocks of a flash memory device) using one or more metrics determined from memory erase operations.
Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information.
Writing data to some types of non-volatile memory, including flash memory requires erasing one or more portions of the memory before writing the data to those portions of the memory. As memory (e.g., flash memory cells) goes through repeated cycles of writes and erasures, it gets worn by the application of repeated, high voltage erase operations. Therefore, it would be desirable to rank portions of a flash memory device based on an erase health metric (i.e., one or more metrics determined from memory erase operations).
Various embodiments of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of various embodiments are used to rank non-volatile memory portions of a storage device.
So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various embodiments, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.
In accordance with common practice the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.
The various implementations described herein include systems, methods and/or devices used to enable an erase health metric to rank memory portions in memory devices. Some implementations include systems, methods and/or devices to rank the memory portions of a storage device in order to preserve memory life of the storage device.
(A1) More specifically, some embodiments include a method for determining a respective health metric for each of a plurality of non-volatile memory portions of a non-volatile memory device by combining an erase difficulty metric and an age metric. Determining the respective health metric includes: (1) calculating the erase difficulty metric for a respective non-volatile memory portion (e.g., a block), and (2) determining the age metric for the respective non-volatile memory portion based on a total number of erase operations performed on the respective non-volatile memory portion during a lifespan of the non-volatile memory device. The erase difficulty metric for the respective non-volatile memory portion is based on one or more erase performance metrics obtained during one or more erase phases of an erase operation performed on the respective non-volatile memory portion. After determining the respective erase health metric for each of the plurality of non-volatile memory portions, the method further includes ranking non-volatile memory portions, including at least the plurality of non-volatile memory portions of the non-volatile memory device, in accordance with the determined respective erase health metrics. The method also includes selecting a non-volatile memory portion of the plurality of non-volatile memory portions in accordance with the ranking of the non-volatile memory portions, and writing data to the selected non-volatile memory portion.
(A2) In some embodiments of the method of A1, the ranking includes determining a highest ranked non-volatile memory portion of the non-volatile memory device, and writing data to the selected non-volatile memory portion comprises writing data to the highest ranked non-volatile memory portion.
(A3) In some embodiments of the method of any of A1-A2, the one or more erase performance metrics include: (1) a number (also referred to as a count) of successive erase phases required to satisfy a stopping condition during the erase operation on the respective non-volatile memory portion, and (2) a change in voltage between an initial erase voltage used during an initial erase phase of the erase operation on the respective non-volatile memory portion, and a final erase voltage used in a final erase phase of the erase operation on the respective non-volatile memory portion.
(A4) In some embodiments of the method of any of A1-A3, calculating the erase difficulty metric includes calculating the erase difficulty metric in accordance with: (1) a first normalization coefficient associated with the number of successive erase phases of the erase operation performed on the respective non-volatile memory portion; and (2) a second normalization coefficient associated with the total number of erase operations performed on the respective non-volatile memory portion during the lifespan of the non-volatile memory device. In some embodiments, the first normalization coefficient is inversely related to the second normalization coefficient.
(A5) In some embodiments of the method of any of A1-A4, each of the one or more erase phases of the erase operation performed on the respective non-volatile memory portion includes: (1) performing an erase phase using an erase voltage, and (2) determining an erase statistic for the performed erase phase. In some embodiments, the erase statistic for the performed erase phase corresponds to a count of non-erased memory cells in the respective non-volatile memory portion having cell voltages that fail (after performing the erase phase) to satisfy a criterion corresponding to the performed erase phase.
(A6) In some embodiments of the method of any of A1-A5, the one or more erase performance metrics include a weighted sum of counts. Each count in the weighted sum of counts comprises an erase statistic for the respective non-volatile memory portion after each of two or more of the successive erase phases.
(A7) In some embodiments of the method of any of A3-A6, calculating the erase difficulty metric for the respective non-volatile memory portion includes calculating a weighted sum of two or more of erase performance metrics for the respective non-volatile memory portion.
(A8) In some embodiments of the method of any of A1-A7, the method further includes, after ranking the non-volatile memory portions, generating an ordered list of non-volatile memory portions of the non-volatile memory device based on their respective erase difficulty metrics.
(A9) In some embodiments of the method of any of A1-A8, the ranking of the non-volatile memory portions includes ranking two or more non-volatile memory portions having a same erase health metric in accordance with a tie-breaker metric. The tie-breaker metric for each non-volatile memory portion of the two or more non-volatile memory portions is based at least in part of the total number of erase operations performed on the non-volatile memory portion during the lifespan of the non-volatile memory device.
(A10) In some embodiments of the method of any of A1-A9, the data includes one or more data streams, and the writing of the data to the selected non-volatile memory portion further includes writing a first data stream of the one or more data streams to the selected non-volatile memory portion of the non-volatile memory device.
Numerous details are described herein in order to provide a thorough understanding of the example implementations illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.
Computer system 110 is coupled to storage controller 124 through data connections 101. However, in some embodiments computer system 110 includes storage controller 124, or a portion of storage controller 124, as a component and/or as a subsystem. For example, in some embodiments, some or all of the functionality of storage controller 124 is implemented by software executed on computer system 110. Computer system 110 may be any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smart phone, a gaming device, a computer server, or any other computing device. Computer system 110 is sometimes called a host, host system, client, or client system. In some embodiments, computer system 110 is a server system, such as a server system in a data center. In some embodiments, computer system 110 includes one or more processors, one or more types of memory, a display and/or other user interface components such as a keyboard, a touch-screen display, a mouse, a track-pad, a digital camera, and/or any number of supplemental I/O devices to add functionality to computer system 110. In some embodiments, computer system 110 does not have a display and other user interface components.
Storage medium 132 is coupled to storage controller 124 through connections 103. Connections 103 are sometimes called data connections, but typically convey commands in addition to data, and optionally convey metadata, error correction information and/or other information in addition to data values to be stored in storage medium 132 and data values read from storage medium 132. In some embodiments, however, storage controller 124 and storage medium 132 are included in the same device (i.e., an integrated device) as components thereof. Furthermore, in some embodiments, storage controller 124 and storage medium 132 are embedded in a host device (e.g., computer system 110), such as a mobile device, tablet, other computer or computer controlled device, and the methods described herein are performed, at least in part, by the embedded storage controller. Storage medium 132 may include any number (i.e., one or more) of memory devices (e.g., NVM 134-1, NVM 134-2 through NVM 134-n) including, without limitation, persistent memory or non-volatile semiconductor memory devices, such as flash memory device(s). For example, flash memory device(s) can be configured for enterprise storage suitable for applications such as cloud computing, for database applications, primary and/or secondary storage, or for caching data stored (or to be stored) in secondary storage, such as hard disk drives. Additionally and/or alternatively, flash memory device(s) can also be configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop, and tablet computers.
Memory devices (e.g., NVM 134-1, NVM 134-2, etc.) of storage medium 132 include addressable and individually selectable blocks, such as selectable portion of storage medium 136 (also referred to herein as selected portion 136). In some embodiments, the individually selectable blocks (sometimes called erase blocks) are the minimum size erasable units in a flash memory device. In other words, each block contains the minimum number of memory cells that can be erased simultaneously. Each block is usually further divided into a plurality of pages and/or word lines, where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some embodiments (e.g., using some types of flash memory), the smallest individually accessible unit of a data set, however, is a sector, which is a subunit of a page. That is, a block includes a plurality of pages, each page contains a plurality of sectors, and each sector is the minimum unit of data for writing data to or reading data from the flash memory device.
In some embodiments, storage controller 124 includes a management module 121-1, a host interface 129, a storage medium I/O interface 128, and additional module(s) 125. Storage controller 124 may include various additional features that have not been illustrated for the sake of brevity and so as not to obscure pertinent features of the example embodiments disclosed herein, and a different arrangement of features may be possible. Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 132 though connections 103. In some embodiments, storage medium I/O 128 includes read and write circuitry, including circuitry capable of providing reading signals to storage medium 132 (e.g., reading threshold voltages for NAND-type flash memory).
In some embodiments, management module 121-1 includes one or more processing units 122-1 (sometimes herein called CPUs, processors, or hardware processors, and sometimes implemented using microprocessors, microcontrollers, or the like) configured to execute instructions in one or more programs (e.g., in management module 121-1). In some embodiments, the one or more CPUs 122-1 are shared by one or more components within, and in some cases, beyond the function of storage controller 124. Management module 121-1 is coupled to host interface 129, additional module(s) 125 and storage medium I/O 128 in order to coordinate the operation of these components. In some embodiments, one or more modules of management module 121-1 are implemented in management module 121-2 of computer system 110. In some embodiments, one or more processors of computer system 110 (not shown) are configured to execute instructions in one or more programs (e.g., in management module 121-2). Management module 121-2 is coupled to storage device 120 in order to manage the operation of storage device 120.
Additional module(s) 125 are coupled to storage medium I/O 128, host interface 129, and management module 121-1. As an example, additional module(s) 125 may include an error control module to limit the number of uncorrectable errors inadvertently introduced into data during writes to memory or reads from memory. In some embodiments, additional module(s) 125 are executed in software by the one or more CPUs 122-1 of management module 121-1, and, in other embodiments, additional module(s) 125 are implemented in whole or in part using special purpose circuitry (e.g., to perform data encoding and decoding functions). In some embodiments, additional module(s) 125 are implemented in whole or in part by software executed on computer system 110.
Memory controller 126 is coupled to host interface 129, and non-volatile memory controllers 130. In some implementations, during a write operation, memory controller 126 receives data from computer system 110 through host interface 129 and during a read operation, memory controller 126 sends data to computer system 110 through host interface 129. Further, host interface 129 provides additional data, signals, voltages, and/or other information needed for communication between memory controller 126 and computer system 110. In some embodiments, memory controller 126 and host interface 129 use a defined interface standard for communication, such as double data rate type three synchronous dynamic random access memory (DDR3). In some embodiments, memory controller 126 and non-volatile memory controllers 130 use a defined interface standard for communication, such as serial advance technology attachment (SATA). In some other implementations, the device interface used by memory controller 126 to communicate with non-volatile memory controllers 130 is SAS (serial attached SCSI), or other storage interface. In some implementations, memory controller 126 includes one or more processing units (sometimes herein called CPUs, processors, or hardware processors, and sometimes implemented using microprocessors, microcontrollers, or the like) configured to execute instructions in one or more programs (e.g., in memory controller 126). In some implementations, the one or more processors are shared by one or more components within, and in some cases, beyond the function of memory controller 126.
In some embodiments, the non-volatile memory controllers 130 include management modules 131 (e.g., management module 121-1,
In some embodiments, the erase module 216 includes a phase erase module 220 that is used for performing erase operations on portions (e.g., selectable portion 136) of storage medium 132. In some embodiments, the phase erase module 220 performs an erase operation in successive phases or stages (i.e., the single erase operation is divided into phases). Further, parameters associated with each subsequent phase of the erase operation are adjusted in accordance with metrics of performance of a previous phase, referred to hereinafter as erase statistics. For example, in some embodiments, a voltage used for a subsequent phase will be adjusted in accordance with the erase statistics of the previous phase. Erase statistics are discussed in further detail below.
In some embodiments, the erase module 216 includes an erase statistic module 222 that is used for determining an erase statistic for each erase phase of an erase operation. For example, in some embodiments, the erase statistic for a particular erase phase will correspond to a measurement of success in erasing a portion of memory in storage medium 132.
In some embodiments, the erase module 216 includes an erase voltage adjustment module 224 that is used for adjusting a voltage applied during an erase operation. For example, in some embodiments, the erase voltage adjustment module 224 determines an erase voltage increment, by which the erase voltage is increased from one erase phase to the next, in accordance with the erase statistic for the last completed erase phase. As described in more detail below, when the erase statistic for the last completed erase phase indicates that the last completed erase phase was successful, the erase voltage increment is a default value (e.g., a fixed value, or a value read from a table of default erase voltage increments). However, when the erase statistic for the last completed erase phase indicates that the last completed erase phase was not successful, the erase voltage increment is computed based on the erase statistic for the last completed erase phase (e.g., by applying a mathematical function of the erase statistic for the last completed erase phase).
Each of the above identified elements may be stored in one or more of the previously mentioned memory devices that together form memory 206, and corresponds to a set of instructions for performing a function described above. The above identified modules or programs (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 206 may store a subset of the modules and data structures identified above. Furthermore, memory 206 may store additional modules and data structures not described above. In some embodiments, the programs, modules, and data structures stored in memory 206, or the computer readable storage medium of memory 206, provide instructions for implementing respective operations in the methods described below with reference to
Although
As discussed below with reference to
Flash memory devices utilize memory cells to store data as electrical values, such as electrical charges or voltages. Each flash memory cell typically includes a single transistor with a floating gate that is used to store a charge, which modifies the threshold voltage of the transistor (i.e., the voltage needed to turn the transistor on). The magnitude of the charge, and the corresponding threshold voltage, is used to represent one or more data values. In some embodiments, during a read operation, a reading threshold voltage is applied to the control gate of the transistor and the resulting sensed current or voltage is mapped to a data value.
The terms “cell voltage” and “memory cell voltage,” in the context of flash memory cells, typically mean the threshold voltage of the memory cell, which is the minimum voltage that needs to be applied to the gate of the memory cell's transistor in order for the transistor to conduct current. Similarly, reading threshold voltages (sometimes also called reading signals, reading voltages, and/or read thresholds) applied to flash memory cells are gate voltages applied to the gates of the flash memory cells to determine whether the memory cells conduct current at that gate voltage. In some embodiments, when a flash memory cell's transistor conducts current at a given reading threshold voltage, indicating that the cell voltage is less than the reading threshold voltage, the raw data value for that read operation is a “1,” and otherwise the raw data value is a “0.”
Sequential voltage ranges 301 and 302 between voltages VSS and Vmax are used to represent corresponding bit values “1” and “0,” respectively. Each voltage range 301, 302 has a respective center voltage V1 301b, V0 302b. As described below, in many circumstances the memory cell current sensed in response to an applied reading threshold voltages is indicative of a memory cell voltage different from the respective center voltage V1 301b or V0 302b corresponding to the respective bit value written into the memory cell. Errors in cell voltage, and/or the cell voltage sensed when reading the memory cell, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the memory cell and the time a read operation is performed to read the data stored in the memory cell. For ease of discussion, these effects are collectively described as “cell voltage drift.” Each voltage range 301, 302 also has a respective voltage distribution 301a, 302a that may occur as a result of any number of a combination of error-inducing factors, examples of which are identified above.
In some implementations, a reading threshold voltage VR is applied between adjacent center voltages (e.g., applied proximate to the halfway region between adjacent center voltages V1 301b and V0 302b). Optionally, in some implementations, the reading threshold voltage is located between voltage ranges 301 and 302. In some implementations, reading threshold voltage VR is applied in the region proximate to where the voltage distributions 301a and 302a overlap, which is not necessarily proximate to the halfway region between adjacent center voltages V1 301b and V0 302b.
In order to increase storage density in flash memory, flash memory has developed from single-level (SLC) cell flash memory to multi-level cell (MLC) flash memory so that two or more bits can be stored by each memory cell. As discussed below with reference to
Sequential voltage ranges 311, 312, 313, 314 between voltages VSS and Vmax are used to represent corresponding bit-tuples “11,” “01,” “00,” “10,” respectively. Each voltage range 311, 312, 313, 314 has a respective center voltage 311b, 312b, 313b, 314b. Each voltage range 311, 312, 313, 314 also has a respective voltage distribution 311a, 312a, 313a, 314a that may occur as a result of any number of a combination of factors, such as electrical fluctuations, defects in the storage medium, operating conditions, device history (e.g., number of program-erase (PE) cycles performed during the lifetime of the device or lifetime of a respective memory portion, and/or number of read operations performed since the last erase operation on the respective memory portion), and/or imperfect performance or design of write-read circuitry.
Ideally, during a write operation, the charge on the floating gate of the MLC would be set such that the resultant cell voltage is at the center of one of the ranges 311, 312, 313, 314 in order to write the corresponding bit-tuple to the MLC. Specifically, the resultant cell voltage would be set to one of V11 311b, V01 312b, V00 313b and V10 314b in order to write a corresponding one of the bit-tuples “11,” “01,” “00” and “10.” In reality, due to the factors mentioned above, the initial cell voltage may differ from the center voltage for the data written to the MLC.
Reading threshold voltages VRA, VRB and VRC are positioned between adjacent center voltages (e.g., positioned at or near the halfway point between adjacent center voltages) and, thus, define threshold voltages between the voltage ranges 311, 312, 313, 314. Optionally, in some implementations, the reading threshold voltages are located between adjacent voltage ranges 311, 312, 313, 314. In some implementations, reading threshold voltages VRA, VRB, and VRC are applied in the regions proximate to where adjacent voltage distributions 311a, 312a, 313a, 314a overlap, which are not necessarily proximate to the halfway regions between adjacent center voltages V11 311b, V01 312b, V00 313b and V10 314b. In some implementations, the reading threshold voltages are selected or adjusted to minimize error. During a read operation, one of the reading threshold voltages VRA, VRB and VRC is applied to determine the cell voltage using a comparison process. However, due to the various factors discussed above, the actual cell voltage, and/or the cell voltage received when reading the MLC, may be different from the respective center voltage V11 311b, V01 312b, V00 313b or V10314b corresponding to the data value written into the cell. For example, the actual cell voltage may be in an altogether different voltage range, strongly indicating that the MLC is storing a different bit-tuple than was written to the MLC. More commonly, the actual cell voltage may be close to one of the read comparison voltages, making it difficult to determine with certainty which of two adjacent bit-tuples is stored by the MLC.
Errors in cell voltage, and/or the cell voltage received when reading the MLC, can occur during write operations, read operations, or due to “drift” of the cell voltage between the time data is written to the MLC and the time a read operation is performed to read the data stored in the MLC. For ease of discussion, sometimes errors in cell voltage, and/or the cell voltage received when reading the MLC, are collectively called “cell voltage drift.”
One way to reduce the impact of a cell voltage drifting from one voltage range to an adjacent voltage range is to gray-code the bit-tuples. Gray-coding the bit-tuples includes constraining the assignment of bit-tuples such that a respective bit-tuple of a particular voltage range is different from a respective bit-tuple of an adjacent voltage range by only one bit. For example, as shown in
Although the description of
It is noted that each voltage level shown in
Subsequent to the first erase phase, the storage device (during an erase verify operation or optionally a read operation) determines the states of the memory cells in the selected portion 136 of storage medium 132 by applying a first-phase erase verify 412 (e.g., applying a reading threshold voltage as discussed above with reference to
In some embodiments, the storage device determines the number of non-erased memory cells 414, after the first erase phase, and determines whether that number satisfies a first erase phase threshold number of non-erased memory cells (also referred to as an erase phase threshold). For example, if the first erase phase threshold number of non-erased memory cells is, say, 33% of the memory cells in the selected portion 136, the number of non-erased memory cells 414, after the first erase phase, satisfies the first erase phase threshold number of non-erased memory cells if the number of non-erased memory cells 414 is less than 33%. Stated another way, if the number of non-erased memory cells after an erase phase is less than the corresponding threshold number, then the phase-specific threshold number is satisfied.
Subsequent to the second erase phase, the storage device (during an erase verify operation or optionally a read operation) determines the states of the memory cells in the selected portion 136 of storage medium 132 by applying an second-phase erase verify or reading threshold voltage 422 to the selected portion 136. Memory cells having a cell voltage below (i.e., left of) the erase verify voltage 422 are said to satisfy a criterion for the second erase phase, whereas memory cells 424 having a cell voltage above (i.e., right of) the erase verify voltage 422 are said to not satisfy (or fail) the criterion for the second erase phase. As discussed above, memory cells 424 are sometimes, for convenience, called “non-erased memory cells.” However, it should be noted that many memory cells that satisfy the criterion for the second erase phase are not truly “erased,” rather they are sufficiently erased to satisfy the criterion for the second erase phase.
In some embodiments, the storage device determines the number of non-erased memory cells 424, after the second erase phase, and determines whether that number satisfies a second phase threshold number of non-erased memory cells. For example, if the second erase phase threshold number of non-erased memory cells is, say, 66% of the memory cells in the selected portion 136, the number of non-erased memory cells 424, after the second erase phase satisfies the second phase threshold number of non-erased memory cells if the number of non-erased memory cells 424 is less than 66%. Stated another way, if the number of non-erased memory cells after an erase phase is less than the corresponding threshold number, then the phase-specific threshold number is satisfied.
It is noted that
In some embodiments, some of the operations (or alternatively, steps) of method 500 are performed at a host system (e.g., computer system 110) that is operatively coupled with the storage device and other operations of method 500 are performed at the storage device. In some of these embodiments, method 500 is governed, at least in part, by instructions that are stored in a non-transitory computer-readable storage medium and that are executed by one or more processors (e.g., hardware processors) of the host system (the one or more processors of the host system are not shown in
For ease of explanation, the following describes method 500 as performed by the storage device (e.g., by storage controller 124 of storage device 120,
The method begins, in some embodiments, when the storage device (e.g., storage device 120,
After initiating performance of the erase operation, the storage device (e.g., storage device 120,
The method further includes the storage device (e.g., storage device 120,
Subsequent to the erase verify operation, the storage device determines if the number of non-erased memory cells satisfies an erase phase threshold for the erase phase. The erase phase threshold is the number (or percentage) of memory cells that should be erased during the erase phase. In one example, after the first erase phase, no more than 50% of the memory cells in the selected portion 136 should be non-erased memory cells. However, if after the first erase phase, 60% of the memory cells in the selected portion 136 are non-erased memory cells, then the number of non-erased memory cells does not satisfy the erase phase threshold for the first erase phase.
It should be understood that, in some embodiments, the erase phase threshold is distinct from the erase operation stop condition during at least the initial phases of the erase operation. In some embodiments, the two are the same during one or more final erase phases of the erase operation.
The method continues, in some embodiments, when the storage device (e.g., storage device 120,
If, however, the erase operation stop condition is satisfied after performing an erase phase, the storage device (e.g., storage device 120,
In accordance with a determination that the erase operation stop condition is not satisfied (508—No), in some embodiments, the storage device (e.g., storage device 120,
In accordance with a determination that the erase operation stop condition is not satisfied (508—No), the storage device (e.g., storage device 120,
ΔErase=function(non-erased memory cell(s) count−erase phase threshold)
Verase(next phase)=Verase(current phase)+ΔErase
where ΔErase is the erase voltage increment, Verase is the erase voltage for a particular erase phase of the erase operation, and “function” is a predefined mathematical function of its argument. In some embodiments, the function is a linear function of the difference between the count of non-erased memory cells and the erase phase threshold, such as A+B*dif, where A is typically equal to or larger than a default erase voltage increment, B is a scaling coefficient, and “dif” is the difference between the count of non-erased memory cells and the erase phase threshold. As discussed above, in some embodiments, the erase phase threshold is the number (or percentage) of memory cells that should be erased during the erase phase.
In some embodiments, the default value is consistent across all erase phases of the erase operation (i.e., erase voltage increases linearly throughout the erase operation if every erase phases is “successful”). In some other embodiments, the default value increases inconsistently between each successive erase phase (e.g., beginning erase phases have small erase voltage increments while later erase phases have larger erase voltage increments, or vice versa).
The method continues (518) with the storage device (e.g., storage device 120,
In some embodiments, the storage device or host system (host system 110,
Subsequent to stopping the erase operation, the storage device (e.g., storage device 120,
In some embodiments, some of the operations (or alternatively, steps) of the method 600 are performed at a host system (e.g., computer system 110,
For ease of explanation, operations of method 600 are explained as being performed by a storage device, but as explained above, it shall be understood that the operations of method 600 may be performed in whole or in part by one or more components of a host system while other portions, if any, of method 600 are performed by one or more components of the storage device.
Method 600 begins, in some embodiments, when the storage device determines whether (602) a trigger condition is satisfied. When the trigger condition is satisfied (602—Yes), the storage device determines erase health metrics for the storage device. In some embodiments, the trigger condition is satisfied after the storage device performs a predefined number of operations (e.g., storage device 120 erases N erase blocks of storage medium 132,
In some embodiments, the trigger condition is satisfied when a predetermined time period (also referred to as a predetermined time frame) expires. In other words, the trigger condition is satisfied after a time period (e.g., ten days or ten minutes) has elapsed since the storage device performed a most recent erase health metric calculation. In some embodiments, the predetermined time frame changes, during the lifespan of the storage device (e.g., the time frame increased or decreases), based on a volume of erase operations being performed on the storage device. In this way, a frequency of erase health metric calculations is a function of the volume of erase operations being performed on the storage device. In some embodiments, satisfying the trigger condition includes satisfying one or more trigger conditions. For example, in order to satisfy the trigger condition, a predetermined time period must elapse and a predefined number of operations must be performed by the storage device.
In accordance with a determination that the trigger condition is not satisfied (602—No), in some embodiments, the storage device continues to perform (604) normal operations (e.g., read, write, and erase operations on the storage medium 132) until the trigger condition is satisfied.
In accordance with a determination that the trigger condition is satisfied (602—Yes), the storage device initiates (606) an erase health metric calculation. In some embodiments, the storage device calculates an erase health metric for each of one or more non-volatile memory portions (e.g., blocks) of the storage device 120. In some embodiments, the storage device calculates an erase health metric for a subset of the memory portions of the storage device 120. For example, erase health metrics are calculated for the subset of the memory portions that were deemed “healthy” during a most recent erase health metric calculation. In another example, erase health metrics are calculated for the subset of the memory portions that were erased since a last time the storage device initiated an erase health metric calculation. In yet another example, erase health metrics are calculated for the subset of the memory portions that were erased at least N times (e.g., two times) since a last time an erase health metric was calculated for those memory portions.
After initiating the erase health metric calculation, the storage device calculates (608) an erase difficulty metric for the one or more memory portions within the storage device 120 for which the calculation was initiated (606). In some embodiments, the storage device calculates the erase difficulty metric using one or more erase performance metrics obtained during one or more recent erase operations performed on each of the memory portions. In some embodiments, the one or more erase performance metrics are based on erase information recorded during performance of method 500 (e.g., record erase information 512,
In some embodiments, an erase phase operation satisfies the erase operation stop condition when substantially all non-volatile memory cells (e.g., bits and/or flash memory cells) in a block (e.g., selected portion of the storage medium 136) are successfully erased. The erase operation stop condition is typically satisfied even if an insignificant amount of memory cells remain in a non-erased state, as further explained above with reference to operation 508 of method 500.
In some embodiments, an erase phase statistic for any given erase phase is the number (or percentage) of non-erased memory cells (e.g., bits and/or flash memory cells) after that erase phase is performed on the selected portion of the storage medium 136, as further explained above with reference to operation 506 of method 500.
In some embodiments, the recorded erase information includes erase information for a particular memory portion from one or more erase operations. For example, in some situations a memory portion (e.g., select portion of storage medium 136) of the storage device will undergo multiple erase operations subsequent to a most recent erase health metric being calculated for the memory portion of storage medium. Consequently, the storage device generates numerous sets of erase performance metrics during the multiple erase operations of the memory portion. As such, in some embodiments, the erase block data structure (e.g., erase block data structure 226,
In some embodiments, in addition to initiating the erase health metric calculation, the storage device determines (610) an age metric for each memory portion (e.g., each block) of the storage device. In some embodiments, the storage device calculates the age metric using erase information recorded during a lifespan of the storage device. In some embodiments, the age metric, for each respective memory portion of the storage device, includes a total number of erase operations performed on the respective memory portion during a lifespan of the storage device.
Next, in some embodiments, method 600 combines (612) the age metric and the erase difficulty metric to determine an erase health metric for the one or more memory portions (e.g., blocks) of the storage device. The erase difficulty metric, as noted above, includes one or more erase performance metrics. In some embodiments, the storage device, in calculating the erase difficulty metric for the one or more memory portions of the storage device, calculates a weighted sum of two or more erase performance metrics for the memory portions.
In some embodiments, the storage device uses one or more coefficients (e.g., coefficients a, b and c in the equation shown below) to normalize the one or more erase performance metrics when combining the age metric and the erase difficulty metric. In this way, the storage device may adjust a significance of a respective erase performance metric or the age metric in determining the erase health metric for a memory portion of the storage device. For example, in some embodiments, the value of the age metric for the memory portion is typically substantially smaller than the value of the erase difficulty metric (e.g., which may be based on the sum of erase statistics for a particular erase operation), or vice versa. As such, the storage device uses the one or more normalizing coefficients to adjust the significance of the age metric to the erase health metric relative to the significance of the erase difficulty metric (or various components of the erase difficulty metric) to the erase health metric, taking into account the value or scale of the age metric and the erase difficulty metric (or the components of the erase difficulty metric). For example, in some embodiments, the storage device multiplies the sum of erase statistics (e.g., non-erased memory cell count) for the particular erase operation by a first coefficient, and multiplies the difference between the final erase voltage and initial erase voltage used during the particular erase operation by a second coefficient. In some embodiments, determining the erase health metric (EHM) for the one or more memory portions of the storage device is represented by the following equation:
EHM=a*Σ[i(non-erased memory cell count(i))]+b*(Vfinal−Vinitial)+c*PE
where a, b and c are coefficients, “i” is an index corresponding to the erase phases, the summation is a summation over the erase phases, Vfinal is a final erase voltage used in a final erase phase of an erase operation on a respective memory portion, Vinitial is an initial erase voltage used during an initial erase phase of the erase operation on the respective memory portion, and PE (program-erase cycles) is the age metric (i.e., a total number of erase operations performed on the respective memory portion during a lifespan of the storage device). It is noted that the first element of the EHM equation, above, is a weighted sum of counts, where each count in the weighted sum of counts is an erase statistic (e.g., the number of non-erased cells) for the respective non-volatile memory portion after each of two or more of the successive erase phases. In this example, each count is weighted by the corresponding erase phase number, and thus the counts of non-erased cells for later erase phases (i.e., counts of non-erased cells after performance of each such erase phase) are more heavily weighted than the counts of non-erased cells for earlier erase phases.
Subsequent to determining the erase health metric for each of the one or more memory portions of the storage device, the storage device ranks (614) the memory portions based on their respective determined erase health metrics. Optionally, the storage device ranks (614) the memory portions based on their respective determined erase health metrics and one or more additional factors or metrics. In some embodiments, the one or more memory portions (e.g., blocks) having erase health metrics (EHM) with low EHM scores are considered the healthiest memory portions (e.g., memory cells in the block were successfully erased with lowest energy input) of the storage device. Consequently, the one or more memory portions with low EHM scores are ranked the highest. It should be understood that the calculated erase health metrics may also be presented such that the high EHM scores are classified as the healthiest memory portions in the storage device. For example, the calculated erase health metrics for each block can be subtracted from say, 100, such that the healthiest memory portions in the storage device have high EHM scores.
In some embodiments, the storage device generates an erase health metric table or list (e.g., an ordered list) that orders the memory portions (e.g., blocks) of the storage device based on their respective determined erase health metrics (e.g., lowest EHM scores ranked highest in the order list). In some embodiments, the storage device assigns a block rank to each block after generating the erase health metric table. In some embodiments, the block having the best erase health metric (e.g., lowest EHM score) obtains a block rank of 1 (i.e., the best block). In some embodiments, or in some circumstances, the “best block” in the generated list is the block that, during previous erase operation(s), was erased using the smallest energy input relative to energy inputs required to erase data from other blocks in the storage device. It should be understood that the ranking of the memory portions typically changes during the lifespan of the storage device as memory portions (e.g., blocks) in the storage device are written to and subsequently erased.
In addition to ranking the memory portions, the storage device typically assigns erased memory portions (e.g., blocks) to a free block list. As indicated above, in some embodiments, each usable block of the storage device is typically assigned to a respective list, such as a free list, open list or closed list, to indicate a current status of the block. In some embodiments, the free list includes blocks with no valid data, the open list includes blocks that are currently “open” for being written to (and thus may have been partially written), and the closed list includes blocks that are not available for writing data to. Thus, the storage device assigns erased blocks, which contain no valid data, to the free list. In some embodiments, the storage device orders blocks “on the free list” in accordance with the rankings determined for the blocks. As such, the ordered list can also be referred to as an ordered free list.
The method continues, in some embodiments, when the storage device selects (616) a memory portion (e.g., a block) of the one or more memory portions based on the rankings, and subsequently writes (618) data to the selected memory portion. In some embodiments, or in some circumstances, the storage device selects the memory portion on the free list having the best erase health metric. In some embodiments, the storage device selects the memory portion for a subsequent write operation based on a type of data (e.g., a data stream) being written to the memory portion. For example, memory portions with EHM scores exceeding a threshold EHM score are reserved for storing data from a first data stream (e.g., a “hot” data stream) while memory portions with EHM scores below the threshold EHM score are used for other write operations, such as storing data from a second data stream (e.g., a “cold” data stream, which is a data stream that is, on average, read less often, and/or overwritten at a slower rate, than the “hot” data stream). In some embodiments, a hot data stream includes data that is overwritten at a higher rate than data in a cold data stream, or that has a predicted or historical overwrite rate that exceeds a predefined threshold overwrite rate. Accordingly, the best blocks (e.g., blocks having low EHM scores) are reserved for storing data in hot data streams to maintain (or increase) the productivity and/or useful lifetime of the storage device. Similarly, the worst blocks (e.g., blocks having high EHM scores) are used to store data in cold data streams.
For ease of explanation, the following describes the method 700 as performed by the storage device (e.g., by storage controller 124 of storage device 120,
With reference to
In some embodiments, as discussed above with reference to
In some embodiments, as discussed above with reference to operation 612 of method 600 (
In some embodiments, as discussed above with reference to operation 612 of method 600 (
In some embodiments, as discussed above with reference to operations 504 and 506 of method 500 (
Method 700 also includes the storage device determining (716) the age metric for the respective non-volatile memory portion based on a total number of erase operations performed on the respective non-volatile memory portion during a lifespan of the memory device. The age metric is further explained above with reference to operation 610 of method 600 (
As discussed above with reference to operation 614 of method 600 (
Further, the storage device selects (724) a non-volatile memory portion (e.g., selectable portion of storage medium 136,
In some embodiments, as discussed above with reference to operations 616 and 618 of method 600 (
Next, in some embodiments, after ranking said non-volatile memory portions, the storage device generates (730) an ordered list of non-volatile memory portions of the non-volatile memory device based on their respective erase difficulty metrics. Generating the ordered list is further explained above with reference to operation 614 of method 600 (
It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, which changing the meaning of the description, so long as all occurrences of the “first contact” are renamed consistently and all occurrences of the second contact are renamed consistently. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true]” or “if [a stated condition precedent is true]” or “when [a stated condition precedent is true]” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art.
This application claims priority to U.S. Provisional Patent Application No. 62/303,244, filed Mar. 3, 2016, which is incorporated by reference in its entirety.
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