Claims
- 1. An error amplifier circuit comprising:
a differential amplifier receiving a first input signal and a second input signal, said differential amplifier generating an output signal on an output terminal indicative of the difference between said first input signal and said second input signal; a cascode gain stage coupled to receive said output signal of said differential amplifier and generating a second output signal, said cascode gain stage being biased by a bias current generated by a current mirror; and an amplifier receiving said second output signal from said cascode gain stage and generating a third output signal; wherein said cascode gain stage is biased by a control signal for causing said current mirror to generate said bias current having substantially constant magnitude over variations in voltage differences of said first input signal and said second input signal.
- 2. The circuit of claim 1, wherein said differential amplifier comprises:
a first transistor having a control terminal coupled to receive said first input signal, a first current handling terminal coupled to a second bias current and a second current handling terminal coupled to a second current mirror; and a second transistor having a control terminal coupled to receive said second input signal, a first current handling terminal coupled to said second bias current and a second current handling terminal coupled to said second current mirror; wherein said second current handling terminals of said first transistor and said second transistor form said output terminal of said differential amplifier.
- 3. The circuit of claim 2, wherein said cascode gain stage comprises:
a third transistor having a control terminal coupled to a first node, a first current handling terminal receiving said bias current and a second current handling terminal coupled to said second current handling terminal of said first transistor of said differential amplifier; a fourth transistor having a control terminal coupled to said first node, a first current handling terminal receiving said bias current and a second current handling terminal coupled to said second current handling terminal of said second transistor of said differential amplifier; a fifth and a sixth transistors forming said current mirror, said fifth and sixth transistors having control terminals coupled to a second node and current handling terminals generating said bias current; a seventh transistor having a control terminal coupled to said second node, a first current handling terminal coupled to a first supply voltage and a second current handling terminal coupled to a third current mirror; said third current mirror having an input terminal receiving said bias current and an output terminal coupled to a third node; a resistor coupled between said first node and said third node; and a reference current source generating a reference current driving said first node; wherein said reference current and said bias current are compared at said first node for generating said control signal at said control terminals of said third and fourth transistors such that said bias current flowing through said third and fourth transistors is substantially constant over variations in voltage differences of said first input signal and said second input signal.
- 4. The circuit of claim 3, wherein said second current mirror of said differential amplifier is coupled to receive a second control signal at said third node.
- 5. The circuit of claim 2, wherein said first and second transistors comprise p-type MOSFET transistors.
- 6. The circuit of claim 3, wherein said third and fourth transistors comprise n-type MOSFET transistors, said fifth, sixth, and seventh transistors comprise p-type MOSFET transistors, and said first supply voltage comprises a Vdd power supply voltage.
- 7. The circuit of claim 1, wherein said amplifier comprises:
a first transistor having a control terminal receiving said output signal from said cascode gain stage, a first current handling terminal coupled to a first supply voltage and a second current handling terminal coupled to a bias current source and providing said output signal; and a resistor and a capacitor connected in series between said control terminal and said second current handling terminal of said first transistor.
- 8. The circuit of claim 7, wherein said bias current source comprises a second transistor having a control terminal receiving a reference voltage, a first current handling terminal coupled to said second current handling terminal of said first transistor and a second current handling terminal coupled to a second supply voltage.
- 9. The circuit of claim 8, wherein said first transistor comprises a p-type MOSFET transistor, said second transistor comprises an n-type MOSFET transistor, said first supply voltage comprises a Vdd power supply voltage and said second supply voltage comprises a Vss power supply voltage.
- 10. The circuit of claim 7, further comprises:
a second transistor having a control terminal coupled to receive a first control signal, a first current handling terminal coupled to said control terminal of said first transistor and a second current handling terminal coupled to said first supply voltage; and a third transistor having a control terminal coupled to receive a second control signal, a first current handling terminal coupled to said control terminal of said first transistor and a second current handling terminal coupled to a second supply voltage; wherein said first control signal and said second control signal are asserted for selectively driving said output signal of said amplifier to said first supply voltage or said second supply voltage, respectively.
- 11. The circuit of claim 10, wherein said first and second transistors comprise p-type MOSFET transistors, said third transistor comprises an n-type MOSFET transistor, said first supply voltage comprises a Vdd power supply voltage and said second supply voltage comprises a Vss power supply voltage.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to U.S. Pat. No. 6,304,067, entitled “Adding A Laplace Transform Zero To A Linear Integrated Circuit For Frequency Stability,” filed on Dec. 8, 2000, and issued Oct. 16, 2001, and U.S. Pat. No. 6,424,132, entitled “Adding A Laplace Transform Zero To A Linear Integrated Circuit For Frequency Stability,” filed on Sep. 7, 2001, and issued Jul. 23, 2002, both of which by Robert S. Wrathall, the same inventor hereof, which patents are incorporated herein by reference in their entireties.
[0002] This application is also related to concurrently filed and commonly assigned U.S. patent application No. ______, entitled “Amplifier Circuit for Adding a Laplace Transform Zero in A Linear Integrated Circuit,” of the same inventor hereof.