Patent Application
20090276680
1. Field of the Invention
The present invention relates to an error correction circuit and an error correction method for a storage medium, and more particularly to an error correction circuit and a method thereof for improving the error correction capability regarding a data stream of a storage medium.
2. Description of Related Art
As science and technologies advance, many operating procedures employ digital processing, and manufacturers put up tremendous efforts to develop and produce high-capacity compact storage media for storing a large quantity of data at a lower cost, and to meet with the requirements of the market.
However, external interferences or noises occurred during the process of transmitting data between storage media may cause errors in data. For example, values of a plurality of bits in a data are changed by the interferences or noises while undergoing the process of being stored in a flash memory of an electronic product, therefore the incorrect data will be obtained when users read the data from the memory. To solve this problem, an error correcting code technique that using a parity produced by computing the data can achieve the effects of detecting and correcting the error bit of the data has developed.
Referring to
The conventional BCH Code error correcting code algorithm is designed to have an error correction capability of t bits. In other words, at most t error bits (including the bits of the parity Ai# and the data segment Ai) in each codeword can be corrected by using the parity, wherein the value of t is well known by those ordinarily skilled in the art, and thus will not be described here.
Even though the error correcting code can solve the aforementioned problem to a certain extend, but a high error rate per unit volume is still problematic, wherein the problem is even more apparent as the semiconductor fabrication process technology advances continuously and the capacity of a storage medium per unit volume expands increasingly. Therefore, finding a way of improving the error correction capability without incurring a higher level of complexity of the hardware or a higher manufacturing cost and implementing a simple and easy hardware and software error correction capability is a technical field worth researching.
In view of the foregoing shortcomings of the prior art, the present invention provides an error correction method that encodes a portion of a data segment to produce a partial data parity, and produces a whole data parity after the whole data segment is encoded. In other words, the whole data parity is the parity of the whole data; the partial data parity is the parity of a portion of the data, and the number of partial data parity depends on the number of portions of the data. Since the partial data parity and the whole data parity has equal error correction capability, assuming one whole parity and one partial parity is applied, then the overall error correction capability can be improved by two times via simply correcting each portion of data segment without increasing the complexity of hardware and software.
It is a primary objective of the present invention to provide an error correction method for improving the error correction capability regarding a data stream.
The present invention discloses an error correction encoding circuit comprising a shift registers and a plurality of auxiliary shift registers, and it is applied for error correction code encoding while writing data to a storage medium. The shift registers are provided for receiving the data stream and applied by the encoder to encode the parity of the data segment (a.k.a. whole data segment), and the auxiliary shift registers are provided for preserving the parity bits encoded from the front partial data segment. The decoding circuit of the storage medium uses the whole data parity and the partial data parity to correct the data stream.
The present invention also discloses an error correction method applicable in a storage medium for accessing data and comprising the following steps:
Firstly, an encoding procedure is performed when it is necessary to store a data in a storage medium, and a portion of the data and the whole data are encoded to produce a partial data parity for the portion of the data and a whole data parity for the whole data respectively. Secondly, a decoding procedure is performed when it is necessary to read the data from the storage medium, and the decoding procedure comprises the steps of: correcting error bits of both of the front portion of the data and the corresponding parity by applying the partial data parity; correcting error bits of both of the whole data (including the corrected portion of the data in the first step) and the corresponding parity by applying the whole data parity; and outputting the corrected data. To be more specific, “correcting error bits of both of the whole data (including the corrected portion of the data in the first step) and the corresponding parity by applying the whole data parity”, is especially important and different from prior art. Where prior art only has whole parity on each segment data (i.e. A0# corrects A0, A1# correct A1 . . . AN# corrects AN, then combine the data segments, as in
In a preferred embodiment of the present invention, the error correction method is applicable for accessing an original data stream in a storage medium. Before the encoding procedure takes place, the original data stream is divided into at least one data segment with an equal length, wherein the data segment is the aforementioned data of the last paragraph. The data segment is processed according to the encoding/decoding method disclosed by the present invention. After the decoding procedure is completed, all corrected data segments are combined sequentially into the original data stream for output.
In a preferred embodiment of the present invention, the encoding procedure further comprises the step of storing a portion of the data, a partial parity, the data and a whole parity into the storage medium.
In a preferred embodiment of the present invention, the encoding procedure and the decoding procedure adopt a Bose-Chaudhuri-Hocquenghem Code (BCH Code) algorithm, a Reed-Solomon Code (RS Code) algorithm or any cyclic code.
In a preferred embodiment of the present invention, a plurality of registers are provided for temporarily storing a partial parity produced after a portion of the data is computed, and a program is used for producing the partial parity after the portion of the data is computed.
In a preferred embodiment of the present invention, the error correction capability is directly proportional to the number of partial parities of the divided portion of the data.
In addition to the general description above, preferred embodiments together with related drawings are provided for illustrating the method, technical measure and performance of the present invention that achieve the expected objectives, and other objectives and advantages of the present invention will be described as follows.
FIG. 6-1˜6-3 is another flow chart of an error correction method in accordance with the present invention.
The present invention provides an error correction method comprising the steps of: dividing a data into a plurality of data segments and encoding a portion of the data segment and the whole data segment to produce a partial data segment parity (also called partial data parity hereafter) and a whole data segment parity (also called whole data parity hereafter) respectively; in other words, the whole data segment parity is the parity of the whole data segment; the partial data segment parity is the parity of a portion of the data segment, and the number of partial data segment parity depends on the number of portions of the data segment; and using the partial data segment parity and then the whole data segment parity to decode and to correct the corresponding data segments, so as to improve the error correction capability by multiple times through this reinforcing error correction method, which will not increase the complexity of hardware or software.
Although the present invention is characterized by an error correcting code circuit which is provided for processing data segments, and by the necessary hardware and sequences of operation required for accessing the data segments in a storage medium as described below. Those ordinarily skilled in the art can also use equivalent components and procedures to record the data segments into the storage medium and apply the present invention method to achieve the same result, thus the present invention is not limited to the embodiments disclosed here only.
In common error correcting code techniques (such as the BCH Code, which is used in the following embodiments for illustrating the present invention) generally use a cyclic parity to correct error bits, and the BCH Code defines a parameter (n, k, t), indicating that the length of an encoded data segment must be k bits for each time, and a parity of (n-k) bits will be produced after the BCH Code is computed, wherein each data segment will attach its corresponding parity to form a n-bit codeword. The BCH Code has a t-bit error correction capability; in other words, the parity can be applied to correct at most t error bits (including the error bits of the parity and the data segment) in each codeword. The operation of the aforementioned BCH Code is well known to those ordinarily skilled in the art, and thus will not be described here.
With reference to
In a preferred embodiment, a portion of the data segment a00 is defined as the content of the first half of the data segment A0 (i.e. the first half of the data segment A0 was also referred to as “front partial data segment” previously). When the partial data segment a00 of the data segment A0 has been serially inputted into the circuit, shift registers b0, b1, . . . , bn-k-1 will contain partial data parity. At this moment, partial data parity will be dumped into auxiliary shift registers b0′, b1′, . . . , bn-k-1′ and at the same time the remaining data segment a01 of the data segment A0 is subsequently inputted to the shift registers. After all data segment have been shifted into register b0, b1, . . . , bn-k-1, the registers shall contain the whole data parity A0#. In a preferred embodiment, (n-k) switches SW are added to the circuit, wherein the switches SW are coupled between the shift registers bi and the auxiliary shift registers bi′, when the partial data segment a00 is serially input into the circuit, then electrically connect the switches SW (e.g. the switches SW are closed), so that the partial data segment a00 is processed via the auxiliary shift registers b0′, b1′, . . . , bn-k-1′ to produce partial data parity a00#. By design, when the switches SW are not electrically connected (e.g. the switches SW are open), only the shift registers bi are connected, therefore it is the shift registers bi that receives the entire incoming data and outputs the whole data parity A0#. After the encoding is completed, the whole data parity A0# and the partial data parity a00# are appended to the data segment A0 for an output.
In a preferred embodiment of the present invention, applying software method to the original hardware encode circuit without the auxiliary shift registers b0′, b1′, . . . , bn-k-1′ can also achieve the partial data parity a00#. Specifically, a program code provides a temporarily stored array variable for the decoding operation of temporarily storing the received data segment A0, wherein the size of the temporarily stored array variable is the same as the size of the data segment A0. During the encoding operation, the temporarily stored array variable will fill the first half of the array variable with a plurality of zeros (0s) and store the other half of the array variable with the first half data segment a00 of the data segment A0 to form a temporary data segment, and then the encoding operation is performed immediately on the temporary data segment to produce a parity a00# for the partial data segment. (also called a partial data parity a00#) Thereafter, the temporarily stored array variable receives the whole data segment A0 to perform the encoding operation in order to produce a parity A0# for the whole data segment. (also called a whole data parity A0#) During the decoding operation, the partial data parity a00# is used for correcting the temporary data segment formed by combining the 0s and the first half data a00 of the data segment A0 first, and then using the whole data parity A0# to decode the corrected content of the partial data segment a00 appended with the partial data segment a01 of the second half. Thus, even the original hardware decoder of prior art applying the software method can be used for correcting up to two times of error bits under the condition that each portion of data contains no more than t error bits.
In a preferred embodiment of the present invention, the storage medium is a flash memory, an AND-flash memory, an OR-flash memory, a NAND-flash memory, a read only memory (ROM), an erasable read only memory (EROM), an electrically erasable read only memory (EEROM), an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM), or a combination thereof.
In a preferred embodiment of the present invention, the error correcting code circuit for achieving the encoding procedure and the decoding procedure adopts a Bose-Chaudhuri-Hocquenghem Code (BCH Code) algorithm, a Reed-Solomon Code (RS Code) algorithm, or any cyclic code.
Please reference
In a preferred embodiment of the present invention, the data segment and the parity can be stored sequentially in the format {a00, a01, A0#, a00#}, or {a00, a00#, a01, A0#}, or even all encoded parities can be recorded into another storage space without a connection with the content of the data segment; these formats are possible in addition to the storage format {a00, a01, a00#, A0#} shown in
For actual practice, in regard to the decoding method of a portion of the data segment please refer to
In the decoding process, as shown by
A raw data stream stored in a storage medium is received (Step S401). When an encode circuit defines the received data stream of a specific length, the encode circuit starts encoding the data stream, so that in the process of receiving a raw data stream, the raw data stream is divided sequentially into at least one data segment for the processing (Step S403). Each data segment has the same length (k-bit), and any subsequent data segment of the preferred embodiment uses a data segment A0 (a.k.a. whole data segment A0) as an example for the method steps. For the first half of the data segment A0, the encode circuit as shown in
The remaining data segment a01 is received. When all data of the data segment A0 are received, the data segment A0 is encoded to obtain a whole data parity A0# (Step S409), and then the format as shown in
Furthermore, the storage medium will determine whether or not to receive an instruction of the received raw data stream (i.e. whether or not to read the raw data stream) (Step S413); if yes, then the content of the partial data parity a00# is read from the storage medium, and the partial data parity a00# is used for performing a decoding procedure for the data segment a00 and the partial data parity a00# (Step S415). In the decoding process, a step is carried out to determine whether or not there is an error (Step S417). If there is no error, then the whole data parity A0# will be used for performing the decoding procedure for the data segment A0 and the whole data parity A0# (Step S425), or else the partial data parity a00# will determine whether or not an error bit can be corrected (Step S419). If the number of error bits exceeds the error correction capability, then an error processing signal will be issued to inform users about the damage condition of the currently read data (Step S421). If the number of error bits has not exceeded the error correction capability, then the error bits in the data segment a00 and the partial data parity a00# will be corrected (Step S423).
The whole data parity A0# is used continuously for performing the decoding procedure for the data segment A0 and the whole data parity A0# (Step S425). In fact, at this time the content of the data segment a00 in the data segment A0 is correct (due to the fact that in order to reach step S425, there will have to be no error with a00 to begin with or if the error in a00 is corrected), and thus step of S425 is a process intended for further checking whether or not there is an error in the contents of the data segment a01 and the whole data parity A0# in next step. In the decoding process, a step is performed to determine whether or not there is an error (Step S427). If there is no error, then the correct data segment A0 will be outputted (Step S435), or else the step will further determine whether or not the error bits can be corrected (Step S429). If the number of error bits exceeds the error correction capability, then an error processing signal will be issued to inform users about the damage condition of the currently read data (Step S431), or else the error bits in the data segment A0 (to be more precise, it would be the error bits from a01 part of the data segment A0) and the whole data parity A0# will be corrected (Step S433), so as to complete the decoding procedure of a single data segment.
Of course, Steps S415 to S433 are carried out repeatedly for processing other data segments Ai. Finally, the corrected data segments A0, A1, . . . , AN are combined into the raw data stream for the output.
In another preferred embodiment of the present invention, the whole data parity A0# is used to perform an error correction procedure for the whole data segment A0 and the whole data parity A0# after the Step S413. If there is an error, then the Step S415 will be executed, or else each data segment Ai will be combined for the output.
In another preferred embodiment of the present invention, Steps S425 to S433 are carried out after the Step S413, and the whole data parity A0# can be used for carrying out the processes of decoding and correcting the whole data segment A0 and the whole data parity A0# and then Steps S415 to S433 are carried out to combine each data segment Ai for the output.
For one preferred implementation, it is considered that since it is rare for error to take place, it would be time saving to decode the whole data first. Only when it is found that there is an uncorrectable error in the whole data segment A0 and whole data parity A0#, then shall the aforementioned partial data decoding process be performed.
In a preferred embodiment of the present invention, each data segment can be divided into a plurality of partial data segment for encoding as a plurality of error correction codes to increase the error correction capability by multiple times. More specifically, if the data segment A0 is divided into three portions of data segments a00, a01, a02, there would be two partial data parities a00#, a01# and one whole data parity A0# after encoding process, wherein the partial data parity a00# has t-bit error correction capability for the data segment a00 and the partial data parity a00#, and the partial data parity a01# has t-bit error correction capability for the data segment a00˜a01 and the partial data parity a01#, and so forth. This technical feature is distinctly different from prior art, wherein there would be only one parity for each data segment and the error correction capability is limited to the error correction code of the hardware design (i.e. a00# corrects a00 and a01# corrects a01). However, in the present invention, due to the fact that there are two partial data parities and one whole data parity, the error correction capability is enhanced three times for the whole data segment, under the condition that each portion of data contains no more than t error bits.
To achieve the effect of dividing the data segment A0 into a plurality of portions for the encoding process, the hardware circuit adds a buffer area as the auxiliary shift registers b0′, b1′, . . . , bn-k-1′ as shown in
Please reference
Finally, referring to FIG. 6-1˜6-3 for flow charts of an error correction method in accordance with the present invention which is based on the storage format of the
Read the data segment (Step S600) and determine whether number of error bits exceeds the bit number of an error correction capability of the whole data parity 502 or not (Step S610). If no, the encode circuit uses the whole data parity 502 to decode the corresponding data segment 500 and the whole data parity 502 and to correct error bits of the data segment 500 and the whole data parity 502 (Step S612). Or, determine whether number of error bits exceeds the bit number of an error correction capability of the first partial data parity 512 or not (Step S620). If no, the encode circuit uses the first partial data parity 512 to decode the corresponding first portion of the data segment 510 and the first partial data parity 512 (Step S622). Then, correct error bits of the first portion of the data segment 510 and the first partial data parity 512 (Step S624). And use the whole data parity 502 to decode the corresponding data segment 500 including the corrected first portion of the data segment 510 and the whole data parity 502 (Step S626), then, to correct error bits of the data segment 500 including the corrected first portion of the data segment 510 and the whole data parity 502 (Step S628).
If number of error bits exceeds the bit number of an error correction capability of the first partial data parity 512, determine whether number of error bits exceeds the bit number of an error correction capability of the second partial data parity 522 or not (Step S630). If no, use the second partial data parity 522 to decode the corresponding second portion of the data segment 520 and the second partial data parity 522 (Step S632). Then, the encode circuit corrects error bits of the contents of the data segment 500 based on above operations.
Similarly, determine which segment has error bits and correct them according to above operations until the data segment 500 is recovered. However, if the number of error bits exceeds the bit number of an error correction capability of the Nth partial data parity 532, then an error processing signal will be issued to inform users about the damage condition of the currently read data (Step S652).
The error correction method of the present invention is disclosed by the aforementioned preferred embodiments, and is disclosed by the method which divides a data segment into multiple data portion for error correction code encoding, and then produces partial data parities and a whole data parity after encoding each portion of the data segments and the whole data segment, and the partial data parities and the whole data parity are used for decoding and correcting errors of the corresponding data segment. Each of the parity has the same error correction capability for the corresponding data, and thus the present invention can achieve the purpose of improving the error correction capability by several times without increasing much of the complexity of hardware or software.
Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the present invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the present invention as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200810096068.9 | Apr 2008 | CN | national |
