Patent Application
20240184669
This US non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0167363, filed on Dec. 5, 2022, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference.
Example embodiments generally relate to semiconductor integrated circuits, and more particularly to an error correction code (ECC) decoder, a storage controller including the same and a storage device including the same.
Semiconductor memory devices are classified into a volatile memory and a nonvolatile memory.
The volatile memory may lose contents stored therein at power-off. The nonvolatile memory may retain stored contents even at power-off. A flash memory, one of the nonvolatile memory devices, may have following advantages: mass storage capability, relatively high noise immunity, and low power operation. Therefore, the flash memory devices are employed in various fields. For example, a mobile system such as a smart-phone, or a tablet PC employs flash memory as a storage medium.
As fabrication process of a flash memory device is scaled-down and memory cells of the flash memory device are stacked, the memory cells are degraded and data retention characteristic of the memory cells are degraded.
Some example embodiments may provide an error correction code (ECC) decoder capable of reducing latency of soft-decision decoding.
Some example embodiments may provide a storage controller including an ECC decoder capable of reducing latency of soft-decision decoding.
Some example embodiments may provide a storage device including an ECC decoder capable of reducing latency of soft-decision decoding.
According to some example embodiments, an ECC decoder includes an input manager, a pre-decoder and a main decoder. The input manager sequentially receives a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector. The pre-decoder sequentially receives the first read data by unit of sector, in parallel with the input manager receiving the first read data and generates a respective syndrome of each of the plurality of data units sequentially. The main decoder sequentially performs a first ECC decoding on the first read data based on the respective syndrome, by unit of sector. The input manager includes a defective sector buffer, in response to the first ECC decoding on a first data unit of the plurality of data units being failed, stores the first data unit in the defective sector buffer and, in response to the first ECC decoding on a second data unit of the plurality of data units being failed, selectively stores the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit, from among the plurality of sectors.
According to some example embodiments, a storage controller configured to control a nonvolatile memory device includes an ECC decoder, a processor to control the ECC decoder. The ECC decoder sequentially receives a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, sequentially performs a first ECC decoding on the first read data by unit of sector, in response to the first ECC decoding on a first data unit of the plurality of data units being failed, stores the first data unit in a defective sector buffer therein, in response to the first ECC decoding on a second data unit of the plurality of data units being failed, selectively stores the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit, from among the plurality of sectors.
According to some example embodiments, a storage device includes at least one nonvolatile memory device and a storage controller including an ECC decoder. The least one nonvolatile memory device includes a memory cell array, wherein the memory cell array includes a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes extending in a vertical direction with respect to the substrate and a word-line cut region extending in a first horizontal direction and dividing the plurality of word-lines into a plurality of memory blocks. The ECC decoder sequentially receives a first read data including a plurality of data units read from a plurality of sectors in the memory cell array based on a default read voltage, by unit of sector, sequentially performs a first ECC decoding on the first read data by unit of sector, in response to the first ECC decoding on a first data unit of the plurality of data units being failed, stores the first data unit in a defective sector buffer therein, in response to the first ECC decoding on a second data unit of the plurality of data units being failed, selectively stores the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and performs a second ECC decoding on a defective data unit stored in the defective sector buffer and a second read data read from a selected sector corresponding to the defective data unit, based on offset read voltages that have an offset with respect to the default read voltage, from among the plurality of sectors.
Accordingly, the ECC decoder performs a first ECC decoding on each of a plurality of data units, in response to the first ECC decoding on a portion of the plurality of data units being failed, stores a defective data unit having a minimum expected error count (i.e., a maximum probability associated with a success of a second ECC decoding) in a defective sector buffer located inside the ECC decoder, reads a second read data from a sector corresponding to the defective data unit, performs a second ECC decoding on the defective data unit and the second read data and corrects error in read data. Therefore, the ECC decoder may reduce latency associated with the second ECC decoding and may increase success probability of the second ECC decoding.
Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.
Referring to
The storage device 200 may be any kind of storage devices.
The storage device 200 may include a storage controller 300, a plurality of nonvolatile memory devices NVM1˜NVMk 400a˜400k (where k is an integer greater than two), a power management integrated circuit (PMIC) 600 and a host interface 240. The host interface 240 may include a signal connector 241 and a power connector 243. The storage device 200 may further include a buffer memory BM 250 that is implemented with a volatile memory device.
The plurality of nonvolatile memory devices 400a˜400k may be used as a storage medium of the storage device 200. In some example embodiments, each of the plurality of nonvolatile memory devices 400a˜400k may include a flash memory or a vertical NAND memory device. The storage controller 300 may be coupled to the plurality of nonvolatile memory devices 400a˜400k through a plurality of channels CH1˜CHk, respectively.
The storage controller 300 may be configured to receive a request REQ from the host 100 and communicate data DTA with the host 100 through the signal connector 241. The storage controller 300 may write data DTA to the plurality of nonvolatile memory devices 400a˜400k or read the data DTA from the plurality of nonvolatile memory devices 400a˜400k based on the request REQ.
The storage controller 300 may communicate the data DTA with the host 100 using the buffer memory 250 as an input/output buffer. In some example embodiments, the buffer memory 250 may include a dynamic random access memory (DRAM).
The PMIC 600 may be configured to receive a plurality of power supply voltages (i.e., external supply voltages) VES1-VESt from the host 100 through the power connector 243. For example, the power connector 243 may include a plurality of power lines P1˜Pt, and the PMIC 600 may be configured to receive the plurality of power supply voltages VES1˜VESt from the host 100 through the plurality of power lines P˜Pt, respectively. Here, t represents a positive integer greater than one.
The PMIC 600 may generate at least one first operating voltage VOP1 used by the storage controller 300, at least one second operating voltage VOP2 used by the plurality of nonvolatile memory devices 400a˜400k, and at least one third operating voltage VOP3 used by the buffer memory 250 based on the plurality of power supply voltages VES1˜VESt.
For example, when the PMIC 600 receives all of the plurality of power supply voltages VES1˜VESt from the host 100, the PMIC 600 may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3 using all of the plurality of power supply voltages VES1˜VESt. On the other hand, when the PMIC 600 receives less than all of the plurality of power supply voltages VES1˜VESt from the host 100, the PMIC 600 may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3 using all of the part of the plurality of power supply voltages VES1˜VESt that is received from the host 100.
Referring to
The bus 160 may refer to a transmission channel via which data is transmitted between the processor 110, the ROM 120, the main memory 130, the storage interface 140 and the user interface 150 of the host 100. The ROM 120 may store various application programs. For example, application programs supporting storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), embedded Multi Media Card (eMMC), and/or Universal flash storage (UFS) protocols are stored.
The main memory 130 may temporarily store data or programs. The user interface 150 may be a physical or virtual medium for exchanging information between a user and the host device 100, a computer program, etc., and includes physical hardware and logical software. For example, the user interface 150 may include an input device for allowing the user to manipulate the host 100, and an output device for outputting a result of processing an input of the user.
The processor 110 may control overall operations of the host 100. The processor 110 may generate a command for storing data in the storage device 200 or a request (or a command) for reading data from the storage device 200 by using an application stored in the ROM 120, and may transmit the request to the storage device 200 via the storage interface 140. The processor 110 may generate plurality of power supply voltages VES1˜VESt.
Referring to
The processor 310 controls an overall operation of the storage controller 300. The processor 310 may control the ECC engine 500, the on-chip memory 330, the AES engine 340, the host interface 350, the ROM 360 and the memory interface 370. The processor 310 may include one or more cores (e.g., a homogeneous multi-core or a heterogeneous multi-core). The processor 310 may be or include, for example, at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). The processor 310 may execute various application programs (e.g., a flash translation layer (FTL) 335 and firmware) loaded onto the on-chip memory 330.
The on-chip memory 330 may store various application programs that are executable by the processor 310. The on-chip memory 330 may operate as a cache memory adjacent to the processor 310. The on-chip memory 330 may store a command, an address, and data to be processed by the processor 310 or may store a processing result of the processor 310. The on-chip memory 330 may be, for example, a storage medium or a working memory including a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a tightly coupled memory (TCM), etc.
The processor 310 may execute the FTL 335 loaded onto the on-chip memory 330. The FTL 335 may be loaded onto the on-chip memory 330 as firmware or a program stored in the one of the nonvolatile memory devices 400a˜400k. The FTL 335 may manage mapping between a logical address provided from the host 100 and a physical address of the nonvolatile memory devices 400a˜400k and may include an address mapping table manager managing and updating an address mapping table. The FTL 335 may further perform a garbage collection operation, a wear leveling operation, and the like, as well as the address mapping described above. The FTL 335 may be executed by the processor 310 for addressing one or more of the following aspects of the nonvolatile memory devices 400a˜400k: overwrite- or in-place write-impossible, a life time of a memory cell, a limited number of program-erase (PE) cycles, and an erase speed slower than a write speed.
Memory cells of the nonvolatile memory devices 400a˜400k may have the physical characteristic that a threshold voltage distribution varies due to causes, such as a program elapsed time, a temperature, program disturbance, read disturbance and etc. For example, data stored at the nonvolatile memory devices 400a˜400k becomes erroneous due to the above causes.
The storage controller 300 may utilize a variety of error correction techniques to correct such errors. For example, the storage controller 300 may include the ECC engine 500. The ECC engine 500 may correct errors which occur in the data stored in the nonvolatile memory devices 400a˜400k. The ECC engine 500 may include an ECC encoder 510 and an ECC decoder 520. The ECC encoder 510 may perform an ECC encoding operation on data to be stored in the nonvolatile memory devices 400a˜400k. The ECC decoder 520 may perform an ECC decoding operation on data read from the nonvolatile memory devices 400a˜400k.
The ECC decoder 520 may receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of at least one of the nonvolatile memory devices 400a˜400k, sequentially by unit of sector, may perform a first ECC decoding on the first read data sequentially by unit of sector, in response to the first ECC decoding on a first data unit of the plurality of data units being failed, may store the first data unit in a defective sector buffer therein, in response to the first ECC decoding on a second data unit of the plurality of data units being failed, may selectively store the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and may perform a second ECC decoding on a defective data unit stored in the defective sector buffer and a second read data read from a selected sector corresponding to the defective data unit, from among the plurality of sectors.
The ROM 360 may store a variety of information, needed for the storage controller 300 to operate, in firmware.
The AES engine 340 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 300 by using a symmetric-key algorithm. Although not illustrated in detail, the AES engine 340 may include an encryption module and a decryption module. For example, the encryption module and the decryption module may be implemented as separate modules. For another example, one module capable of performing both encryption and decryption operations may be implemented in the AES engine 340.
The storage controller 300 may communicate with the host 100 through the host interface 350. For example, the host interface 350 may include Universal Serial Bus (USB), Multimedia Card (MMC), embedded-MMC, peripheral component interconnection (PCI), PCI-express, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), Nonvolatile memory express (NVMe), Universal Flash Storage (UFS), and etc. The storage controller 300 may communicate with the nonvolatile memory devices 400a˜400k through the memory interface 370.
Referring to
The nonvolatile memory device 400a may perform an erase operation, a program operation, and/or a write operation under control of the storage controller 300. The nonvolatile memory device 400a may receive a command CMD, an address ADDR, and (user) data DTA (i.e., a write data WD) through input/output lines from the storage controller 300 for performing such operations. In addition, the nonvolatile memory device 400a may receive a control signal CTRL through a control line and receives a power PWR1 through a power line from the storage controller 300. In addition, the nonvolatile memory device 400a may provide the storage controller 300 with the data DTA (i.e., a read data RD).
The storage controller 300 may include the ECC engine 500, and the ECC engine 500 may include the ECC encoder 510 and the ECC decoder 520. The ECC encoder 510 may perform an ECC encoding operation on data to be stored in the nonvolatile memory device 400a. The ECC decoder 520 may perform an ECC decoding operation on data read from the nonvolatile memory device 400a.
The ECC decoder 520 may receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of the nonvolatile memory device 400a, sequentially by unit of sector, may perform a first ECC decoding on the first read data sequentially by unit of sector, in response to the first ECC decoding on a first data unit of the plurality of data units being failed, may store the first data unit in a defective sector buffer therein, in response to the first ECC decoding on a second data unit of the plurality of data units being failed, may selectively store the second data unit in the defective sector buffer based on an expected error count of each of the first data unit and the second data unit, and may perform a second ECC decoding on a defective data unit stored in the defective sector buffer and a second read data read from a selected sector corresponding to the defective data unit, from among the plurality of sectors.
Referring to
The memory cell array 420 may be coupled to the address decoder 450 through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL. In addition, the memory cell array 420 may be coupled to the page buffer circuit 430 through a plurality of bit-lines BLs.
The memory cell array 420 may include a plurality of memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.
In some example embodiments, the memory cell array 420 may be or include a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array 420 may include (vertical) cell strings that are vertically oriented such that at least one memory cell is located over another memory cell.
Referring to
The memory block BLKi of
Referring to
The string selection transistor SST may be connected to corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to corresponding word-lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2 and BL3, and the ground selection transistor GST may be connected to the common source line CSL.
Word-lines (e.g., WL1) having the same height may be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 may be separated. In
Referring to
A sectional view taken along a line V-V′ is also illustrated in
The body BD may include P-type silicon and may be an area where a channel will be formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer B1 may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI, and the first word line WL1 may constitute or be included in a charge trap type transistor that is formed in a direction perpendicular to the substrate SUB or to an upper surface of the substrate SUB. A string selection transistor SST, a ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.
Referring back to
For example, the control circuit 460 may generate control signals CTLs, which are used for controlling the voltage generator 470, may generate a page buffer control signal PBC for controlling the page buffer circuit 430 based on the command signal CMD, may provide the control signals CTLs to the voltage generator 470 and may provide the page buffer control signal PBC to the page buffer circuit 430. In addition, the control circuit 460 may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 460 may provide the row address R_ADDR to the address decoder 450 and may provide the column address C_ADDR to the data I/O circuit 440.
The address decoder 450 may be coupled to the memory cell array 420 through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder 450 may determine one of the plurality of word-lines WLs as a first word-line (e.g., a selected word-line) and determine the rest of the plurality of word-lines WLs, except for the first word-line, as unselected word-lines based on the row address R_ADDR.
The voltage generator 470 may generate word-line voltages VWLs, which are required for the operation of the nonvolatile memory device 400a, based on the control signals CTLs. The voltage generator 470 may receive the power PWR1 from the storage controller 300. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder 450.
For example, during the erase operation, the voltage generator 470 may apply an erase voltage to a well of the memory block and may apply a ground voltage to entire word-lines of the memory block. During the erase verification operation, the voltage generator 470 may apply an erase verification voltage to the entire word-lines of the memory block or sequentially apply the erase verification voltage to word-lines in a word-line basis.
For example, during the program operation, the voltage generator 470 may apply a program voltage to the first word-line and may apply a program pass voltage to the unselected word-lines. In addition, during the program verification operation, the voltage generator 470 may apply a program verification voltage to the first word-line and may apply a verification pass voltage to the unselected word-lines.
Furthermore, during the read operation, the voltage generator 470 may apply a read voltage to the first word-line and may apply a read pass voltage to the unselected word-lines.
The page buffer circuit 430 may be coupled to the memory cell array 420 through the plurality of bit-lines BLs. The page buffer circuit 430 may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit-line. In some example embodiments, one page buffer may be connected to two or more bit-lines.
The page buffer circuit 430 may temporarily store data to be programmed in a selected page or data read out from the selected page.
The data I/O circuit 440 may be coupled to the page buffer circuit 430 through data lines DLs. During the program operation, the data input/output circuit 440 may receive the data DTA (or, the write data WD) from the storage controller 300 and provide the data DTA to the page buffer circuit 430 based on the column address C_ADDR received from the control circuit 460.
During the read operation, the data I/O circuit 440 may provide the data DTA (or, the read data RD) which are stored in the page buffer circuit 430, to the storage controller 300 based on the column address C_ADDR received from the control circuit 460.
The control circuit 460 may control the page buffer circuit 430 and data I/O circuit 440.
The control circuit 460 may include a status signal generator 465 and the status signal generator 465 may generate a status signal RnB indicating whether each of the program operation, the erase operation and the read operation is completed and/or is in progress.
The storage controller 300 may determine idle state or busy state of each of the nonvolatile memory devices 400a˜400k based on the status signal RnB.
Referring to
The memory cell array 420 may include a normal cell region NCA to store the user data DTA and a parity cell region PCA to store parity bits.
Memory cells of the normal cell region NCA and the parity cell region PCA may be coupled to bit-lines BL1˜BLn (n is an integer equal to or greater than 4). Each of the pages in the normal cell region NCA and the parity cell region PCA may include a plurality of sectors SEC1, SEC2 to SECj (j is an integer equal to or greater than 3).
Referring to
A plurality of vertical channels or channel holes penetrate the at least one ground selection lines GSL, the plurality of word-lines WLs and the at least one string selection lines SSL. The at least one ground selection lines GSL, the plurality of word-lines WL and the at least one string selection lines SSL may be formed in the shape of planks. Bit-lines BL are connected to top surfaces of the channel holes.
Referring to
A first read voltage Vr1 has a voltage level between a distribution of a memory cell having the erase state E and a distribution of a memory cell having the first program state P1. Each of second through fifteenth read voltages Vr2 through Vr15 have a voltage level between distributions of memory cells having adjacent program states.
In example embodiments, assuming that the first read voltage Vr1 is applied, when a memory cell is turned on, data ‘1’ may be stored, and when the memory cell is turned off, data ‘0’ may be stored. However, the present disclosure is not limited thereto, and other example embodiments, assuming that the first read voltage Vr1 is applied, when a memory cell is turned on, data ‘0’ may be stored, and when the memory cell is turned off, data ‘1’ may be stored. As such, a logic level of data may vary according to the present disclosure.
Referring to
For example, when a read operation is performed on a memory device by using the first read voltage Vr1, although memory cells included in a hatched portion are programmed to the first program state P1, the memory cells may be determined to have the erase state E due to a decrease in the threshold voltage Vth. Accordingly, an error may occur in the read operation, thereby reducing the reliability of the nonvolatile memory device.
When data is read from the nonvolatile memory device 400a, a raw bit error rate (RBER) may vary according to a voltage level of a read voltage. An optimum or, alternatively, desirable voltage level of a read voltage maybe determined according to a distribution pattern of the memory cells. Accordingly, as a distribution of the memory cells changes, an optimum or, alternatively, desirable voltage level of a read voltage needed to read data from the nonvolatile memory device may change.
For convenience of explanation, the present embodiment assumes a case where a memory cell is a QLC. However, in other embodiments the memory cell may be a different type other than a QLC.
Referring to
Referring to
It is assumed that the ECC decoder 520 in
An LDPC code has an error correction capability near a channel capacity and is widely used in communication systems, communication standards, memory controllers, etc. The LDPC code is a linear block code that may be defined as a parity check matrix (PCM). Here, the definition of a code may be a relation between information and parity.
The LDPC code having a codeword length of s and an information length of t may be represented by the PCM having a size of (s−t)*s. In general, the LDPC code has a higher correction capability as the codeword length is long. The codeword may correspond to a sector.
Referring to
The ECC decoder 520 may apply log likelihood ratio (LLR) values LLRVa, LLRVb, LLRVc, LLRVd, LLRVe and LLRVf to the variable nodes a, b, c, d, e and f, respectively.
Referring to
The hard-decision decoding may refer to a decoding based on a normal data read operation and reads the data stored in the memory cell as ‘1’ or ‘0’, depending on whether the memory cell is the on-cell or the off-cell, when the voltage having the read level is applied to the word line of the memory cell. A hard-decision read voltage refers to the default read voltage VH. When the default read voltage VH is applied to the memory cell through the word-line, a hard-decision data becomes ‘1’ if the memory cell is an on-cell, and the hard-decision data becomes ‘0’ if the memory cell is an off-cell.
The soft-decision decoding may refer to a decoding that adds reliability to the hard decision data by applying offset read voltages (i.e., soft-decision read voltages) to the memory cells.
As shown in
When the first soft-decision data and the second soft-decision data correspond to ‘11’, a reliability of the hard-decision data is strong. When the first soft-decision data and the second soft-decision data correspond to ‘00’, a reliability of the hard-decision data is weak.
Absolute values of the LLR values may indicate reliability of the hard-decision data.
The nonvolatile memory device 400a may perform a read operation including a hard decision read operation and/or a soft decision read operation on a plurality of sectors in a target page. The hard decision read operation reads the hard decision data stored in the memory cell as 1 or 0, depending on whether the memory cell coupled to a target word-line is the on-cell or the off-cell, when the default read voltage is applied to the target word-line. The ECC decoder 520 may perform hard decision type of error correction based on the hard decision data and an error correction code (i.e., LDPC code). The soft decision read operation reads the soft decision data having reliability information on the hard decision data, from the memory cells coupled to the target word-lines when offset read voltages having offsets with respect to the default read voltage are applied to the target word-line. The ECC decoder 520 may perform soft decision type of error correction based on the hard decision data, the reliability information on the hard decision data and the error correction code (i.e., LDPC code).
Referring to
The input manager 530 may receive a first read data including a plurality of data units HDRDs read from a plurality of sectors of a target page, sequentially by unit of sector.
The pre-decoder 550 may receive the first read data including the plurality of data units HDRDs sequentially by unit of sector in parallel with the input manager 530 receiving the first read data, may generate a syndrome SDR of each of the plurality of data units HDRDS sequentially and may provide the syndrome SDR to the main decoder 560. The syndrome SDR may indicate whether each of the plurality of data units HDRDS includes at least one error bit.
The main decoder 560 may receive the plurality of data units HDRDs sequentially from the input manager 530, may perform a first ECC decoding on the plurality of data units HDRDs based on the respective syndrome SDR, sequentially by unit of sector, and may determine pass/fail of the first ECC decoding on each of the plurality of data units HDRDs.
The input manager 530, in response to the first ECC decoding on a first data unit of the plurality of data units HDRDs being failed, may store the first data unit in a defective sector buffer therein, based on a result of the first ECC decoding on each of the plurality of data units HDRDs, in response to the first ECC decoding on a second data unit of the plurality of data units HDRDs being failed, may selectively store the second data unit in the defective sector buffer based on an expected error count EEC of each of the first data unit and the second data unit and may provide the main decoder 560 with a defective data unit of which expected error count is relatively small. Each of the plurality of data units HDRDs may correspond to a hard decision data that is read from each of the plurality of sectors based on a default read voltage.
The main decoder 560 may perform a second ECC decoding on the defective data unit of which expected error count is relatively small and a second read data SDRD read from a selected sector corresponding to the defective data unit, from among the plurality of sectors and may provide the output manager 590 with a result of the second ECC decoding. The second read data SDRD may correspond to a soft-decision data that is read from the selected sector based on offset read voltages that have an offset with respect to the default read voltage.
The output manager 590 may output a decoded data CD or a read error message ERR based on the result of the second ECC decoding.
Referring to
The input manager 530 may include a first sector buffer 531, a second sector buffer 533, a defective sector buffer 535, a buffer controller 540 and a multiplexer 537.
The first sector buffer 531 may sequentially store the plurality of data units HDRDs by unit of sector. The second sector buffer 533 may store the second read data SDRD and may provide the second read data SDRD to the main decoder 560 when the second ECC decoding is performed.
The defective sector buffer 535 may store the first data unit on which the first ECC decoding is failed, from among the plurality of data units HDRDs, and may selectively store a second data unit based on an expected error count of each of the first data unit and the second data unit, provided from the main decoder 560, in response to the first ECC decoding on the second data unit of the plurality of data units HDRDs being failed.
The buffer controller 540 may firstly store the first data unit on which the first ECC decoding is failed in the defective sector buffer 535 and may selectively store the second data unit on which the first ECC decoding is failed in the defective sector buffer 535 based on a first expected error count EEC1 of the first data unit and a second expected error count EEC2 of the second data unit.
In response to the second expected error count EEC2 being smaller than the first expected error count EEC1, the buffer controller 540 may update the second data unit in the defective sector buffer 535. In response to the second expected error count EEC2 being equal to or greater than the first expected error count EEC1, the buffer controller 540 may maintain the first data unit in the defective sector buffer 535.
Therefore, when the first ECC decoding on two or more data units from among the plurality of data units HDRDs is failed, the buffer controller 540 may update a data unit having a minimum expected error count in the defective sector buffer 535.
The buffer controller 540 may provide a selection signal SEL to the multiplexer 537 based on whether the first ECC decoding or the second ECC decoding is performed.
When the first ECC decoding on the plurality of data units HDRDs is performed, the buffer controller 540 may generate the selection signal SEL with a first logic level (i.e., a logic low level) and the multiplexer 537 may provide the main decoder 560 with each of the plurality of data units HDRDs sequentially received from the first sector buffer 531, in response to the selection signal SEL with a first logic level.
When the second ECC decoding on is performed, the buffer controller 540 may generate the selection signal SEL with a second logic level (i.e., a logic high level) and provide the multiplexer 537 with a defective data unit HDRD_D having a minimum expected error count may, which is stored in the defective sector buffer 535, and the multiplexer 537 may provide the main decoder 560 with the defective data unit HDRD_D having a minimum expected error count, in response to the selection signal SEL with a first logic level.
The pre-decoder 550 may include a syndrome calculator 551 and a syndrome buffer 553 connected to the syndrome calculator 551.
The syndrome calculator 551 may sequentially generate a syndrome SDR of each of the plurality of data units HDRDs when the first ECC decoding is performed on each of the plurality of data units HDRDs and may provide the syndrome SDR to the main decoder 560.
The syndrome buffer 553 may store a first syndrome associated with the first data unit on which the first ECC decoding is failed, and may selectively update a second syndrome associated with the second data unit in response to the second data unit being selectively updated in the defective sector buffer 535.
The syndrome buffer 553 may provide the main decoder 560 with a syndrome stored therein as a selected syndrome SDR_S when the second ECC decoding is performed.
The main decoder 560 may include an LLR mapper 565, a register 567, a variable node processor VNP 570, a first switch network SWN1 575, a check node processor CNP 580 and a second switch network SWN2 585. The variable node processor 570 may include variable nodes such as the variable nodes a, b, c, d, e and f in
The register 567 may store first LLR values LLRV1 associated with the first ECC decoding and second LLR values LLRV2 associated with the second ECC decoding and may provide the first LLR values LLRV1 and the second LLR values LLRV2 to the LLR mapper 565.
The LLR mapper 565 may output LLR data LLRD to the variable node processor 570 by mapping the first LLR values LLRV1 to the each of plurality of data units HDRDs provided from the input manager 530 in the first ECC decoding (i.e., hard decision decoding) and may output the LLR data LLRD to the variable node processor 570 by mapping the second LLR values LLRV2 to the defective data unit HDRD_D and the second read data SDRD provided from the input manager 530 in the second decoding (i.e., soft decision decoding).
The main decoder 560 may update values of the variable nodes and values of the check nodes by performing node operation based on the LLR data LLRD and may output a decoding result data DRD to the output manager 590.
During the LDPC decoding, a nonzero element in the parity check matrix means that a corresponding variable node and a corresponding check node are connected to each other. The decoding is performed through data transmitted according to the connection of the variable node and the check node.
The variable node processor 570 may include the variable nodes a, b, c, d, e and f in
The check node processor 580, while the first ECC decoding is being performed, may generate a first syndrome weight SDRW1 based on the first syndrome associated with the first data unit, may generate a second syndrome weight SDRW2 based on the second syndrome associated with the second data unit and may provide the buffer controller 540 in the input manager 530 with the first syndrome weight SDRW1 and the second syndrome weight SDRW2 as the first expected error count EEC1 and the second expected error count EEC2, respectively. Each of the first syndrome weight SDRW1 and the second syndrome weight SDRW2 indicates a number of bits having a first logic level in each of the first syndrome and the second syndrome in a plurality of iterations of the first ECC decoding on each of the first data unit and the second data unit.
The variable node processor 570 may be connected to the check node processor 580 through the second switch network 557, may update values of the variable nodes a, b, c, d, e and f with reference to the check node message CNM, may perform decoding on the LLR data LLRD according to the updated values of the variable nodes and may output the decoding result data DRD indicating a result of the decoding to the output manager 590.
The variable node processor 570, while the first ECC decoding is being performed, may provide the buffer controller 540 in the input manager 530 with updated values VNV1 and VNV2 of the variable nodes as the first expected error count EEC1 and the second expected error count EEC2. Each of the updated values VNV1 and VNV2 may be associated with each of the first data unit and the second data unit.
The main decoder 560 may provide the buffer controller 540 with intermediate data which is generated during performing the first ECC decoding on each of the first data unit and the second data unit and is associated with a number of error bits as the first expected error count EEC1 and the second expected error count EEC2, respectively.
The output manager 590 may output the decoded data CD by correcting error in the defective data unit HDRD_D or may output the read error message EER when the error is uncorrectable, based on the decoding result data DRD from the variable node processor 570.
The output manager 590 may include a cyclic redundancy check (CRC) checker 591 and an output sector buffer 593.
The CRC checker 591 may perform CRC on the decoding result data DRD and may store a corrected data in the output sector buffer 593 when the error of the decoding result data DRD is correctable and the output sector buffer 593 may output the corrected data as the decoded data CD. The CRC checker 591 may perform CRC on the decoding result data DRD and may output the read error message ERR when the error of the decoding result data DRD is uncorrectable.
If the decoding is correctly performed, the ECC decoder 520 outputs the corrected data as the decoded data CD. If the decoding is not correctly performed (e.g., all errors of the read data are not corrected), the ECC decoder 520 re-updates the check nodes and the variable nodes.
The above update and provisional decoding of check nodes and variable nodes are iteratively performed. The update and provisional decoding of check nodes and variable nodes may constitute a single decoding loop, that is, a decoding iteration.
When the first ECC decoding is performed in the ECC decoder 520 and the first ECC decoding on at least a portion of the plurality of data units is failed, the main decoder 560 may transmit a fail message to the input manger 530 and the input manger 530 may transmit a read request for the second ECC decoding to the processor 310.
Referring to
The register 541 may store the expected error count EEC of each of the first data unit and the second data unit on which the first ECC decoding is failed, from among the plurality of data units HDRDs, may provide the comparator 543 with the expected error count EEC of each of the first data unit and the second data unit on which the first ECC decoding is failed as the first expected error count EEC1 and the second expected error count EEC2, respectively.
The comparator 543 may generate a comparison signal CS by comparing the first expected error count EEC1 and the second expected error count EEC2 and may provide the comparison signal CS to the control logic 545.
The control logic 545 may be connected to the defective sector buffer 535 and the first sector buffer 531 and may control an updating operation of the defective sector buffer 535 based on the comparison signal CS. That is, the control logic 545 may control updating of the first data unit and the second data unit in the defective sector buffer 535 based on the comparison signal CS. In addition, the control logic 545 may generate the selection signal SEL with a first logic level when the first ECC decoding is performed, may generate the selection signal SEL with a second logic level when the second ECC decoding is performed and may provide the selection signal SEL to the multiplexer 537.
In
Referring to
An LDPC code having a codeword length of s and an information length of t may be represented by a parity check matrix (PCM) having a size of (s−t)*s. The LDPC code has a higher correction capability as the codeword length is long. For example, the memory controller may use a codeword longer than 1 KB. For example s is greater than 8192. The size of the PCM of the long codeword is very large and it is difficult to store the PCM of a large size.
To solve such problems, the PCM may be divided into a plurality of sub blocks (i.e., sub matrices) and the PCM may be defined by information of each sub matrix, for example, a position of each sub matrix, a shape of each sub matrix, etc. The LDPC code defined as such may be referred to as a quasi-cyclic LDPC (QC-LDPC) code. For example, it is assumed that the codeword length is 1055 bits and the information length is 422 (=1055-633). If the size of the sub matrix is 211, five sub matrices may be arranged in each row (1055/211=5) and three sub matrices may be arranged in each column (633/211=3) as illustrated in
Referring to
The plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 sequentially stored in the first sector buffer 531 is sequentially provided to the main decoder 560. The main decoder 560 sequentially performs respective one of first ECC decoding HD_DEC11, HD_DEC12, HD_DEC13 and HD_DEC14 on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 and determines whether the first ECC decoding on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 is successful. Based on a result of the first ECC decoding, it is determined that the first ECC decoding on the data unit HDRD1 is failed and the data unit HDRD1 is stored in the defective sector buffer 535 as a defective data unit.
When the first ECC decoding is completed, the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 may be sequentially stored in the buffer memory 250 in
For performing a second ECC decoding, a second read data SDRD1 is read from a sector corresponding to the data unit HDRD1 and the second read data SDRD1 is stored in the second sector buffer 533 as a reference numeral 715 indicates. The main decoder 560 performs a second ECC decoding SD_DEC based on the data unit HDRD1 stored in the defective sector buffer 535 and the second read data SDRD1 and may output a corrected data unit by correcting error in the data unit HDRD1 as a reference numeral 717.
Referring to
The plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 sequentially stored in the first sector buffer 531 are sequentially provided to the main decoder 560. The main decoder 560 sequentially performs respective one of first ECC decoding HD_DEC11, HD_DEC12, HD_DEC13 and HD_DEC14 on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 and determines whether the first ECC decoding on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 is successful. Based on a result of the first ECC decoding, it is determined that the first ECC decoding on the data unit HDRD1 is failed and the data unit HDRD1 is stored in the defective sector buffer 535 as a defective data unit.
When the first ECC decoding is completed, the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 may be sequentially stored in the buffer memory 250 in
For performing a second ECC decoding, the data unit HDRD1 is read from the buffer memory 250 located out of the ECC decoder 520 and is provided to the ECC decoder 520 as a reference numeral 714 indicates and a second read data SDRD1 read from a sector corresponding to the data unit HDRD1 is stored in the second sector buffer 533 as a reference numeral 715 indicates. The main decoder 560 performs a second ECC decoding SD_DEC based on the data unit HDRD1 stored in the defective sector buffer 535 and the second read data SDRD1 and may output a corrected data unit by correcting error in the data unit HDRD1 as reference numeral 717 indicates.
Referring to
The plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 sequentially stored in the first sector buffer 531 are sequentially provided to the main decoder 560. The main decoder 560 sequentially performs respective one of first ECC decoding HD_DEC11, HD_DEC12, HD_DEC13 and HD_DEC14 on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 and determines whether the first ECC decoding on each of the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 is successful. Based on a result of the first ECC decoding, it is determined that the first ECC decoding on the data units HDRD1 and HDRD3 is failed and the data unit HDRD3 is stored in the defective sector buffer 535 as a defective data unit because an expected error count of the data unit HDRD3 is smaller than an expected error count of the data unit HDRD1.
When the first ECC decoding is completed, the plurality of data units HDRD1, HDRD2, HDRD3 and HDRD4 may be sequentially stored in the buffer memory 250 in
For performing a second ECC decoding, a second read data SDRD3 is read from a sector corresponding to the data unit HDRD3 and the second read data SDRD3 is stored in the second sector buffer 533 as a reference numeral 725 indicates. The main decoder 560 performs a second ECC decoding SD_DEC based on the data unit HDRD3 stored in the defective sector buffer 535 and the second read data SDRD3 and may output a corrected data unit by correcting error in the data unit HDRD3 as reference numeral 727 indicates.
Referring to
The ECC decoder 520 in the storage controller 300 sequentially performs a first ECC decoding (hard decision decoding) on each of the plurality of data units HDRDs (operation S130). In this instance, it is determined that the first ECC decoding on one or more data units from among the plurality of data units HDRDs is failed (operation S135), therefore, the ECC decoder 520 stores a data unit having a minimum expected error count, from among the data units on which the first ECC decoding is failed in a defective sector buffer 535 as a defective data unit (operation S140).
The storage controller 300 transmits a read command CMD to the nonvolatile memory device 400a for reading a second read data from a selected sector corresponding to the defective data unit (operation S150). The nonvolatile memory device 400a performs a second read operation on the selected sector, based on offset read voltages, in response to the read command CMD (operation S155) and transmits a second read data SDRD from the selected sector to the storage controller 300 (operation S160).
The ECC decoder 520 performs a second ECC decoding (soft decision decoding) based on the data unit stored in the defective sector buffer 535 and the second read data SDRD (operation S170) and may output a result of the second ECC decoding (operation S180).
Referring to
The buffer controller 540 checks whether the defective sector buffer 535 is full (operation S220). When the defective sector buffer 535 is not full (NO in S220), the buffer controller 540 stores a current data unit on which the first ECC decoding is failed in the defective sector buffer 535 (operation S230), and the main decoder 560 performs a second ECC decoding (operation S260).
When the defective sector buffer 535 is full (YES in S220), the buffer controller 540 determines when an expected error count EEC1 of a previous data unit that is pre-stored in the defective sector buffer 535 is greater than an expected error count EEC2 of the current data unit (operation S240).
When the expected error count EEC1 of the previous data unit is not greater than the expected error count EEC2 of the current data unit (NO in S240), the main decoder 560 performs a second ECC decoding (operation S260). When the expected error count EEC1 of the previous data unit is greater than the expected error count EEC2 of the current data unit (YES in S240), the buffer controller 540 stores the current data unit in the defective sector buffer (operation S250) and the main decoder 560 performs a second ECC decoding (operation S260).
Therefore, the ECC decoder, the storage controller and the storage device according to example embodiments may reduce a latency of soft decision decoding by storing a hard decision read data (defective read data) having a minimum expected error count in a defective sector buffer in the ECC decoder, from among one or more hard decision read data on which the hard decision decoding is failed, by receiving the defective read data from the defective sector buffer when the second ECC decoding is performed, by receiving a soft decision read data from a sector corresponding to the defective read data, by receiving a syndrome, stored while a hard decision decoding is being performed, from a syndrome buffer in the ECC decoder and by performing the soft decision decoding. In addition, the ECC decoder 520 may reduce a time interval associated with performing a second ECC decoding (soft decision decoding) because the ECC decoder 520 may skip the second ECC decoding on data units except the defective data unit stored in the defective sector buffer, from among the data units on which the first ECC decoding is failed.
Referring to
The storage media 820 may include a plurality of nonvolatile memory devices NVM11, NVM12, . . . , NVMIp, NVM21, NVM22, . . . , NVM2p, NVMk1, NVMk2, . . . , NVMkp. For example, the nonvolatile memory devices NVM11 to NVMkp may correspond to the nonvolatile memory devices 400a˜400k in
The storage controller 810 may select one of the nonvolatile memories NVM11 to NVMks, which is connected to each of the channels CH1 to CHk, by using a corresponding one of the channels CH1 to CHk, and may transmit and receive signals to and from the selected nonvolatile memory device. For example, the storage controller 810 may select the nonvolatile memory NVM11 from among the nonvolatile memories NVM11 to NVM1p connected to the first channel CH1. The storage controller 810 may transmit the command CMDa, the address ADDRa and the DTAa to the selected nonvolatile memory device NVM11 through the first channel CH1 or may receive the DTAa from the selected nonvolatile memory device NVM11.
The storage controller 810 may transmit and receive signals to and from the storage media 820 in parallel through different channels.
Referring to
The semiconductor device 3100 may be a non-volatile memory device, for example, a NAND flash memory device that is explained with reference to
In the second structure 3100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit-line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied in accordance with example embodiments.
In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.
In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected with each other in serial. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistors MCT through gate induced drain leakage (GIDL) phenomenon.
The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 3110 through first connection wirings 3115 extending from the second structure 3110S to the first structure 3100F. The bit-lines BL may be electrically connected to the page buffer circuit 3120 through second connection wirings 3125 extending from the second structure 3100S to the first structure 3100F.
In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130. The semiconductor device 3100 may communicate with the controller 3200 through an input/output pad 3101 electrically connected to the logic circuit 3130. The input/output pad 3101 may be electrically connected to the logic circuit 3130 through an input/output connection wiring 3135 extending to the second structure 3100S in the first structure 3100F.
The controller 3200 may include a processor 3210, a NAND controller 3220, and a host interface 3230. The electronic system 3000 may include a plurality of semiconductor devices 3100, and in this case, the controller 3200 may control the plurality of semiconductor devices 3100.
The processor 3210 may control operations of the electronic system 3000 including the controller 3200. The processor 3210 may be operated by firmware, and may control the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 may include a NAND interface 3221 for communicating with the semiconductor device 3100. Through the NAND interface 3221, control command for controlling the semiconductor device 3100, data to be written in the memory cell transistors MCT of the semiconductor device 3100, data to be read from the memory cell transistors MCT of the semiconductor device 3100, etc., may be transferred. The host interface 3230 may provide communication between the electronic system 3000 and an outside host. When control command is received from the outside host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.
Referring to
The memory device 5000 may include the at least one upper chip including the cell region. For example, as illustrated in
Each of the peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may include an external pad bonding region PA, a word-line bonding region WLBA, and a bit-line bonding region BLBA.
The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements 5220a, 5220b and 5220c formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be provided on the plurality of circuit elements 5220a, 5220b and 5220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 5220a, 5220b and 5220c may be provided in the interlayer insulating layer 5215. For example, the plurality of metal lines may include first metal lines 5230a, 5230b and 5230c connected to the plurality of circuit elements 5220a, 5220b and 5220c, and second metal lines 5240a, 5240b and 5240c formed on the first metal lines 5230a, 5230b and 5230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 5230a, 5230b and 5230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal lines 5240a, 5240b and 5240c may be formed of copper having a relatively low electrical resistivity.
The first metal lines 5230a, 5230b and 5230c and the second metal lines 5240a, 5240b and 5240c are illustrated and described in the present embodiments. However, embodiments of the present disclosure are not limited thereto. In certain embodiments, at least one or more additional metal lines may further be formed on the second metal lines 5240a, 5240b and 5240c. In this case, the second metal lines 5240a, 5240b and 5240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 5240a, 5240b and 5240c may be formed of copper having an electrical resistivity lower than that of aluminum of the second metal lines 5240a, 5240b and 5240c.
The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and may include an insulating material such as silicon oxide and/or silicon nitride.
Each of the first and second cell regions CREG1 and CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word-lines 5330 (5331 to 5338) may be stacked on the second substrate 5310 in a direction (i.e., the third direction VD) perpendicular to a top surface of the second substrate 5310. String selection lines and a ground selection line may be disposed on and under the word-lines 5330, and the plurality of word-lines 5330 may be disposed between the string selection lines and the ground selection line. Likewise, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word-lines 5430 (5431 to 5438) may be stacked on the third substrate 5410 in a direction (i.e., the third direction VD) perpendicular to a top surface of the third substrate 5410. Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystalline epitaxial layer grown on a single-crystalline silicon substrate. A plurality of channel structures CH may be formed in each of the first and second cell regions CREG1 and CREG2.
In some embodiments, as illustrated in a region ‘A1’, the channel structure CH may be provided in the bit-line bonding region BLBA and may extend in the direction perpendicular to the top surface of the second substrate 5310 (i.e., the third direction VD) to penetrate the word-lines 5330, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulation layer. The channel layer may be electrically connected to a first metal line 5350c and a second metal line 5360c in the bit-line bonding region BLBA. For example, the second metal line 5360c may be a bit-line and may be connected to the channel structure CH through the first metal line 5350c. The bit-line 5360c may extend in a second direction HD2 parallel to the top surface of the second substrate 5310.
In some embodiments, as illustrated in a region ‘A2’, the channel structure CH may include a lower channel LCH and an upper channel UCH, which are connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in the direction perpendicular to the top surface of the second substrate 5310 (i.e., the third direction VD) to penetrate the common source line 5320 and lower word-lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulation layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate upper word-lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulation layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As a length of a channel increases, due to characteristics of manufacturing processes, it may be difficult to form a channel having a substantially uniform width. The memory device 5000 according to the present embodiments may include a channel having improved width uniformity due to the lower channel LCH and the upper channel UCH which are formed by the processes performed sequentially.
In the case in which the channel structure CH includes the lower channel LCH and the upper channel UCH as illustrated in the region ‘A2’, a word-line located near to a boundary between the lower channel LCH and the upper channel UCH may be a dummy word-line. For example, the word-lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be the dummy word-lines. In this case, data may not be stored in memory cells connected to the dummy word-line. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word-line may be less than the number of pages corresponding to the memory cells connected to a general word-line. A level of a voltage applied to the dummy word-line may be different from a level of a voltage applied to the general word-line, and thus it is possible to reduce an influence of a non-uniform channel width between the lower and upper channels LCH and UCH on an operation of the memory device.
Meanwhile, the number of the lower word-lines 5331 and 5332 penetrated by the lower channel LCH is less than the number of the upper word-lines 5333 to 5338 penetrated by the upper channel UCH in the region ‘A2’. However, embodiments of the present disclosure are not limited thereto. In certain embodiments, the number of the lower word-lines penetrated by the lower channel LCH may be equal to or more than the number of the upper word-lines penetrated by the upper channel UCH. In addition, structural features and connection relation of the channel structure CH disposed in the second cell region CREG2 may be substantially the same as those of the channel structure CH disposed in the first cell region CREG1.
In the bit-line bonding region BLBA, a first through-electrode THV1 may be provided in the first cell region CREG1, and a second through-electrode THV2 may be provided in the second cell region CREG2. As illustrated in
In some embodiments, the first through-electrode THV1 and the second through-electrode THV2 may be electrically connected to each other through a first through-metal pattern 5372d and a second through-metal pattern 5472d. The first through-metal pattern 5372d may be formed at a bottom end of the first upper chip including the first cell region CREG1, and the second through-metal pattern 5472d may be formed at a top end of the second upper chip including the second cell region CREG2. The first through-electrode THV1 may be electrically connected to the first metal line 5350c and the second metal line 5360c. A lower via 5371d may be formed between the first through-electrode THV1 and the first through-metal pattern 5372d, and an upper via 5471d may be formed between the second through-electrode THV2 and the second through-metal pattern 5472d. The first through-metal pattern 5372d and the second through-metal pattern 5472d may be connected to each other by the bonding method.
In addition, in the bit-line bonding region BLBA, an upper metal pattern 5252 may be formed in an uppermost metal layer of the peripheral circuit region PER1, and an upper metal pattern 5392 having the same shape as the upper metal pattern 5252 may be formed in an uppermost metal layer of the first cell region CREG1. The upper metal pattern 5392 of the first cell region CREG1 and the upper metal pattern 5252 of the peripheral circuit region PREG may be electrically connected to each other by the bonding method. In the bit-line bonding region BLBA, the bit-line 5360c may be electrically connected to a page buffer included in the peripheral circuit region PER1. For example, some of the circuit elements 5220c of the peripheral circuit region PREG may constitute the page buffer, and the bit-line 5360c may be electrically connected to the circuit elements 5220c constituting the page buffer through an upper bonding metal pattern 5370c of the first cell region CREG1 and an upper bonding metal pattern 5270c of the peripheral circuit region PER1.
Referring to
The cell contact plugs 5340 may be electrically connected to a row decoder included in the peripheral circuit region PER1. For example, some of the circuit elements 5220b of the peripheral circuit region PREG may constitute the row decoder, and the cell contact plugs 5340 may be electrically connected to the circuit elements 5220b constituting the row decoder through the upper bonding metal patterns 5370b of the first cell region CREG1 and the upper bonding metal patterns 5270b of the peripheral circuit region PER1. In some embodiments, an operating voltage of the circuit elements 5220b constituting the row decoder may be different from an operating voltage of the circuit elements 5220c constituting the page buffer. For example, the operating voltage of the circuit elements 5220c constituting the page buffer may be greater than the operating voltage of the circuit elements 5220b constituting the row decoder.
Likewise, in the word-line bonding region WLBA, the word-lines 5430 of the second cell region CREG2 may extend in the first direction HD1 parallel to the top surface of the third substrate 5410 and may be connected to a plurality of cell contact plugs 5440 (5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuit region PREG through an upper metal pattern of the second cell region CREG2 and lower and upper metal patterns and a cell contact plug 5348 of the first cell region CREG1.
In the word-line bonding region WLBA, the upper bonding metal patterns 5370b may be formed in the first cell region CREG1, and the upper bonding metal patterns 5270b may be formed in the peripheral circuit region PER1. The upper bonding metal patterns 5370b of the first cell region CREG1 and the upper bonding metal patterns 5270b of the peripheral circuit region PREG may be electrically connected to each other by the bonding method. The upper bonding metal patterns 5370b and the upper bonding metal patterns 5270b may be formed of aluminum, copper, or tungsten.
In the external pad bonding region PA, a lower metal pattern 5371e may be formed in a lower portion of the first cell region CREG1, and an upper metal pattern 5472a may be formed in an upper portion of the second cell region CREG2. The lower metal pattern 5371e of the first cell region CREG1 and the upper metal pattern 5472a of the second cell region CREG2 may be connected to each other by the bonding method in the external pad bonding region PA. Likewise, an upper metal pattern 5372a may be formed in an upper portion of the first cell region CREG1, and an upper metal pattern 5272a may be formed in an upper portion of the peripheral circuit region PER1. The upper metal pattern 5372a of the first cell region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by the bonding method.
Common source line contact plugs 5380 and 5480 may be disposed in the external pad bonding region PA. The common source line contact plugs 5380 and 5480 may be formed of a conductive material such as a metal, a metal compound, and/or doped polysilicon. The common source line contact plug 5380 of the first cell region CREG1 may be electrically connected to the common source line 5320, and the common source line contact plug 5480 of the second cell region CREG2 may be electrically connected to the common source line 5420. A first metal line 5350a and a second metal line 5360a may be sequentially stacked on the common source line contact plug 5380 of the first cell region CREG1, and a first metal line 5450a and a second metal line 5460a may be sequentially stacked on the common source line contact plug 5480 of the second cell region CREG2.
Input/output pads 5205, 5405 and 5406 may be disposed in the external pad bonding region PA. Referring to
An upper insulating layer 5401 covering a top surface of the third substrate 5410 may be formed on the third substrate 5410. A second input/output pad 5405 and/or a third input/output pad 5406 may be disposed on the upper insulating layer 5401. The second input/output pad 5405 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through second input/output contact plugs 5403 and 5303, and the third input/output pad 5406 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through third input/output contact plugs 5404 and 5304.
In some embodiments, the third substrate 5410 may not be disposed in a region in which the input/output contact plug is disposed. For example, as illustrated in a region ‘B’, the third input/output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410 and may penetrate an interlayer insulating layer 5415 of the second cell region CREG2 so as to be connected to the third input/output pad 5406. In this case, the third input/output contact plug 5404 may be formed by at least one of various processes.
In some embodiments, as illustrated in a region ‘B1’, the third input/output contact plug 5404 may extend in the third direction VD, and a diameter of the third input/output contact plug 5404 may become progressively greater toward the upper insulating layer 5401. In other words, a diameter of the channel structure CH described in the region ‘A1’ may become progressively less toward the upper insulating layer 5401, but the diameter of the third input/output contact plug 5404 may become progressively greater toward the upper insulating layer 5401. For example, the third input/output contact plug 5404 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other by the bonding method.
In certain embodiments, as illustrated in a region ‘B2’, the third input/output contact plug 5404 may extend in the third direction VD, and a diameter of the third input/output contact plug 5404 may become progressively less toward the upper insulating layer 5401. In other words, like the channel structure CH, the diameter of the third input/output contact plug 5404 may become progressively less toward the upper insulating layer 5401. For example, the third input/output contact plug 5404 may be formed together with the cell contact plugs 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.
In certain embodiments, the input/output contact plug may overlap with the third substrate 5410. For example, as illustrated in a region ‘C’, the second input/output contact plug 5403 may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 in the third direction VD and may be electrically connected to the second input/output pad 5405 through the third substrate 5410. In this case, a connection structure of the second input/output contact plug 5403 and the second input/output pad 5405 may be realized by various methods.
In some embodiments, as illustrated in a region ‘C1’, an opening 5408 may be formed to penetrate the third substrate 5410, and the second input/output contact plug 5403 may be connected directly to the second input/output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as illustrated in the region ‘C1’, a diameter of the second input/output contact plug 5403 may become progressively greater toward the second input/output pad 5405. However, embodiments of the present disclosure are not limited thereto, and in certain embodiments, the diameter of the second input/output contact plug 5403 may become progressively less toward the second input/output pad 5405.
In certain embodiments, as illustrated in a region ‘C2’, the opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. An end of the contact 5407 may be connected to the second input/output pad 5405, and another end of the contact 5407 may be connected to the second input/output contact plug 5403. Thus, the second input/output contact plug 5403 may be electrically connected to the second input/output pad 5405 through the contact 5407 in the opening 5408. In this case, as illustrated in the region ‘C2’, a diameter of the contact 5407 may become progressively greater toward the second input/output pad 5405, and a diameter of the second input/output contact plug 5403 may become progressively less toward the second input/output pad 5405. For example, the second input/output contact plug 5403 may be formed together with the cell contact plugs 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other, and the contact 5407 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other.
In certain embodiments illustrated in a region ‘C3’, a stopper 5409 may further be formed on a bottom end of the opening 5408 of the third substrate 5410, as compared with the embodiments of the region ‘C2’. The stopper 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively, the stopper 5409 may be a metal line formed in the same layer as at least one of the word-lines 5430. The second input/output contact plug 5403 may be electrically connected to the second input/output pad 5405 through the contact 5407 and the stopper 5409.
Like the second and third input/output contact plugs 5403 and 5404 of the second cell region CREG2, a diameter of each of the second and third input/output contact plugs 5303 and 5304 of the first cell region CREG1 may become progressively less toward the lower metal pattern 5371e or may become progressively greater toward the lower metal pattern 5371e.
Meanwhile, in some embodiments, a slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a certain position of the external pad bonding region PA. For example, as illustrated in a region ‘D’, the slit 5411 may be located between the second input/output pad 5405 and the cell contact plugs 5440 when viewed in a plan view. Alternatively, the second input/output pad 5405 may be located between the slit 5411 and the cell contact plugs 5440 when viewed in a plan view.
In some embodiments, as illustrated in a region ‘D1’, the slit 5411 may be formed to penetrate the third substrate 5410. For example, the slit 5411 may be used to prevent the third substrate 5410 from being finely cracked when the opening 5408 is formed. However, embodiments of the present disclosure are not limited thereto, and in certain embodiments, the slit 5411 may be formed to have a depth ranging from about 60% to about 70% of a thickness of the third substrate 5410.
In certain embodiments, as illustrated in a region ‘D2’, a conductive material 5412 may be formed in the slit 5411. For example, the conductive material 5412 may be used to discharge a leakage current occurring in driving of the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 5412 may be connected to an external ground line.
In certain embodiments, as illustrated in a region ‘D3’, an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second input/output pad 5405 and the second input/output contact plug 5403 disposed in the external pad bonding region PA from the word-line bonding region WLBA. Since the insulating material 5413 is formed in the slit 5411, it is possible to prevent a voltage provided through the second input/output pad 5405 from affecting a metal layer disposed on the third substrate 5410 in the word-line bonding region WLBA.
Meanwhile, in certain embodiments, the first to third input/output pads 5205, 5405 and 5406 may be selectively formed. For example, the memory device 5000 may be realized to include only the first input/output pad 5205 disposed on the first substrate 5210, to include only the second input/output pad 5405 disposed on the third substrate 5410, or to include only the third input/output pad 5406 disposed on the upper insulating layer 5401.
In some embodiments, at least one of the second substrate 5310 of the first cell region CREG1 or the third substrate 5410 of the second cell region CREG2 may be used as a sacrificial substrate and may be completely or partially removed before or after a bonding process. An additional layer may be stacked after the removal of the substrate. For example, the second substrate 5310 of the first cell region CREG1 may be removed before or after the bonding process of the peripheral circuit region PREG and the first cell region CREG1, and then, an insulating layer covering a top surface of the common source line 5320 or a conductive layer for connection may be formed. Likewise, the third substrate 5410 of the second cell region CREG2 may be removed before or after the bonding process of the first cell region CREG1 and the second cell region CREG2, and then, the upper insulating layer 5401 covering a top surface of the common source line 5420 or a conductive layer for connection may be formed.
Referring to
After the various integrated circuits have been respectively formed on the first and second wafers WF1 and WF2, the first wafer WF1 and the second wafer WF2 may be bonded together. The bonded wafers WF1 and WF2 may then be cut (or divided) into separate chips, in which each chip corresponds to a semiconductor device such as, for example, the nonvolatile memory device 5000, including a first semiconductor die SD1 and a second semiconductor die SD2 that are stacked vertically (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each cut portion of the first wafer WF1 corresponds to the first semiconductor die SD1 and each cut portion of the second wafer WF2 corresponds to the second semiconductor die SD2.
The present disclosure may be applied to various electronic devices including a storage device. For example, example embodiments may be applied to systems such as a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash storage (UFS), a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IOT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a server system, an automotive driving system, etc.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0167363 | Dec 2022 | KR | national |
