Patent Application
20100169743
The inventions generally relate to improved reliability in a solid state mass storage product.
A solid state disk (SSD) is a high performance storage device that contains no moving parts. SSDs are much faster than typical hard disk drives with conventional rotating magnetic media, and typically include a controller to manage data storage. The controller manages operations of the SSD, including data storage and access as well as communication between the SSD and a host device. The controller also performs Error Correction Code (ECC) to assure integrity of the data written on the SSD. ECC identifies and corrects errors in data communicated between the SSD and the host device. However, some failure mechanisms of the storage media exceed the correction capabilities of the ECC engine resulting in unrecoverable data or data loss. For example, a catastrophic die failure.
U.S. patent application Ser. No. 11/396,262 filed on Mar. 31, 2006 and entitled “Improving Reliability of Write Operations to a Non-Volatile Memory” addresses program failure by keeping a copy of all the data written to an erase block until the last program operation succeeds. This patent application addresses program failure issues rather than ECC failure issues or die failure issues. Therefore, a need has arisen to address ECC failures and/or die failures.
The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only.
Some embodiments of the inventions relate to improved error correction in a solid state disk.
In some embodiments, a solid state disk (SSD) includes a non-volatile memory and a controller. The controller performs ECC (Error Correcting Code) on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data.
In some embodiments, a system includes a host and a solid state disk. The solid state disk includes a non-volatile memory and a controller. The controller performs ECC on host data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data.
In some embodiments, ECC is performed on data stored on a non-volatile memory of a solid state disk. A parity operation is performed on the data if the ECC cannot correct the data.
In some embodiments exclusive OR (XOR) error correction code (ECC) techniques are used to protect a solid state disk (SSD) from component level failure, programming failures (for example, NAND programming failures), and/or uncorrectable errors from the primary ECC system. For example, in some embodiments, parity techniques (for example, Redundant Arrays of Independent Disks or RAID implementations) that are similar to those used in mass storage environments may be implemented in the non-volatile memory environment of an SSD. In some embodiments, write data from the host flows through an XOR parity generator, and the host data plus the parity is written to the non-volatile memory. In the event that the primary ECC engine of the SSD cannot correct a host sector, or in the event that a die (for example, a NAND die) has failed, a second level of error correction in implemented according to some embodiments in order to obtain the correct data.
In some embodiments, parity and host data, excluding the uncorrectable sectors, are read from the media and the missing data is recovered using an XOR operation. In a case of a program failure such as a NAND program failure where data previously written to an erase block has been corrupted when a program failure occurs on a subsequent write/program within the same erase block, each of the previously written but currently corrupted pages in the erase block are recovered one at a time using an XOR operation. The same type of XOR operation may be used in the case of a primary ECC failure or a program failure.
Since a single SSD may contain around 80 NAND die, the mean time to failure (MTTF) of an SSD product may be increased according to some embodiments by approximately six times longer due to the ability to tolerate a NAND die failure and continue operation without data loss. This MTTF improvement is very significant. Further, according to some embodiments, data reliability relative to implementations using primary ECC is increased by several orders of magnitude. This is because when reading, if the ECC correction fails due to more error bits than the ECC can correct, redundant XOR data may be used to reconstruct the original data. Similarly, when writing, if a program failure occurs that corrupts other data on the same erase block, the reconstruction of corrupted data may be performed according to some embodiments. These are critical improvements in for SSDs and for NAND memory, particularly as NAND memory becomes based on finer lithography.
As illustrated in
In embodiments with one parity slot 79 as described above, in the event of an uncorrectable error in any sector of any page of slots 00 through 78, the SSD can read that sector number from all of the pages except for the one in error, and XOR the content of those sectors along with the corresponding parity sector in slot 79 in order to recover the missing content. In some embodiments, ECC such as Bose-Chaudhuri-Hocquengen (BCH) correction occurs on each sector, including the parity, and an uncorrectable state is used to trigger the second level of ECC recovery by XORing the content.
In the embodiments discussed above with one parity slot 79, a single parity page per array of slots 00 through 78 will protect from hard errors and catastrophic die failure. In embodiments, in which protection against component failure that takes out more than one slot other implementations are available according to some embodiments. For example, in order to protect against component failure that would take out two slots, two parity pages may be inserted per slot array (for example, at slots 39 and 79). The parity at slot 39 may be used to cover slots 00 to 38, and the parity at slot 79 may be used to cover slots 40 to 78 in some embodiments. The slot array may be adjusted accordingly so that a package failure would take out one slot from the parity stripe of slots 00 to 39 and a second slot from the parity stripe of slots 40 through 79. For example, if package 5 is mapped with two CE into slots 5 and 45, then the described parity stripes would protect from component failure at a capacity cost of 2.5%. The capacity cost may be cut in half if die failures (and not package failures) are to be protected.
While XOR has been used previously in multiple mass storage device environments, according to some embodiments a technique is available to protect content from catastrophic component failure in the context of a single storage device (for example, an SSD). In an SSD environment, where indirection allows all writes essentially to be sequential, there is no penalty associated with random write operations. In addition, problems that are particular to SSDs such as NAND programming failures resulting in a loss of previously written data may be solved according to some embodiments. In some embodiments, program failures are addressed in a low cost manner, and additionally addresses die failures and ECC failures.
Although some embodiments have been described herein as being implemented in a particular manner, according to some embodiments these particular implementations may not be required. For example, although
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by a computing platform to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, the interfaces that transmit and/or receive signals, etc.), and others.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
Although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the inventions are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state or in exactly the same order as illustrated and described herein.
The inventions are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.
