ERROR CORRECTION METHOD

Abstract

This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a general view showing an information processing unit having an error correction function which is one embodiment of the present invention;

FIG. 2 is a detailed view showing a rollback control unit in one embodiment of the present invention;

FIG. 3 is a detailed view showing an output unit of a CPU and an error mask circuit of in one embodiment of the present invention;

FIG. 4 is a timing chart for reference, showing an operation example in which a condition that DPCK is less than DCL_MIN is not satisfied in one embodiment of the present invention;

FIG. 5 is a timing chart showing an operation example in which a condition that DPCK is less than DCL_MIN is satisfied in one embodiment of the present invention;

FIG. 6 is a state transition diagram of a rollback state machine in one embodiment of the present invention;

FIG. 7 is a detailed view showing an instruction queue in one embodiment of the present invention;

FIG. 8 is a detailed view showing a store queue in one embodiment of the present invention;

FIG. 9 is a detailed view showing a CPU bus error detector in one embodiment of the present invention;

FIG. 10 is a flowchart showing a rollback exception routine in one embodiment of the present invention;

FIG. 11 is a timing chart showing an example of a rollback operation in one embodiment of the present invention; and

FIG. 12 is a timing chart showing an operation example of preventing an erroneous CPU bus write in one embodiment of the present invention.

Claims

1. An error correction method, wherein, when an error is detected in a CPU with pipeline struct, the content of a register file is restored from a delayed register file, which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed,the error correction method collecting a parity check result of a arbitrary Flip-Flops existing inside the CPU and detecting the error.

2. The error correction method according to claim 1, wherein the [instruction N+1] is an instruction decoded first by the CPU among at least one or more instructions executed at the timing on which the error occurs.

3. The error correction method according to claim 1, wherein a CPU signal inputted to the rollback control unit that performs the rollback control nullifies the CPU signal delayed by a latency portion of the error detection signal by an error detection signal, andwherein an output delay of the error detection signal is adjusted to be less than the minimum value of the output delay of the CPU signal.

4. An error correction method, wherein, when an error is detected in a CPU with pipeline struct, the content of a register file is restored from a delayed register file, which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N],wherein, if an error exists in the CPU bus write accompanied with the execution of the instruction subsequent to the error occurrence, that error is detected and nullified.

5. The error correction method according to claim 4, wherein the instruction generating the content of a source operand is disposed before the instruction accompanied with the CPU bus write so that the source operand of the instruction accompanied with the CPU bus write is reflected on the delayed register file before the CPU bus write,wherein the error of the CPU bus write is detected using the read value of the delayed register file, and cancelled.