Error correction structures and methods

Abstract

A parallel Chien search by partitioning of the nonzero elements of a root field and using a parallel Galois multiplier.

Description

BACKGROUND OF THE INVENTION

[0002] The invention relates to electronic devices, and, more particularly, to error correction structures and methods.

[0003] Digital communication and storage systems typically include error correction coding in order to overcome errors arising from the transmission or storage medium. Forward error-correction coding (FEC) systems add redundancy to the transmitted signal so that the receiver can detect and correct errors using only the received signal. This eliminates the need for the receiver to send requests for retransmission to the transmitter.

[0004] FIGS. 1-2 are high level views of a FEC system. In particular, FIG. 1 shows a block of information symbols, I, transformed into a codeword C which is a larger block that contains both the original information and redundant symbols. After transmission over a channel, the received block of symbols can be represented as C+E where E is a block of error symbols. The decoder generates I′ from C+E, and I′ will equal I if the number of errors symbols in E is within the correction capabilities of the code.

[0005] FIG. 2 shows a more detailed description of the coding. A block of bk information bits is divided into k groups of b bits and each group of b bits represents a symbol, producing a block of k information symbols for coding. The encoder operates on the block of k information symbols to produce a codeword block of n symbols containing the original information in some form as well as redundancy. The code can be designed so that the redundancy is used for error detection only, error correction only, or a combination of some error detection and some error correction. The codeword block of n symbols is then translated into a block of bn bits and transmitted over the channel. The receiver front-end produces a block of bn bits that might be corrupted, depending upon the amount of channel distortion. The block of bn bits is translated into a block of n symbols and processed with the decoder. As long as the transmission errors lead to at most t=(n-k)/2 erroneous symbols, a hard-decision decoder can reliably recover the input k information symbols (and thus the input bk bits). The price paid for the added redundancy is the increase in the number of symbols to transmit by a factor of n/k. Of course, this means an information decrease by a factor of k/n for a constant transmission rate.

[0006] One of the more popular error correction code types is BCH codes which are cyclic block codes that utilize Galois fields beyond the simplest GF(2) (the usual binary {0,1}) to prescribe code generator polynomials. Indeed, a BCH code uses a minimal degree generator polynomial with roots being a sequence of powers of a primitive element of a Galois field which may be an extension field of the symbol field (codeword components field). This leads to computations involving multiplications of Galois field elements for the usual decoding steps of syndrome calculation, association with error pattern (determine error-locator polynomial and error locations and values), and error correction. Reed-Solomon codes are a subclass of BCH codes with both symbols and generator polynomial roots in the same field GF(pm). The commonly used field GF(2m) allows the elements to be represented as m-bit words.

[0007] The nonzero elements of a Galois field form a cyclic multiplicative subgroup and can be expressed as powers of a primitive element α. That is, the elements of GF(pm) are {0, 1, α, α2, . . . , αq} where the maximum q=pm−2 and αq+1=1. Thus the roots of a generator polynomial G(x) for a BCH code could be {α, α2, . . . , α2} for a code which can correct t errors per codeword. The generator polynomial thus would be the least common multiple of the polynomials φ(x) for j=1, 2, . . . , 2 t where φ(x) is a minimal polynomial for αj. The special case of the symbol field being the same as the root field (Reed-Solomon codes) implies φ(x) is simply x-αj.

[0008] Systematic BCH encoding, as with cyclic codes in general, forms codewords by concatenating the k information symbols with n-k parity symbols which are computed according to xn-kI(x) modG(x). The additional n-k parity symbols contain the redundant information that is used by the receiver to choose the most likely transmitted k information symbols. In particular, with receiver soft decision the n-k parity symbols can be used to correct t error symbols and detect s erased symbols provided 2 t+s is at most equal to n-k. Note that values such as n=204 and k=188 with the field GF(28) in a Reed-Solomon code is a commonly used (shortened) code for high speed modems. Such a (204, 188) code can correct 8 error symbols per 204-symbol codeword. Similarly, the (200, 192) code can correct 4 errors per 200-symbol codeword.

[0009] FIG. 3 is a flow chart for a commonly-used method of errors-only decoding BCH coded information and which proceeds as follows. Take n-k=2 t so that at most t errors can be corrected in a codeword of n symbols. The received polynomial R(x)=C(x)+E(x) where C(x) is the codeword polynomial and E(x) is the error polynomial. E(x)=Σjejxj with a non-zero ej the error occurring in the jth position (symbol) of C(x). The decoder is to find the error positions and values to reconstruct E(x) and then recover C(x) as R(x)−E(x). The method first evaluates R(x)=r0xn-1+r1xn-2+. . . +rn-1 at the 2 t roots of the code generator polynomial (G(x)=IIj(x-αj) for Reed-Solomon) and denotes these 2 t evaluations as the syndromes S0, S1, S2, . . . , S2t-1. That is, with the roots of G(x) being αj for j=0, 1, 2, . . . , 2 t−1 (which are denoted β0, β1, β2, . . . , β2t-1, respectively) the syndromes are (with * denoting Galois field multiplication):

S 0 =r 0 * β0n-1+r1*β0n-2+r2*β0n-3+. . . +rn-2*β0+rn-1

S 1 =r 0 * β1n-1+r1*β1n-2+r2*β1n-3+. . . +rn-2*β1+rn-1

S 2t-1 =r 0 * β2t-1n-1+r1*β2t-1n-2+r2*β2t-1n-3+. . . +rn-2*β2t-1+rn-1

[0010] Because C(x) is a product of G(x), C(x) vanishes at each of the 2t roots of G(x), and the syndrome Sj equals E(βj). Thus the 2t syndrome equations are nonlinear relations between the 2t syndromes, the at most t error locations, and the at most t error values; that is, 2t nonlinear equations for at most 2t unknowns.

[0011] Next, linearize these nonlinear syndrome equations by introduction of the error locator polynomial, Λ(x)=IIm(1+Xmx)=1+ΣmΛmXm, where Xm is the mth error location. The error locator polynomial has degree equal to the (not-yet-known) number of errors. That is, Xm=αj for the mth j for which ej is nonzero, and the roots of Λ(x) are the inverses of the error locations.

[0012] Multiplying the defining equation for Λ(x) by the error values and powers of the error locations and summing leads to n-k-e linear equations for the e unknowns Λj with coefficients of these linear equations being an array of the syndromes S0 to S2e-2 and the inhomogeneous terms being the sequence of syndromes Se to S2e-1. The number of errors, e, is unknown, so the linear equations cannot be simply solved. Rather, the method of FIG. 3 uses the iterative and inductive Berlekamp-Massey method to find the Λj.

[0013] Once the locator polynomial is known, find its roots (the inverses of the error locations) using the Chien search. The Chien search systematically evaluates the locator polynomial Λ(x) at all non-zero possible values of the variable and checks for zeros by repeatedly computing Λ(αj) and incrementing j.

[0014] Inserting the error locations into the definitions of the syndromes yields simple linear equations for the error values. In fact, the Forney algorithm in FIG. 3 computes the error values without matrix inversion to solve the linear equations. And combining the error values and error locations reconstructs the error polynomial E(x) to subtract from R(x) and lastly recover error-free C(x).

[0015] However, efficient computation of the Chien search has problems for systems, especially for systems in which the code (generator polynomial) may change and parallel multiplication is available.

SUMMARY OF THE INVENTION

[0016] The present invention provides a BCH code Chien search method with partitioning of the search into subsets for parallel computation with a parallel multiplier.

[0017] This has the advantages of full parallel multiplier usage in Chien search.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings are heuristic for clarity.

[0019] FIGS. 1-2 schematically illustrate FEC coding.

[0020] FIG. 3 is a flow for BCH decoding.

[0021] FIGS. 4 a -4c show a preferred embodiment Galois multiplier.

[0022] FIGS. 5 a -6 show preferred embodiment Chien search.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] System overview

[0024] Preferred embodiment Chien searches partition the multiplicative subgroup of the root field GF() into subsets and perform parallel simultaneous searches in the subsets and thereby fully load a parallel Galois multiplier. The subsets are conveniently taken as sequences of powers of a primitive element of the root field. Preferred embodiment systems include a digital signal processor with a parallel Galois multiplier, parallel Galois adder (XOR), and memory which implement these Chien searches and other methods to provide realtime decoding of BCH (including Reed-Solomon) coded streams such as used in ADSL communications.

[0025] Chien search preferred embodiments

[0026] The first preferred embodiments use GF(256) symbols with (n,k) Reed-Solomon codes with n-k=16 and 8, and with n even or odd. The elements of GF(256) can be expressed as 8-bit symbols (bytes). Also, the first preferred embodiments include a 32-bit GF(256) multiplier which can multiply in parallel 4 pairs of GF(256) elements to yield 4 products as illustrated in FIGS. 4a-4c but with a latency of 4 cycles.

[0027] Once the error locator polynomial, Λ(x), has been found (that is, the coefficients Λi for i=1, 2, . . . , e are found), find the roots of Λ(x) by checking if Λ(αj)=0 for j=0, 1, 2, . . . , 254 to exhaust all possibilities; this is the Chien search. Of course, Λ(0)=Λ0=1, so 0 is never a root of Λ(x).

[0028] First, note that Λ(αj)=1+Λ1*αj+Λ2*αj2+. . . +Λe*αje. Thus incrementing j amounts to multiplying the mth power term, Λm*αj, by αm to obtain Λm*α0+10m. The initial (j=0) mth power term is simply Λm. Thus a circuit as illustrated in FIG. 5a (in which the polynomial coefficients are denoted by σm rather than Λm) evaluates the polynomial on each iteration. And if Λ(αj)=0, then αj is stored in a root table.

[0029] Rather than treating the error locator polynomial as of degree e and ending the summation of terms with m=e, the error locator polynomial can be taken to have degree t=8 with the coefficients Λm for m>e set equal to 0. Thus the loop summing the terms Λm*αjm can be taken of fixed length t.

[0030] The preferred embodiments also change the search to first partition the 255 non-zero elements of GF(256) into four subsets of 64 elements each: {αj for j=0, 1, 2, . . . , 63}, {αj for j=64, 65, 66, . . . , 127}, {αj for j=128, 129, 130, . . . , 191}, and {αj for j=192, 193, 194, . . . , 255}. Note that α255 equals α0=1.

[0031] Then perform searches through the four subsets simultaneously for roots of Λ(x) using the parallel Galois multiplier. Each of these four searches in effect is a circuit somewhat analogous to that of FIG. 5a, see FIG. 5b. The initial (j =0) mth power terms of the four searches are Λm, Λm*α64m, Λm*α128m, and Λm*α192m, respectively; and each increments by multiplication by αm just as if the search had not been partitioned. FIG. 6 illustrates the four parallel multiplications by αm in a parallel Galois multiplier and the accumulation in a register (Galois addition is bitwise XOR and is done four in parallel). After the t multiplies and accumulations, the register holds {Λ(αj), Λ(αj+64), Λ(αj+128), Λ(αj+192)}. These four entries are checked to see which are zero and the register reset to {1,1,1,1} and j incremented; this uses the full parallel capacity of the Galois multiplier.

[0032] Error location polynomial degree

[0033] The latency of the Galois multiplier is not a problem unless the degree of the error locator polynomial is less than the latency because a product output in the jth loop is not multiplied again until the j+1 loop. In particular, see FIG. 6 which shows the Λn*αnj terms being loaded into the Galois multiplier while the Λm*αm(j+1) terms are being read out of the multiplier both into the accumulator for the Λ(αj+1) summation and back into the memory for the multiplication Λm*αm(j+1)*αm of the j+2 iteration. Of course, the tables in FIG. 6 would be in memory, and the offset between the read pointer and write pointer matches (or exceeds) the latency of the Galois multiplier. In particular, if t=8 and a degree 8 error location polynomial (with high order coefficients possibly 0) is being used, and the Galois multiplier has latency 4, then Λm*αm(j+1) will be in memory for 4 cycles (=8−4). In contrast, if t=4, so an degree 4 error location polynomial is being used, the product Λm*αm(j+1) will be stored just in time for use in the j+2 iteration multiplication: Λm*αm(j+1)*αm. Thus there is no loss in using the fixed degree t polynomial instead of an actual lower degree polynomial if there are fewer than 4 errors.

[0034] Indeed, the case of t=4 can just use the case t=8 by zeroing out the high degree coefficients Λm for m>4 and thereby reuse the same program as for t=8 and limit program memory.

[0035] Alternatives

[0036] In the case of a parallel Galois multiplier with P parallel multiplications, the analogous preferred embodiments partition the multiplicative subgroup of GF(256) into P subsets {αj for j=0, 1, 2, . . . , J−1}, {αj for j=J, J+1, . . . , 2J−1}, {αj for j=2J, 2J+1, . . . 3J−1}, et cetera, where J is the smallest integer at least as large as 255/P. (note that the last subset may generate duplications because the exponent exceeds 254). Then perform P parallel polynomial evaluations as before.

[0037] Also, the searches may decrement the index starting at j=255, 191, 127, and 63 and ending at j=192, 128, 64, and 0 with multiplications by α−m.

[0038] Or a combination of increment and decrement: start two at j=64 and decrement down plus increment up, plus start two at j=192 and increment and decrement.

[0039] Modifications

[0040] The preferred embodiments can be modified in various ways while retaining the feature of parallel Chien searches and fixed length error location polynomials with a parallel multiplier and parallel adder and scalable evaluations for use with changes in code error-correction capabilities such as t changing from 8 to 4.

[0041] For example, various Galois fields could be used; in particular, GF(2m) for m less than 8 can immediately be implemented by just using only the m lefthand bits of a symbol byte: the Galois multiplier yields a product in the same lefthand m bits for a given m by applying a corresponding mask in the partial product combinations.

[0042] Further, codes with various error-correction capabilities (e.g., t values from 1 to 8) can be handled by the same search method with use of a higher t value and just taking error locator polynomial coefficients as 0. For t larger than 8, the method can be scaled up by just increasing the length of the evaluation loops: if the Galois multiplier can handle P parallel multiplies, then partition the Galois field into P subsets and ┌(number of nonzero field elements)/P┐ loops suffice.

[0043] Of course, the same searches (with the 0 element included) can be used to find the roots of any polynomial (not just error locator polynomials) over a finite field.

Claims

1. A method of BCH decoding, comprising: (a) partitioning a root field into P subsets with P an integer greater than 1; (b) evaluating an error locator polynomial for each of said P subsets with a multiplier capable of P parallel multiplications.

2. The method of claim 1, wherein: (a) when said error locator polynomial has degree less than maximal for said BCH code, extending said polynomial with one or more 0 coefficients.

3. The method of claim 2, wherein: (a) said extending said polynomial includes at least one 0 coefficient for a degree higher than said maximal for said BCH code.

4. A method of error locator polynomial evaluation, comprising: (a) providing a Galois multiplier with latency L cycles with L an integer greater than 1 for P parallel multiplications with P a positive integer; (b) partitioning the nonzero elements of a Galois field into P subsets; (c) evaluating in parallel an error locator polynomial for each of said P subsets using said Galois multiplier.