Error detection mechanism for quantum bits

Abstract

A feedback controller is provided to generate a quantum feedback operation to control one or more ancilla qubits in a quantum error correcting code. The quantum feedback operation is based on the measurement of the one or more ancilla qubits. The feedback controller is operable to dynamically adjust a state discrimination according to previous measurements of the one or more ancilla qubits.

Description

BACKGROUND

The present disclosure relates to tracking of qubit errors in quantum computing systems. The disclosure provides a method that can be employed on ancilla-based error correcting codes, where errors on a data qubit are detected without compromising its quantum state by entangling it with an ancilla qubit and measuring the state of the ancilla qubit.

BRIEF SUMMARY

The present disclosure includes a novel method for improving the ability of error correction codes to detect qubit errors. Aspects of the invention make use of operations on measurement qubits which are conditional on previous measurement results thereof. Application of the disclosure is relevant for quantum computing systems which are comprised of qubits which can be coupled to each other to perform entangling operations, state measurement apparatuses capable of performing quantum-non-demolition measurements. The disclosure makes use of a quantum hardware controller capable of detecting the measured state of a qubit and applying operations based on that state within a time frame significantly shorter than the useful lifetime of the state of the qubit.

Aspects of the invention comprise of a state machine whose state is based on measurement results of ancilla qubits. These measurements are generated periodically during error correction cycles of a quantum system, and their outcome depends on the quantum operations applied to the ancilla and data qubits during their evolution, whether by deliberate design or due to errors. In particular, the measurement outcomes may depend on the parity, in some chosen basis, of the states of data qubits which are coupled to it via entangling gates. The state machine comprises of a finite number of states. These states determine which of a set of possible operations on the qubits are applied during the error correction cycle. The state machine is designed to minimize the probability that the operations performed on the qubits during the error cycle, both deliberately and due to noise, will lead to faulty error correction operations.

In addition to the above, aspects of the invention make use of a parallelization mechanism which enables quantum operations to be performed in parallel with the processing required to perform the conditional operations. This parallelization mechanism allows performance of conditional operations with a latency that is substantially shorter than the round-trip time between the quantum system and the hardware controllers.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a depiction of the operating principle in accordance with an example embodiment of the invention

FIG. 2 illustrates and example of the states of the state machine which implements example aspects of the invention.

FIG. 3 is a general hybrid quantum/classical gate sequence which implements the example state machine described in FIG. 2, which sequence may continue indefinitely in both directions.

FIG. 4 is a specific non-limiting example of hybrid quantum/classical gate sequence for performing the improved error correction cycle which uses an ancilla qubit for the detection of bit flip errors on two adjacent data qubits

FIG. 5 is an example illustration of the expected benefit of the correction scheme.

FIG. 6 provides example proof that the measurement outcomes provide the error detection events.

FIG. 7 is an example pseudo-code implementation of a particular non-limiting example of the state system corresponding to the example in FIG. 4.

FIG. 8 shows an example quantum orchestration platform.

DETAILED DESCRIPTION

Various aspects of the present disclosure are presented by way of example. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component, or a first section could be termed a second element, a second component, or a second section without departing from the teachings of the present disclosure.

Aspects of the invention comprise an implementation of a feedback control mechanism which controls the quantum state of an ancilla qubit that is typically (but not always) used to measure the parity, in some chosen basis, of a quantum state of data qubits in an error correcting code. Feedback control is performed by measuring the state of the qubits and subsequently sending electromagnetic control to the qubits based on the measurement results.

The feedback controller employs a state machine with a particular state update logic that is designed to minimize the probability of readout errors from the measured qubits, as well as minimize the effect of the measurement on qubits that are not being measured.

The state machine may be implemented in practice using electronic programmable logic arrays, integrated circuit logic, software which is executed on a CPU or any other means which can store a representation of the state machine. The hardware will also affect the generation of electromagnetic pulses and quantum state estimation operations in a timely manner based on the state of the state machine.

An example controller state machine logic is depicted in FIG. 1. The state machine has two binary states, r and f, which can take the values 0 and 1. At the beginning of the code operation, the controller states are initialized to 0, and the state of the ancilla qubit is initialized to the ground state (g). After the initialization step, the code cycle repeats at least once. During the cycle, at step n, the controller applies an operation that rotates the state of the ancilla by π around an axis situated on the equator of the Bloch sphere if and only if f_n=1. The parity of the number of bit-flips of all other operations, quantum or otherwise, and intentional or otherwise, which are performed on the ancilla qubit during the cycle time, are denoted by {circumflex over (p)}_n. The state of the qubit is then measured and placed in the binary register r_n. The state machine then updates its state using the rule f_n+1=f_n⊕r_n and r_n+1=m_n.

When operated in the manner described above, the measurement outcomes m_n correspond to error detection events D_n. Namely, m_n=D_n, where D_n={circumflex over (p)}_n⊕{circumflex over (p)}_n−1. This claim is proved in FIG. 6.

The state diagram of the state machine is shown in FIG. 2. The arrows correspond to the measurement outcome m_n and the state corresponds to the binary values of f_n and r_n.

The state machine can also be described using a hybrid quantum/classical gate sequence as shown in FIG. 3. In this figure it is made clear that the operation applied at step n+1 depends on measurement outcomes from step n−1, since f_n+1=f_n⊕m_n−1. In state of the art and representative quantum computing implementations, the feedback response latency is shorter than a single cycle time, and therefore this control mechanism allows the feedback response to be prepared in parallel with the non-conditional quantum operations performed by the controller. This parallelism is a fundamental part of the invention and provides the benefit that the feedback response time can be minimized.

A more particular example of the operation of the controller is depicted in FIG. 4. This example is a particular representation of the invention and does not limit its scope. For this example, the state of the ancilla qubit is flipped by an integer number of π rotations around a vector perpendicular to the equator, whose parity is {circumflex over (p)}_n. This parity is determined by the quantum state of two adjacent data qubits whose state is entangled with the state of the ancilla via CZ quantum gates. Additional single qubit −√{square root over (Y)} and a conditional operation which is equal to √{square root over (Y)} if f_n=0 and to −√{square root over (Y)} if f_n=1 performs the feedback control. In this example, no additional gates are required to perform the control operation. A pseudo-code implementation of this control logic is found in FIG. 7.

State of the art hardware control methods used for the purpose of sensing detection events use control mechanisms that are conditioned only on the measurement outcome at a particular cycle. These mechanisms have two disadvantages. The first is that feedback latency is necessarily added to the cycle time, which increases the error probability per cycle and thus may lower significantly the effectiveness of the code for certain implementations. The second is that the measurement outcomes do not directly represent the detection events, which are actionable and meaningful quantities extracted during the code cycle. Importantly, this means that the states of the ancilla measurement qubits are not controlled to be with high probability in specific states (e.g. the ground state), chosen to represent the no error detection state, which leads to sub-optimal error detection probabilities as we show in the next two paragraphs.

A specific mechanism by which the measurement error probability of the ancilla qubits may be reduced is depicted in FIG. 5. The figure plots representative graphs of the likelihood probability density functions for the estimator of the state of the qubit. The likelihoods are defined given that the qubit was prepared in the ground state, f (I|g) (panel a) and in the excited state f(I|e) (panel b). The abscissa of the graph represents a value measured by the controller for the purpose of state estimation, and the ordinate represents the empiric frequency of a particular outcome I. Quantum state estimation is performed by calculating the sign of I−I_th, where I_th is a threshold value chosen in an optimal manner. In this example we estimate excited state, e, when I>I_th and ground state, g, otherwise. In typical scenarios the qubit tends to decay to the ground state during a quantum-non-demolition measurement, and therefore p (I<I_th|e)>p (I>I_th|g), where p(I<x|a)=∫_−∞^xf(x|a)dx. Therefore, the estimation error, p_err=p(I>I_th|g)p(g)+p(I<I_th|e)p(e) can be reduced by reducing the prior distribution p(e). As explained above, this prior distribution is minimized when the measurement outcomes m_n provide the detection events D_n directly, since in this case the ancillas are in the excited state for the minimal duration required to deduce a detection event. Moreover, the discrimination threshold, I_th, can also be optimized once the prior distribution p(e) is minimized to give the overall minimal error probability, p_err.

Furthermore, the discrimination threshold, I_th, can also be set during the execution of the detection protocol itself to reflect the prior knowledge of the previous measurements to reflect changes in, p(e), given different previous states, i.e. p(m_n=e|m_n−1=e)≠p(m_n=e|m_n−1=g). Here, again, real-time feedback is required where the new threshold is calculated during the time between the end of the previous measurement, m_n−1 and the discrimination stage of the current measurement, m_n. An optimal feedback latency would not limit this time.

FIG. 8 shows an example quantum orchestration platform (QOP). The system comprises a quantum programming subsystem 802, a quantum controller 810, and a quantum processor 820.

The quantum programming subsystem 802 comprises circuitry operable to generate a quantum algorithm description 806 which configures the quantum controller 810 and includes instructions the quantum controller 810 can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control and readout pulse(s) 814, read and process the readout and feedback pulses 818, perform real-time decision making and other calculations, based or not based on measurements, to generate the appropriate control and readout pulses and process and stream results 808, etc.) with little or no human intervention during runtime. In an example implementation these results may be used to perform quantum error correction as described above in reference to one or more of FIGS. 1-7. The quantum controller 810 can perform the quantum error correction protocols described above in reference to FIGS. 1-7 with feedback latencies that for typical quantum processing units would not limit the protocol and the error detection cycle duration. In an example implementation, the quantum programming system 802 is a personal computer comprising a processor, memory, and other associated circuitry (e.g., an x86 or x64 chipset) having installed on it a quantum orchestration software development kit (SDK) that enables creation (e.g., by a user via a text editor and/or by automated quantum algorithm description generation circuitry) of a high-level (as opposed to binary or “machine code”) quantum algorithm description 806. In an example implementation, the high-level quantum algorithm description uses a high-level programming language (e.g., Python, R, Java, Matlab, etc.) simply as a “host” programming language in which are embedded the QOP programming constructs.

The high-level quantum algorithm description may comprise a specification and a program. Although the specification and program may be part of one or more larger databases and/or contained in one or more files, the remainder of this disclosure will, for simplicity of description, assume the configuration data structure and the program data structure each takes the form of a plain-text file recognizable by an operating system (e.g., windows, Linux, Mac, or another OS) on which quantum programming subsystem runs. The quantum programming subsystem 802 then compiles the high-level quantum algorithm description 806 to a machine code version of the quantum algorithm description 806 (i.e., series of binary vectors that represent instructions that the quantum controller's hardware can interpret and execute directly). An example implementation of the data structures/vectors used for realizing the machine code version of the quantum algorithm description are described below.

The quantum programming subsystem 802 is coupled to the quantum controller 810 via interconnect 804 which may, for example, utilize universal serial bus (USB), peripheral component interconnect (PCIe) bus, wired or wireless Ethernet, or any other suitable communication protocol. The quantum controller 810 comprises circuitry operable to load the machine code quantum algorithm description 806 from the programming subsystem 802 via interconnect 804. Then, execution of the machine code by the quantum controller 810 causes the quantum controller 810 to generate the necessary outbound quantum control pulse(s) 814 that correspond to the desired operations to be performed on the quantum processor 820 (e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.). Depending on the quantum algorithm to be performed, outbound pulse(s) 814 for carrying out the algorithm may be predetermined at design time and/or may need to be determined during runtime. The runtime determination of the pulses may comprise performance of classical calculations and processing in the quantum controller 810 and/or the quantum programing subsystem 802 during runtime of the algorithm (e.g., runtime analysis of inbound pulses 816 received from the quantum processor 820).

During runtime and/or upon completion of a quantum algorithm performed by the quantum controller 810, the quantum controller 810 may output data/results 808 to the quantum programming subsystem 802.

The quantum controller 810 is coupled to the quantum processor 820 via interconnect 812 which may comprise, for example, one or more conductors and/or optical fibers. The quantum controller 810 may comprise a plurality of interconnected, but physically distinct quantum control modules (e.g., each module being a desktop or rack mounted device) such that quantum control systems requiring relatively fewer resources can be realized with relatively fewer quantum control modules and quantum control systems requiring relatively more resources can be realized with relatively more quantum control modules. This enables a scalable quantum-computer-as-a-service architecture which can be hosted the cloud.

The quantum processor 820 comprises K (an integer) quantum elements 822, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element(s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling the outbound quantum control pulses 814 and inbound quantum control pulses 816 between interconnect 812 and the quantum element(s) 822 (e.g., readout resonator(s)). In an example implementation in which the quantum processor comprises readout resonators (or other readout circuitry), K may be equal to the total number of qubits plus the number of readout circuits. That is, if each of Q (an integer) qubits of the quantum processor 820 is associated with a dedicated readout circuit, then K may be equal to 2Q. For ease of description, the remainder of this disclosure will assume such an implementation, but it need not be the case in all implementations. Other elements of the quantum processor 820 may include, for example, flux lines (electronic lines for carrying current), gate electrodes (electrodes for voltage gating), current/voltage lines, amplifiers, classical logic circuits residing on-chip in the quantum processor 820, and/or the like.

The present method and/or system may be realized in hardware, software, or a combination of hardware and software. The present methods and/or systems may be realized in a centralized fashion in at least one computing system, or in a distributed fashion where different elements are spread across several interconnected computing systems. Any kind of computing system or other apparatus adapted for carrying out the methods described herein is suited. A typical implementation may comprise one or more application specific integrated circuit (ASIC), one or more field programmable gate array (FPGA), and/or one or more processor (e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture) and associated supporting circuitry (e.g., storage, DRAM, FLASH, bus interface circuits, etc.). Each discrete ASIC, FPGA, Processor, or other circuit may be referred to as “chip,” and multiple such circuits may be referred to as a “chipset.” Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to perform processes as described in this disclosure. Another implementation may comprise a non-transitory machine-readable (e.g., computer readable) medium (e.g., FLASH drive, optical disk, magnetic storage disk, or the like) having stored thereon one or more lines of code that, when executed by a machine, cause the machine to be configured (e.g., to load software and/or firmware into its circuits) to operate as a system described in this disclosure.

As used herein the terms “circuits” and “circuitry” refer to physical electronic components (i.e. hardware) and any software and/or firmware (“code”) which may configure the hardware, be executed by the hardware, and or otherwise be associated with the hardware. As used herein, for example, a particular processor and memory may comprise a first “circuit” when executing a first one or more lines of code and may comprise a second “circuit” when executing a second one or more lines of code. As used herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As used herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As used herein, the terms “e.g.,” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is “operable” to perform a function whenever the circuitry comprises the necessary hardware and code (if any is necessary) to perform the function, regardless of whether performance of the function is disabled or not enabled (e.g., by a user-configurable setting, factory trim, etc.). As used herein, the term “based on” means “based at least in part on.” For example, “x based on y” means that “x” is based at least in part on “y” (and may also be based on z, for example).

While the present method and/or system has been described with reference to certain implementations, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present method and/or system. In addition, many modifications may be made to adapt a particular situation or implementation to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present method and/or system not be limited to the particular implementations disclosed, but that the present method and/or system will include all implementations falling within the scope of the appended claims.

Claims

1. A system, comprising: a quantum controller comprising a feedback controller, wherein: the feedback controller is operable to measure one or more ancilla qubits in a quantum error correcting code,the feedback controller is operable to generate a quantum feedback operation to control the one or more ancilla qubits,the feedback controller comprises a state machine,the state machine is configured to receive the measurements of the one or more ancilla qubits,the state machine is operable to generate the quantum feedback operation according to the measurements of the one or more ancilla qubits and a state of the state machine,the state machine comprises a logic circuit operable to generate the quantum feedback operation, andthe quantum feedback operation increases a probability that the one or more ancilla qubits will be subsequently measured in a specific state.

2. The system of claim 1, wherein: the state machine comprises a logic circuit operable to provide an error detection event from the measurements of the one or more ancilla qubits.

3. The system of claim 1, wherein: the specific state is a ground state.

4. The system of claim 1, wherein: the quantum feedback operation is determined according to the increased probability that the one or more ancilla qubits will be measured in the specific state.

5. The system of claim 1, wherein: the quantum feedback operation is determined by a state discrimination protocol.

6. The system of claim 5, wherein: the feedback controller is operable to dynamically adjust the discrimination protocol according to previous measurements of the one or more ancilla qubits.

7. The system of claim 1, wherein: the quantum feedback operation is determined by a state discrimination parameter.

8. The system of claim 7, wherein: the state discrimination parameter is a state discrimination threshold.

9. The system of claim 7, wherein: the feedback controller is operable to dynamically adjust the state discrimination parameter according to previous measurements of the one or more ancilla qubits.

10. The system of claim 1, wherein: the feedback controller is operable to adjust, in real-time, a state discrimination according to the one or more ancilla qubits.

11. The system of claim 1, wherein: the quantum feedback operation decreases a probability that the measurements of the one or more ancilla qubits will decay.

12. The system of claim 1, wherein: the quantum feedback operation provides a higher measurement fidelity.

13. The system of claim 1, wherein: the quantum feedback operation provides a shorter measurement time.

14. The system of claim 1, wherein: the feedback controller is operable to determine error detection events in parallel with a generation of non-conditional quantum operations.

15. The system of claim 1, wherein: the generation of the quantum feedback operation is a conditioned operation.

16. The system of claim 15, wherein: the conditioned operation is performed without added latency, thereby reducing an error correction cycle time and errors per cycle.

17. The system of claim 1, wherein: a measurement of the one or more ancilla qubits provide an error detection event, and readout errors in the error correcting code are reduced by maintaining the one or more ancilla qubits in a favorable state.

18. The system of claim 17, wherein: the favorable state is a ground state.

19. A method, comprising: measuring, via a feedback controller of a quantum controller, one or more ancilla qubits in a quantum error correcting code;generating, via the feedback controller, a quantum feedback operation to control the one or more ancilla qubits;receiving, via a state machine of the feedback controller, the measurements of the one or more ancilla qubits;generating, via the state machine, the quantum feedback operation according to the measurements of the one or more ancilla qubits and a state of the state machine; andincreasing a probability, via the quantum feedback operation, that the one or more ancilla qubits will be subsequently measured in a specific state.

20. The method of claim 19, wherein the method comprises: discriminating an error detection event from the measurements of the one or more ancilla qubits.

21. The method of claim 19, wherein: the specific state is a ground state.

22. The method of claim 19, wherein the method comprises: determining the quantum feedback operation according to the increased probability that the one or more ancilla qubits will be measured in the specific state.

23. The method of claim 19, wherein the method comprises: determining the quantum feedback operation according to a state discrimination protocol.

24. The method of claim 23, wherein the method comprises: dynamically adjusting the discrimination protocol according to previous measurements of the one or more ancilla qubits.

25. The method of claim 19, wherein the method comprises: determining the quantum feedback operation according to a state discrimination parameter.

26. The method of claim 25, wherein the method comprises: the state discrimination parameter is a state discrimination threshold.

27. The method of claim 25, wherein the method comprises: dynamically adjusting the state discrimination parameter according to previous measurements of the one or more ancilla qubits.

28. The method of claim 19, wherein the method comprises: adjusting, in real-time, a state discrimination according to the measurement of the one or more ancilla qubits.

29. The method of claim 19, wherein the method comprises: decreasing a probability, via the quantum feedback operation, that the measurement of the one or more ancilla qubits will decay.

30. The method of claim 19, wherein the method comprises: providing a higher measurement fidelity via the quantum feedback operation.

31. The method of claim 19, wherein the method comprises: providing a shorter measurement time via the quantum feedback operation.

32. The method of claim 19, wherein the method comprises: determining error detection events in parallel with generating non-conditional quantum operations.

33. The method of claim 19, wherein: the generation of the quantum feedback operation is a conditioned operation.

34. The method of claim 33, wherein the method comprises: reducing errors per cycle by performing the conditioned operation without added latency.

35. The method of claim 19, wherein the method comprises: discriminating an error detection event according to a measurement of the one or more ancilla qubits; andreducing readout errors in the error correcting code by maintaining the one or more ancilla qubits in a favorable state.

36. The method of claim 35, wherein: the favorable state is a ground state.