Patent Application
20080049716
The present invention is illustrated by way of example and is not limited by the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
Embodiments of a method, apparatus, and system to manage the power of a high-speed serial link by dynamically modifying the link's voltage to operate at the lowest voltage level that maintains compliance with the allowable serial link error rate are disclosed. In the following description, numerous specific details are set forth. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known elements, specifications, and protocols have not been discussed in detail in order to avoid obscuring the present invention.
Processor-memory interconnect 100 provides the central processor 102 and other devices access to the system memory 104. A system memory controller controls access to the system memory 104. In one embodiment, the system memory controller is located within the north bridge 108 of a chipset 106 that is coupled to processor-memory interconnect 100. In another embodiment, a system memory controller is located on the same chip as central processor 102 (not shown). Information, instructions, and other data may be stored in system memory 104 for use by central processor 102 as well as many other potential devices.
A graphics subsystem 110 is coupled to the north bridge 108 of the chipset 106. In one embodiment, the graphics subsystem 110 is connected to the north bridge 108 through a PCI-Express™ bi-directional serial interconnect 112. The PCI-Express™ interconnect is a high-speed serial interconnect for transferring information between the graphics subsystem 110 and the rest of the computer system (including the central processor 102 and the system memory 104). The PCI-Express™ interconnect 112 allows direct data transfers between the graphics subsystem and the chipset 106. In this embodiment, the chipset 106 has a PCI-Express™ host controller incorporated within it to couple to the PCI-Express™ interconnect.
The chipset 106 also includes a south bridge that allows access to one or more I/O interconnects. I/O devices, such as I/O device 118 and device 122, are coupled to the south bridge 114 of the chipset 106 through one or more I/O interconnects. In one embodiment, interconnect 124 is a PCI interconnect and I/O device 122 is a network interface card. In one embodiment, interconnect 120 is a high speed Serial Advanced Technology Attachment (SATA) bi-directional interconnect that includes a SATA cable. In this embodiment, I/O device 118 is a SATA device such as a hard disk, a CD drive, or a DVD drive. In this embodiment, a SATA host controller (not shown) is located within the chipset 106. The SATA host controller 112 allows the SATA I/O device 114 to communicate with the rest of the computer system.
In one embodiment, one or more of the high-speed bi-directional serial interconnects in the system in
As the voltage is lowered to the output drivers, the error rate across the interconnect regarding information sent from the host controller to the SATA I/O device 118 increases. The error rate increases because as the transmitter's supply voltage continues to decline, the transmitter's signal sent across the bus gets weaker. The weaker the signal is, the more likely that SATA packet transmission will result in errors. The SATA specification (SATA Advanced Host Controller Interface 1.0) defines a maximum allowable error rate (e.g. 1 error per 1012 packets transferred or some similar error rate). If the error rate increases beyond the allowable error rate in the specification, the SATA interconnect falls out of compliance.
Thus, for any SATA transmitter, a minimum voltage level exists to be compliant with the specification. Throughout the industry, most devices' and host controllers' output drivers are supplied with more than enough voltage to be easily compliant with the allowable error rate. Most of these compliant host controllers and devices could have the output drivers still remain compliant with a substantially diminished supply voltage in comparison to the default supply voltage.
Thus, in one embodiment, the ERPMC 116 lowers the voltage supplied to the output drivers to a level just above or equal to the minimum voltage required to remain compliant with the allowable error rate. This ERPMC 116 supply voltage lowering process results in a power reduction to the transmission hardware. Therefore, by adjusting the error rate of the sent data up to the maximum allowable error rate, there is power consumption savings for the SATA host controller and, specifically, the output drivers within the SATA host controller's transmitter.
In one embodiment, the link is initialized to begin operation. At this point, the ERPMC 210 sets the voltage level at the voltage control circuit 212 to a standard nominal voltage that is compliant with the specification. The voltage control 212 feeds voltage to the transmitter 202 from a voltage source (Vcc) and can increase or decrease voltage supplied to the transmitter 202. At this point a low voltage calibration routine begins. In one embodiment, the ERPMC 210 and the transmitter 202 calibrate the voltage during normal transmission operation. In another embodiment, the ERPMC 210 and the transmitter 202 calibrate the voltage by sending special test packets across the serial link to the receiver.
In this embodiment, a series of packets will be sent specifically to determine whether any errors occur due to the transmission. The device on the other end of the serial link (not shown in
Next, processing logic sets the error rate threshold (processing block 302). The error rate threshold is the maximum error rate allowable over the link by the link's specification. This threshold will change based on the type of link involved. Then, processing logic starts the voltage calibration routine on the link (processing block 304). In one embodiment, the calibration routine may be part of the normal operation of the link, thus calibration takes place in unison with data transfers. In another embodiment, the routine may be a special calibration routine that does not coexist with data transfers over the link. In this embodiment, the calibration routine initially will run as part of the computer system's boot up procedures, though, after the initial routine is run, subsequent recalibration routines would temporarily suspend normal link data transfer operations while voltage is recalibrated.
In one embodiment, the voltage calibration routine begins with the transmitter with modifiable voltage (transmitter 202 in
If the error rate threshold has not been exceeded, then processing logic steps down the voltage sent to the transmitter's output drivers (processing block 308) and then the process returns to block 306 where processing logic again determines whether the error rate threshold has been exceeded. If the error rate threshold has been exceeded, it indicates that the voltage level is too low and, thus, creating too many transmission errors. In this case, processing logic steps up the voltage sent to the transmitter's output drivers (processing logic 310).
Then, again, processing logic determines whether the error rate threshold has been exceeded (processing block 306). If the error rate threshold is still exceeded, then the process returns to block 310 to step up the voltage again. Otherwise, if the error rate threshold is no longer exceeded, then processing logic waits for a recalibration interval period of time (processing block 314) and then the process returns to block 304 for another voltage calibration. In one embodiment, the recalibration interval is set in the BIOS at system start up. In another embodiment, the operating system running on the computer system that the link is located within has the capability to modify the recalibration interval. In this embodiment, the recalibration interval is modified by the operating system based on the environment where the computer system is located.
Environmental determination may be made by any number of different methodologies. For example, if the computer system is a mobile computer, the recalibration interval can be shortened when the system is plugged in because there may be more electrical noise and interference changes in an office environment than a non-office environment. In another example, the computer system may have a motion detector, which can determine whether the computer itself is in motion. If the computer is in motion the recalibration interval will shorten since the change in electrical interference may become more pronounced than in a stationary environment.
In another embodiment, there is no recalibration interval. In this embodiment, the voltage calibration begins immediately after the voltage level was set in the previous calibration routine. This embodiment works in conjunction with a calibration routine that runs during normal link operations.
Thus, embodiments of a method, apparatus, and system to enable native SATA device presence detection and hot-plugging in SATA AHCI low power mode are disclosed. These embodiments have been described with reference to specific exemplary embodiments thereof. It will be evident to persons having the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the embodiments described herein. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
