Patent Application
20060023387
The present invention relates to chip design. More particularly, but not exclusively, the present invention relates to chip design that provides ESD protection and is suitable for use in high speed data communication systems.
In recent years, much research has focused on improving high speed data communication systems especially in wireline data communication systems. The data rate can reach several Gbit/s. Several products offer around 3 Gbit/s data rate. There are several challenges that have to be met in order to increase the data rate to several Gbit/s. One of the challenges is the Electrostatic Discharge (ESD) protection devices that are placed at the driver and receiver to protect the chip from ESD events that can be devastating to the chip interior circuitry. The ESD devices, on the other hand, act as low pass filters that filter out the driver transmitted signal above a few GHz. It is very impractical to design a chip with no ESD protection because it becomes very vulnerable to ESD events resulting in lower yield and field failures.
The mechanism of ESD protection is to provide an alternate low impedance path for the current to be discharged to the substrate or ground of the chip instead of entering the internal circuitry and damaging sensitive active and passive devices.
The ESD event can be the result of a human hand touching the chip or even getting close to it. The human body can be charged up to several kilo-Volts. One source of the charge accumulation is the person walking on carpet. If the human hand touches a chip already charged at a ground potential, a potential difference will result in discharge of the charge on the human body to the chip. The electrical model for this phenomenon is called the Human Body Model (HBM). This ESD event can be damaging to the chip.
Another source of ESD event is when the chip becomes charged, and then discharges after one of its pins is connected to another potential point like ground. If it is not well-protected, the ESD event of this type is faster and more critical to the chip than HBM phenomenon. The electrical model for this event is known as the Charge Device Model (CDM).
In the normal circuit operating mode, the ESD device is off and virtually no current passes through it. The input signal bypasses the ESD device and is directed to the internal circuitry which is usually the gate of a MOSFET transistor or the base of a bipolar transistor. In principle, the ESD device should not affect the normal operation of the chip internal circuit. In reality, the ESD device does affect the electrical properties of the signal path, and careful consideration of the tradeoffs should take place to ensure the optimal performance of the chip.
In the case of an ESD event, the ESD device is activated through the voltage breakdown characteristics of the device. The ESD device bypasses the internal circuitry, and provides an alternate low impedance path for the large current to be dissipated in it. The ESD device is designed to be large enough to be capable of passing current on the order of several Amperes. However, using a large device comes at the cost of increasing parasitic capacitances at the node where the ESD protection is introduced.
If the internal circuitry of the chip does not have ESD protection devices, then its vulnerability to ESD damage is high. If an ESD current affects the chip and passes through the internal circuitry, a damage can occur to it in the form of dielectric breakdown of gate oxide. In a typical submicron CMOS process, the gate oxide material used is usually Silicon Dixoide, SiO2, which has a dielectric strength of around 8-10 MV/cm. The thickness of SiO2 is on the order of 40-50 Angstroms in a typical CMOS process where the minimum draw feature length is 0.18 μm. Therefore, if a voltage in excess of 3V is applied to the gate, it can be damaged. As a result, a voltage applied to the transistor gate of this magnitude should be prevented.
Another form of ESD damage is due to thermal damage of SiO2 and metal interconnect. This happens because of the poor thermal conductivity of SiO2. The I2R heat is generated in the path that the current takes such as a metal interconnect. Since the ESD event elapses for a short time with large current, the heat is not dissipated as quickly as needed. The temperature of the SiO2 is raised locally to a degree that the silicon is damaged and the metal interconnect is melted. A short circuit or an open circuit can occur and in many cases the damage can be seen under the microscope as a localized burn or melting of the metal interconnect. In addition, high leakage current in the ESD device can be observed after breakdown.
The ESD protection structure should be able to meet several goals, some of which are challenging. In many cases, there is a compromise between the high protection level, circuit operation frequency, size, and silicon area in order the achieve the best ESD protection circuit for a specific chip or design. The problem of ESD protection for RF and very high speed circuits is a particularly challenging task. The challenge is in designing an ESD protection structure that is capable of at least Class 2 (2 kV-4 kV) level of protection. At the same time, it does not impede signals with high frequency content in the GHz range, and should turn on faster than the internal circuitry in order to achieve protection.
What is needed for chips is an ESD device that allows for high speed data communication while providing adequate ESD protection. Therefore, it is a primary, object, feature, or advantage of the present invention to improve upon the state of the art by providing an ESD device for high speed data communication systems with improved bandwidth.
It is a further object, feature, or advantage of the present invention to provide a chip that is capable of sending and receiving data at a rate of several Gbits/s without being impeded by parasitic capacitances.
Another object, feature, or advantage of the present invention is to provide an ESD structure capable of protecting internal circuitry of a chip from high ESD transients.
A still further, object, feature, or advantage of the present invention is to provide a chip with internal circuitry isolated from the outside world.
Another object, feature, or advantage of the present invention is to provide a low capacitance ESD structure which is minimally disruptive of differential signals.
A further object, feature, or advantage of the present invention is to provide an ESD structure for a chip that is reliable and can withstand repeated ESD events effectively.
Another object, feature, or advantage of the present invention is to provide an ESD structure which is reasonably simple to design, layout, and fabricate.
One or more of these and/or other objects, features, or advantages of the present invention will become apparent from the specification that follows.
The present invention provides an ESD device that places a transformer at the transmitter and receiver as an interface and as an insulator between the chip internal circuitry and the PCB interconnect. The transformer differentiates the current signal that enters its primary and then generates an induced voltage at the secondary ports of the transformer. To divert the ESD event from affecting the internal circuitry, spark gap structures are placed close to the chip pads and have a pointing shape that are close to the interconnection so that a spark can be formed between the interconnect and the spark gap. In this way, a conductive path is generated when a large voltage affects the chip. This path consists of the interconnection that reaches the chip pads from outside, the chip pads, the spark, and the connection between the spark gaps and the substrate. In addition, a set of diodes is connected to the middle point between the transformers on each of the primary and the secondary sides. In the case of an ESD event, the ESD current can pass through the low impedance path provided by the diode sets.
The present invention provides for the complete isolation between the on-chip circuitry and off chip circuitry though using a chip transformer. The ESD device can be used in RF circuits in many applications such as low noise and wireless circuit design. It can, for example, be used in high speed serializer and deserializer circuits.
The present invention provides for a high speed serial link with improved ESD protection. The architecture of the driver is to include on chip RF transformers at the driver. The transformers isolate the inner circuitry from outside the chip. The transformers can be designed to have a lower cutoff frequency that is higher than the bandwidth of the ESD signal.
According to one aspect of the present invention, an integrated circuit includes first and second monolithic transformers. There is an electrostatic discharge (ESD) device connected between the first and second monolithic transformers. First and second on-chip spark gaps for forming low impedance grounds during ESD events are electrically connected to the first and second monolithic transformer, respectively. The first on-chip spark gap is electrically connected to a secondary coil of the first monolithic transformer and the second on-chip spark gap is electrically connected to a secondary coil of the second monolithic transformer. The ESD device may include a set of diodes that are connected to the middle point between the two transformers at the primary, and another set of diodes connected to the middle point between the transformers at the secondary side. Preferably, the integrated circuit is adapted to be attached to a printed circuit board (PCB) using a Chip On Board attachment method. Each of the monolithic transformers preferably includes a primary winding and a secondary winding, and a shield between the primary winding and the secondary winding, and wherein the shield is grounded. The shield need not be continuous, but can be segmented into short segments to prevent induced currents. The transformers may be planar transformers, torroidal transformers, or of other geometries.
According to another aspect of the present invention, a system for high speed data communication with improved bandwidth is provided. The system includes a substrate, a driver chip attached to the substrate, a receiver chip attached to the substrate. Each of the driver chip and the receiver chip include first and second monolithic transformers. There is an ESD device connected between the first and second monolithic transformers. In addition, first and second on-chip spark gaps are provided for forming low impedance grounds during ESD events. The first on-chip spark gaps are electrically connected to the first monolithic transformer and the second on-chip spark gaps are electrically connected to the second monolithic transformer. Each of the first and second monolithic transformers may comprise a primary winding, a secondary winding, and a shield between the primary winding and the secondary winding. The first and second monolithic transformers may be planar transformers, torroidal transformers, or transformers of other geometries. The shield need not be continuous between the primary and secondary winding and is preferably segmented into short segments to prevent induced currents.
The middle point between the transformers (14, 16) is balanced and can be considered to be an AC ground. This is due to the fact that the signal transmitted is differential. The transformers (14, 16) are connected in series. The two ports of the primary are connected to the internal circuitry and the two ports of the secondary are connected to the bonding pads. The transformer layout can be planar interleaved, planar concentric, a toroidal solenoid or others.
In order to improve the bandwidth of the transformer used, the present invention provides for shielding primary and secondary windings of each transformer. This shielding allows for the coupling resonance frequency, fc, to be increased. The shielding can be a thin metal layer between the primary and secondary. Preferably, the shield is not continuous between the primary and secondary, but rather segmented into short segments to prevent induced currents in it. Preferably the shield converts the coupling capacitance to self-capacitance. As the self-capacitance increases, the coupling capacitance decreases and the coupling bandwidth increases. Thus, the shield between the primary and secondary windings of the transformer may serve as a shield for a surge in voltage that is imposed on the primary of the transformer. The shield can be considered as a secondary protection measure against an ESD event.
On the secondary side, in the middle point between the transformers, an ESD device 18 is provided. The use of two diodes in the configuration shown in
The spark gaps (20, 22) are placed close to the bonding pads on both sides of the secondary. The spark gaps (20,22) can be configured in any number of ways. In one embodiment, the spark gaps have a saw tooth shape.
In a normal mode of operation, the transformers, ESD structure, and spark gaps act as part of the driver/receiver circuit in a wireline data communications serializer/deserializer scheme. The signals enter the transformer primary in differential current mode fashion. The four port transformer acts as an isolator.
The ESD structure can be large and yet fast enough to withstand high current and fast triggering, providing a high level of protection. The ESD protection structure can be included in a wireline data driver or receiver capable of data rates, of several Gbit/s or more as shown in
According to the present invention, it is preferred that the chip-on-board (COB), flip-chip, or other low low-inductance packaging method be used. The benefit of this type of attachment method is that it eliminates lead inductance and down bondwire. It also results in less parasitic capacitances that impede the signal path.
It should be apparent that the present invention contemplates numerous variations as may be appropriate under particular design criteria and design considerations, or to particular applications or environments. These and other variations, options, and alternatives are all within the spirit and scope of the invention which is to be limited only by the attached claims.
This application claims priority to U.S. Provisional Patent Application No. 60/588,286, filed Jul. 15, 2004, herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60588286 | Jul 2004 | US |
