Patent Application
20070146564
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit for a thin film transistor liquid crystal display (TFT-LCD).
A TFT-LCD has the advantages of portability, low power consumption, and low radiation, and has been widely used in various portable information products such as notebooks, personal digital assistants (PDAs), video cameras and the like. Furthermore, the TFT-LCD is considered by many to have the potential to completely replace CRT (cathode ray tube) monitors and televisions.
During a typical TFT-LCD fabricating process, static electricity may be generated on the TFT-LCD. If a large amount of electrical charge builds up at any one location on the TFT-LCD, the built up electrical charge is liable to discharge and thereby damage or destroy internal components of the TFT-LCD such as thin film transistors. To avoid the damaging effects of static electricity buildup and discharge during and after forming of the TFT-LCD array, a plurality of ESD protection circuits are employed in a typical TFT-LCD.
Generally, operation of the ESD protection circuit 240 is as follows. When positive charge generated by an ESD flows from the first terminal 245, the first transistor 241 is turned on and the positive charge on the first terminal 245 flows to the common electrode 230 via the second terminal 246. When negative charge generated by an ESD flows from the first terminal 245, the second transistor 242 is turned on and the negative charge on the first terminal 245 flows to the common electrode 230 via the second terminal 246. Thus, the ESD protection circuit 240 can prevent static electricity generated in the process of fabricating the gate lines 210 or the data line 220 of TFT-LCD 200 from destroying other internal circuits (not shown) of the TFT LCD 200.
On the other hand, if built-up electrical charge does not flow from the first terminal 245, then the first and second transistors 241, 242 are maintained in an off state. In this state, the ESD protection circuit 240 blocks the electrical path between the first terminal 245 and the second terminal 246 to insulate the first terminal 245 and the second terminal 246 from each other.
When the electrical charge generated by an ESD flows from the first terminal 245, only one current path can be formed between the first terminal 245 and the second terminal 246 at any one time. That is, the current path is either through the first transistor 241 or the second transistor 242. However, the current of electrical charge may be so large that it destroys one of the transistors 241, 242. If one of the transistors 241, 242 is destroyed by the discharge current, the corresponding current path between the first terminal 245 and the second terminal 246 cannot be formed. Thus, a subsequent discharge of static electricity generated in the process of fabricating the gate line 210 or the data line 220 may destroy other internal circuits of the TFT-LCD 200.
Generally, operation of the ESD protection circuit 260 is as follows. When positive charge generated by an ESD flows from the first terminal 265, the voltage of the first terminal 265 is much higher than the voltage of the node 267. Thus the first transistor 261 is turned on, and the positive charge on the first terminal 265 flows through the first transistor 261 to charge the gate electrode ‘g’ of the second transistor 262. Then the second transistor 262 is turned on and the positive charge flows to the common electrode 230 via the second terminal 266. When negative charge generated by an ESD flows from the first terminal 265, the voltage of the first terminal 265 is much lower than the voltage of the node 268. Thus the third transistor 263 is turned on, and the negative charge on the first terminal 265 flows through the first transistor 263 to charge the node 268. Then the voltage of the second terminal 266 is much higher than the voltage of the node 268. Thus the fourth transistor 264 is turned on, and the negative charge flows to the common electrode 230 via the second terminal 266.
On the other hand, if built-up electrical charge does not flow from the first terminal 265, then the first, second, third and fourth transistors 261, 262, 263, 264 are maintained in an off state. In this state, the ESD protection circuit 260 blocks the electrical path between the first terminal 265 and the second terminal 266 to insulate the first terminal 265 and the second terminal 266 from each other.
However, the ESD protection circuit 260 is subject to the same kind of problem as that described above in relation to the ESD protection circuit 240. That is, a large current of electrical charge may destroy one of the transistors 261, 262, 263, 264. Thus, a subsequent discharge of static electricity generated in the process of fabricating the gate line 210 or the data line 220 may destroy other internal circuits of the TFT-LCD 200.
It is desired to provide an ESD protection circuit which overcomes the above-described deficiencies.
An ESD protection circuit includes a first transistor including a source electrode, a drain electrode and a gate electrode; a second transistor including a source electrode, a drain electrode and a gate electrode; a third transistor including a source electrode, a drain electrode and a gate electrode; and a fourth transistor including a source electrode, a drain electrode and a gate electrode. The gate electrode of the first transistor, the gate electrode of the second transistor, the drain electrode of the third transistor, and the drain electrode of the fourth transistor are connected to each other. The source electrode of the first transistor, the source electrode of the second transistor, and the source and gate electrodes of the third transistor are connected to each other. The drain electrode of the first transistor, the drain electrode of the second transistor, and the source and gate electrodes of the fourth transistor are connected to each other.
A driving circuit of a TFT-LCD includes a plurality of gate lines that are parallel to each other and that each extend along a first direction; a plurality of data lines that are parallel to each other and that each extend along a second direction orthogonal to the first direction; a common electrode; and a plurality of ESD protection circuits, each ESD protection circuits including: a first terminal which is connected to the gate line or the data line; a second terminal which is connected to the common electrode; a first transistor including a source electrode, a drain electrode and a gate electrode; a second transistor including a source electrode, a drain electrode and a gate electrode; a third transistor including a source electrode, a drain electrode and a gate electrode; and a fourth transistor including a source electrode, a drain electrode and a gate electrode. The gate electrode of the first transistor, the gate electrode of the second transistor, the drain electrode of the third transistor, and the drain electrode of the fourth transistor are connected to each other. The source electrode of the first transistor, the source electrode of the second transistor, and the source and gate electrodes of the third transistor are connected to the first terminal. The drain electrode of the first transistor, the drain electrode of the second transistor, and the source and gate electrodes of the fourth transistor are connected to the second terminal.
Advantages and novel features of the above-described circuits will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
The gate electrode ‘g’ of the first transistor 141 is connected to the gate electrode ‘g’ of the second transistor 142 to define a crunode 167. The source electrode ‘s’ of the first transistor 141 and the source electrode ‘s’ of the second transistor 142 are connected together to define the first terminal 145. The drain electrode ‘d’ of the first transistor 141 and drain electrode ‘d’ of the second transistor 142 are connected together to define the second terminal 146. The first and second transistors 141, 142 function as electrostatic discharge elements.
The drain electrode ‘d’ of the third transistor 143 and the drain electrode ‘d’ of fourth transistor 144 are both connected to the crunode 167. The source electrode ‘s’ and the gate electrode ‘g’ of the third transistor 143 are connected to the first terminal 145. The source electrode ‘s’ and the gate electrode ‘g’ of the fourth transistor 144 are connected to the second terminal 146. The third and fourth transistors 143, 144 function as control elements. The first transistor 141, the second transistor 142, the third transistor 143, and the fourth transistor 144 may be positive metal-oxide semiconductor (PMOS) transistors, negative metal-oxide semiconductor (NMOS) transistors, or thin film transistors. The first terminal 145 is connected to one of the gate lines 110 or one of the data lines 120. The second terminal 146 is connected to the common electrode 130.
Generally, operation of the ESD protection circuit 140 is as follows. When electrical charge generated by an ESD flows from the first terminal 145, the third transistor 143 is turned on. The electrical charge at the first terminal 145 flows through the third transistor 143 to charge the crunode 167. Because the gate electrodes ‘g’ of the first and second transistors 141, 142 are connected to the crunode 167, the first and second transistors 141, 142 are turned on, and the electrical charge flows to the common electrode 130 via the second terminal 146.
Unlike with the conventional ESD protection circuits 240, 260 described above, in the ESD protection circuit 140, when electrical charge generated by an ESD flows from the first terminal 145, the ESD protection circuit 140 can form two current paths between the first terminal 145 and the second terminal 146. That is, the current paths are through the first transistor 141 and the second transistor 142. Thus a maximum current of electrical charge that the ESD protection circuit 140 can tolerate without sustaining damage is larger. Furthermore, even if a current of electrical charge damages or destroys one of the transistors 141, 142, a current path can still be formed between the first terminal 145 and the second terminal 146 via the other of the transistors 141, 142. Thus, the ESD protection circuit 140 can prevent static electricity generated in the process of fabricating the gate lines 110 or the data lines 120 from destroying other internal circuits (not shown) of the TFT-LCD 100.
In alternative applications, the ESD protection circuit 140 can be used in other electronic devices such as at an input pad of an integrated circuit.
It is to be understood, however, that even though numerous characteristics and advantages of preferred embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
