Patent Application
20130285196
Disclosed embodiments relate to electrostatic discharge (ESD) circuits for protecting multiple pins of integrated circuits.
An integrated circuit (IC) may be subject to damaging ESD events in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional IC ESD protection schemes, clamp circuits are often used to shunt ESD current to ground during voltage peaks to protect internal circuitry on the IC from ESD-induced damage.
Where multiple ports need to be protected, for instance multiple pins of an IC, a local clamp approach using dedicated separate ESD structures, each with an anode and a cathode, is generally used to protect each pin. What is needed is an ESD protection circuit architecture that requires significantly less space.
Disclosed embodiments include electrostatic discharge (ESD) protection circuits comprising a stacked plurality of ESD protection cells in a semiconductor surface each having a surrounding isolation structure. The plurality of ESD protection cells are connected in series by an interconnect, and include a first ESD protection cell in series with at least a second ESD protection cell. The ESD protection circuit includes a plurality of protection pins (by connections to electrode taps including electrode taps within the stack of ESD protection cells) including a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating, and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating.
The plurality of electrode taps include overlapping discharge paths which share some of same ESD protection cells for various pin applications. Disclosed embodiments thus mitigate the problem of large chip area needed by conventional high voltage ESD protection arrangements for protecting ICs. In one particular embodiment, the ESD protection circuit is formed on a semiconductor on insulator (SOI) substrate which permits dielectric isolation to be used as the isolation between the ESD protection cells which allows a closer cell spacing as compared to junction isolated cells.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
ESD protection circuit 100 comprises a substrate 105 having a semiconductor surface 106, where the plurality of ESD protection cells 1101-1104 are formed in the semiconductor surface 106 each having a surrounding isolation structure 108. Although the ESD protection cells 1101-1104 are shown with a symbol indicating a reversed biased diode, disclosed ESD protection cells can comprise any type of protection device, including unidirectional devices or bidirectional devices. Example protection devices include those based on silicon controlled rectifiers (SCRs), snapback devices based on npn or pnp bipolar transistors, statically or dynamically triggered, with any type of triggering enhancement circuit, such as capacitors, resistors, MOS field effect transistors (MOSFETs), or zener diodes. Although disclosed ESD protection cells are generally described herein as being unidirectional devices, two disclosed ESD protection cells may be configured in parallel to provide bidirectional protection if desired. The isolation structures 108 can comprise junction isolation (see
The plurality of ESD protection cells 1101-1104 are connected in series by an interconnect 115, typically a metal interconnect, which couples vias that connect to contacts on the semiconductor surface 106 within the ESD protection cells 1101-1104 to bond pads for stand-alone embodiments. ESD protection cells 1101 may be referred to herein as the first ESD protection cell and ESD protection cell 1102 as the second ESD protection cell.
ESD protection circuit 100 includes a plurality of protection pins 122, 123 and 124 and a ground pin 121 each shown as bond pads which are connected by connector 177 to respective nodes of the stacked ESD protection circuit 100 including protection pin 122 to internal node 132, and protection pin 123 to internal node 133. Protection pin 124 is connected to node 134 which is across all of the ESD protection cells 1101-1104. There is no pin shown connected to internal node 131.
To simplify the description of ESD protection circuit 100 and ESD protection circuits 300 and 350 described below relative to
ESD protection circuit 100 thus provides protection pins 122, 123 and 124 which each provide a plurality of different voltage ratings (20V, 100V and 200V, respectively), with the higher voltage rated pins including the same ESD protection cells as lower voltage rated pins, along with additional ESD protection cells not utilized by the lower voltage rated pins. The respective protection pins thus utilize sharing of some of the discharge paths.
As noted above, the isolation structures 108 for disclosed ESD protection circuits can comprise junction isolation and use a bulk substrate (e.g., silicon substrate), or epitaxial substrate (e.g., p− epi on a p+ substrate). For junction isolated embodiments, each ESD protection cell has its own surrounding junction isolation and the size of the isolation region depends on the position of the ESD protection cell in the stack. For example, assuming 10V ESD cells and the stacking of 5 identical ESD cells, the core of every cell can be the same, and every cell receive a different isolation region size. For example, the cell between the 0V (ground) and 10V rails may not need an isolation structure, the cell between 10V and 20V rails can be given a 20V tolerant isolation structure, and the cell between 20V and 30V rails can be given a 30V tolerant isolation structure, and so on. In junction isolated embodiments the distance between adjacent stacked ESD cells cannot be a fixed minimum distance, but instead depends on the isolation voltage rating.
In contrast, in dielectric isolated embodiments enabled by SOI substrates, all ESD protection cells are electrically isolated from one another by a dielectric, so that the distance between adjacent stacked ESD cells can be constant, and be defined by lithography and etch capabilities. Accordingly, a significant advantage of dielectric isolation is there are no spacing limitations relating to stacking of disclosed ESD protection cells, resulting in a minimized chip area for disclosed ESD protection circuits.
Whether junction isolated or dielectric isolated, disclosed ESD protection circuits provide an area saving by sharing ESD protection cells of the same ESD protection stack among different pins. Since disclosed ESD protection circuits are formed from a plurality of ESD protection cells, the shape of disclosed ESD protection circuits can easily be adapted to fit into a given space even for irregularly shaped spaces, helping the circuit designer to minimize the area of the overall layout.
For example,
Bus 4 provides the physical serial connection to all the ESD protection cells (2601 to 2609). Bus 1 provides physical connection to ESD protection cells 2601, 2606 and 2607, thereby providing 90V, 40V or 30V of protection, depending on which one the above three cells is connected to Bus 1. Likewise, Bus 2 provides physical connection to ESD protection cells 2602, 2605 and 2608, thereby providing 20V, 50V or 80V of protection, depending on which one of the above three cells is connected to Bus 2. In a similar fashion, Bus 3 provides physical connection to ESD protection cells 2603, 2604 and 2609, thereby providing 10V, 60V or 70V of protection, depending on which one of the above three cells is connected to Bus 3.
IC 400 also includes a number of external terminals, by way of which functional circuitry 424 carries out its function. A few of those external terminals are illustrated in
IC 400 includes an instance of a disclosed ESD protection circuit 100 at its lower left corner. Protection pin 122 is connected to the I/O pin of functional circuitry 424 to protect I/O circuitry of functional circuit 424, protection pin 123 is connected to VDD to protect circuitry on functional circuit 424 vulnerable to an ESD event applied to VDD, and protection pin 124 is connected to OUT to protect output stage circuitry from an ESD event applied to OUT. Although not shown, another protection pin may be connected between VDD and VSS.
Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this Disclosure.
