ESD PROTECTION CIRCUIT WITH ISOLATED DIODE ELEMENT AND METHOD THEREOF

Abstract

An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to −Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:

FIG. 1 is a schematic block diagram view of a standard ESD circuit known in the art;

FIG. 2 is a schematic block diagram view of an ESD protection circuit with an isolated diode element according to an embodiment of the present disclosure;

FIGS. 3-6 are cross-sectional views of a portion of the ESD protection circuit with an isolated diode element during a manufacture thereof according to an embodiment of the present disclosure;

FIG. 7 is a top-down view of a portion of the ESD protection circuit with an isolated diode element according to one embodiment of the present disclosure;

FIG. 8 is an image view of a portion of the ESD protection circuit with an isolated diode element according to one embodiment of the present disclosure;

FIG. 9 is a cross-sectional view of an ESD protection circuit with an isolated diode element according to one embodiment of the present disclosure;

FIG. 10 is a cross-sectional view of an ESD protection circuit with an isolated diode element according to another embodiment of the present disclosure; and

FIG. 11 is a cross-sectional view of an ESD protection circuit with an isolated diode element according to yet another embodiment of the present disclosure.

Claims

1. An ESD protection circuit comprising: an ESD device, wherein the ESD device includes a drain-source junction isolated ESD transistor; andan isolation diode element coupled in series with the ESD device and configured for providing ESD protection to a transistor device needing ESD protection, wherein (i) responsive to −Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element, and (ii) responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition, further wherein the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

2. The circuit of claim 1, wherein the isolation diode element comprises a diode element isolated from a semiconductor body of the protected transistor device.

3. The circuit of claim 2, further including an isolation region, wherein the isolation region provides isolation between the isolation diode element and the semiconductor body.

4. The circuit of claim 3, wherein the isolation region comprises a portion of semiconductor material bounded by (i) trench isolation and (ii) an insulator layer of an SOI substrate, further wherein the isolation diode element is formed within the portion of semiconductor material.

5. The circuit of claim 1, wherein the isolation diode element comprises interdigitated n-type and p-type regions.

6. The circuit of claim 1, wherein the isolation diode element includes a semiconductor material selected from the group consisting of single crystalline silicon, poly crystalline silicon, germanium, silicon-germanium, gallium-arsenide, and gallium-nitride.

7. The circuit of claim 1, wherein the isolation diode element comprises one selected from the group consisting of (i) p-type regions surrounded by n-type regions, (ii) n-type regions surrounded by p-type regions, and (iii) uniform pairs of n-type and p-type regions.

8. The circuit of claim 1, further wherein the series coupled isolation diode element and ESD device do not conduct in response to an input to the protected device gate being driven into an opposite polarity with respect to a polarity of the semiconductor body of the protected transistor device.

9. The circuit of claim 1, further wherein the semiconductor body comprises one selected from the group consisting of a silicon substrate, germanium substrate, silicon-germanium substrate, a III-V semiconductor material substrate, a bulk semiconductor substrate, and a semiconductor-on-insulator substrate.

10. The circuit of claim 1, wherein the isolation diode element comprises a resistive element portion and a diode element portion, wherein an amount of resistance of the resistive element portion establishes a given breakdown condition of the isolated diode element.

11. The circuit of claim 1, wherein the series coupled combination of the isolation diode element and ESD device have a common source with the protected transistor device.

12. The circuit of claim 1, wherein the isolation diode element comprises an isolated poly silicon diode element.

13. The circuit of claim 1, wherein the isolated diode element is located proximate the protected transistor device.

14. The circuit of claim 1, wherein the protected device comprises an RF LDMOSFET.

15. The circuit of claim 1, wherein the ESD device comprises a grounded-gate n-type Laterally Diffused Metal Oxide Semiconductor ESD circuit.

16. A method of making an ESD protection circuit comprising: forming an ESD device, the ESD device including a drain-source junction isolated ESD transistor; andforming an isolation diode element coupled in series with the ESD device, wherein the isolation diode element is configured for providing ESD protection to a transistor device needing ESD protection, wherein (i) responsive to −Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element, and (ii) responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition, further wherein the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

17. The method of claim 16, wherein forming the isolation diode element comprises forming a diode element isolated from a semiconductor body of the protected transistor device.

18. The method of claim 17, further comprising: forming an isolation region prior to forming the isolation diode element, wherein the isolation region provides isolation between the isolation diode element and the semiconductor body.

19. The method of claim 18, wherein forming the isolation region further comprises bounding a portion of semiconductor material by (i) trench isolation and (ii) an insulator layer of an SOI substrate, wherein forming the isolation diode element further includes forming the isolation diode element within the portion of semiconductor material.

20. The method of claim 16, wherein forming the isolation diode element comprises forming interdigitated n-type and p-type regions.