This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-264507, filed Dec. 2, 2011; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate to a semiconductor device, for example, an ESD protection circuit, which can protect a power supply circuit from electrostatic discharge (Electro Static Discharge) (hereafter referred to as ESD).
A power supply voltage supplied to a semiconductor device varies and can be 3.3V/2.5V/1.8V. As a result, a thick film transistor (called thick film) which operates with 3.3V/2.5V, an inside film transistor which operates with 1.8V, and a thin film transistor (called a thin film transistor) which operates with 0.9V to 1.2V, are used. For miniaturization, e.g., for semiconductor devices having 65 nm features sizes, it is not favorable to use three types of transistors because they increase the cost of manufacturing.
Instead, a tolerant type circuit that operates with voltages not more than 1.8V, but can bear the power supply voltage of 3.3V/2.5V has been developed without incorporating a transistor which operates with 3.3V/2.5V. Such tolerant type circuit needs to similarly include an ESD protection circuit that is used for ESD protection of a power supply.
In general, one embodiment will be explained with reference to the figures.
In one embodiment, a transistor that provides voltage resistance up to a level that is lower than the power supply voltage is implemented in an ESD protection circuit for a power supply circuit, so as to reduce the number of circuit elements in the ESD circuit.
The ESD protection circuit according to the embodiment includes a first power supply node to which a first power supply voltage is supplied, first and the second transistors of a first conduction type that are connected in series between the first power supply node and a second power supply node to which a second power supply voltage lower than the first power supply voltage is supplied, a third transistor of the first conduction type, and fourth and fifth transistors of a second conduction type. The voltage resistance levels of the transistors are each lower than the first power supply voltage.
One end of a current path through the third transistor is connected to a gate of the second transistor, and the other end of the current path is connected to the second power supply node. During normal operation, a third voltage higher than the second power supply voltage is supplied to a gate of the third transistor.
One end of a current path through the fourth transistor is connected to the first power supply node, and the other end of the current path is connected to a gate of the first transistor. During ESD operation, the fourth transistor causes the first transistor to be in an ON state. During normal operation, the fourth transistor is in an OFF state.
During ESD operation, one end of a damping time constant circuit of the ESD protection circuit causes the fifth transistor to be in an ON state, so that a current path is established between one end to the other end of the fifth transistor which is connected to the gate of the second transistor. The fifth transistor has a third voltage supplied to its gate, changes into an OFF state during normal operation, and causes the second transistor to change into an ON state during ESD operation. The fifth transistor is connected between the other end of the current path of the fourth transistor and the gate of the first transistor, and provides a resistance which supplies a bias voltage to the gate of the first transistor during normal operation.
The semiconductor device of this embodiment is an ESD protection circuit configured with a transistor that operates with voltages not more than 1.8V but is supplied with a power supply voltage that is beyond the voltage resistance level of the transistor, for example, 3.3V, and protects the power supply of this circuit from ESD.
An ESD protection circuit 10 that is shown in
The ESD clamp circuit 11 includes two n channel MOS transistor (hereafter called NMOS transistor) MN1 and MN2. The NMOS transistors MN1 and MN2 is connected in series between a power supply line 14 to which a power supply voltage VDDH is applied and a ground line 15 which is at the ground potential GND. The substrate of the NMOS transistors MN1 and MN2 is also connected to the ground line 15.
The gate bias circuit 12 includes two p channel MOS transistors (hereafter called PMOS transistor) MP1 and MP2, an NMOS transistor MN3, and a resistor R2. The PMOS transistors MP1, MP2, and the NMOS transistor MN3 are connected in series between the power supply line 14 and the ground line 15. In addition, the substrate of the NMOS transistor MN3 is connected to the ground line 15, and the substrate of PMOS transistors MP1 and MP2 is connected to the power supply line 14.
A connection node between the PMOS transistors MP1 and MP2 is connected to the gate of the NMOS transistor MN1, and a connection node between the PMOS transistor MP2 and the NMOS transistor MN3 is connected to the gate of the NMOS transistor NM2. Moreover, the gates of the PMOS transistor MP2 and the NMOS transistor MN3 are each connected to the power supply terminal VL. A mid-level voltage VDDL, for example, 1.8V, is applied to the power supply terminal VL from an external source at the time of normal operation of the semiconductor device. The mid-level voltage VDDL is not limited to 1.8V, and can be any voltage that is higher than the ground potential, is lower than the power supply voltage VDDH, and can turn ON the NMOS transistor MN3. The resistor R2 is connected between the power supply terminal VL and the connection node between the PMOS transistors MP1 and MP2.
Continuing, the damping time constant circuit 13 includes a resistor R1 and capacitor CP1 that includes a PMOS transistor, in one embodiment. The resistor R1 and the capacitor CP1 are connected in series between the power supply line 14 and the power supply terminal VL. The connection node between the resistor R1 and capacitor CP1 is connected to the gate of the PMOS transistor MP1. In addition, the cathode of the diode D1 is connected to the power supply line 14, and the anode is connected to the ground line 15.
The voltage resistance level of the NMOS transistors MN1, MN2, MN3, and the PMOS transistors MP1, MP2 is set as 1.8V, and 3.3V is applied to the power supply line 14 as the power supply voltage VDDH at the time of the normal operation of the semiconductor device.
The operation of the semiconductor device is explained with reference to
Next, the operation during ESD is explained.
Prior to the occurrence of ESD, which is shown in
Moreover, in the state where the power supply line 14 and the power supply terminal VL are 0V, when ESD occurs such that a negative voltage is applied to the power supply line 14, the diode D1 is then set to ON. As a result, the ESD current is discharged to the power supply line 14 through the diode D1, and the power supply circuit is protected from ESD.
On the other hand, as shown in
When the threshold voltage of the NMOS transistor MN1 is set to 0.3V and the voltage drop of resistor R2 is disregarded, the voltage Vgs between the gate and the source of the NMOS transistor MN1 is 1.5V (=1.8V−0.3V). Therefore, the voltage Vds between the drain and the source of the NMOS transistor MN1 is 1.8V (=3.3V−1.5V). Accordingly, the voltage of each part of the NMOS transistor MN1 lies within its voltage resistance level.
Moreover, since the voltage Vgs between the gate and the source of the NMOS transistor MN2 is 0V and the voltage at the drain of the NMOS transistor MN2 is 1.5V, the voltage Vds between the drain and the source of the NMOS transistor MN2 in an ON state is 1.5V−0V=1.5 V. Accordingly, the voltage of each part of the NMOS transistor MN2 also lies within its voltage resistance level.
The voltage Vds between the drain and the source of the PMOS transistor MP1 is 3.3V−1.8V=1.5V, and the voltage Vgs between the gate and the source of the PMOS transistor MP1 lies within its voltage resistance level.
The voltage Vds between the drain and the source of the PMOS transistor MP2 is 1.8V−0V=1.8V, and the voltage Vgs between the gate and the source of the PMOS transistor MP2 lies within its voltage resistance level.
Moreover, the voltage Vgs between the gate and the source of the NMOS transistor MN3 is 1.8V−0V=1.8V, and the voltage between the drain and the source of the NMOS transistor MN3 is 0V. Accordingly, the voltage of each part of the NMOS transistor MN3 also lies within its voltage resistance level.
Thus, the ESD protection circuit 10 of this embodiment meets the performance tolerance at the time of the normal operation of the semiconductor device.
In addition,
According to the embodiment, a power supply may not be supplied to the semiconductor device during a non-operating state. In this state, gates of the PMOS transistors MP1, MP2 are connected to the damping time constant circuit 13 and the power supply terminal VL, respectively, and the PMOS transistor MP1 set in the ON state. The ground line 15 is made to discharge the ESD current from the power supply line 14 by making the NMOS transistors MN1 and MN2 turn on through the PMOS transistors MP1 and MP2 at the time of ESD generation. Accordingly, it is possible to protect a power supply circuit from ESD.
In addition, the voltage of each part of the NMOS transistor MN1, MN2, MN3, and the PMOS transistor MP1 and MP2 is set as 1.8V or less, i.e., less than the voltage resistance levels of these transistors at the time of normal operation. For this reason, it is possible to provide a tolerant type ESD protection circuit using transistors having low voltage resistance levels. Furthermore, since the number of elements in the circuit has been reduced, it is possible to minimize the overall circuit size.
As shown in
In addition, the power supply terminal VL becomes unnecessary, although the power supply terminal VL is indicated as a power supply node in
According to the first modification, it is not necessary to apply the middle voltage from outside the semiconductor device. For this reason, it is possible to simplify the power supply specification of the semiconductor device.
More specifically, in the second modification, the damping time constant circuit 13 includes the PMOS transistors MP3 and MP4, which are connected in series between the power supply line 14 and the ground line 15, and the capacitor CP1. The capacitor CP1 is an NMOS transistor in the second modification. The drain of the PMOS transistor MP4 is connected with this capacitor CP1 and the gate of the PMOS transistor MP4 at a connection node between the gate of the PMOS transistor MP4 and the gate of the PMOS transistor MP1.
The second modification can also constitute the same damping time constant circuit as the embodiment, and the PMOS transistors MP3 and MP4 will provide resistance according to the second modification instead of the resistor R1. Compared with the case where resistance is formed in the same poly-silicon layer as a gate as in the embodiment, it is possible to reduce the circuit area, and thus to further miniaturize the circuit.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
P2011-264507 | Dec 2011 | JP | national |