Claims
- 1. A computer system comprising:
- at least one central processing unit:
- at least one memory system for storing programs to be run on said at least one central processing unit, including at least one cache memory system;
- at least one I/O system for communication with I/O devices;
- at least one system bus for connecting said at least one central processing unit, said at least one memory system, said at least one cache memory system, and said at least one I/O system, and
- at least one mixed voltage integrated circuit comprising an electrostatic discharge protection device comprising at least one cascode configured transistor pair, each of said transistor pairs further comprising:
- a first NMOS transistor having a first gate region, a first source region, and a first drain region, said first drain region coupled to said mixed voltage integrated circuit, said first gate region coupled to a low power supply of said mixed voltage integrated circuit;
- a second NMOS transistor, merged into the same active area as said first transistor, having a second gate region, a second source region, and a second drain region, said second gate region and said second source region of said second NMOS transistor coupled to a ground plane of said mixed voltage integrated circuit; and
- a shared diffusion region coupling the first source region of said first NMOS transistor to the second drain region of said second NMOS transistor, said shared diffusion region constructing the source region of said first NMOS transistor and constructing said second drain region of said second NMOS transistor.
Parent Case Info
This is a divisional of application Ser. No. 08/555,463 filed on Nov. 13, 1995 now U.S. Pat. No. 5,780,897.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
5698873 |
Colwell et al. |
Dec 1997 |
|
5764464 |
Botker et al. |
Jun 1998 |
|
5850195 |
Berlien, Jr. et al. |
Dec 1998 |
|
Non-Patent Literature Citations (2)
Entry |
Voldman, Steven H., "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50-and 0.25-um Channel Length CMOS Tehcnologies," Essex Junction, VT: IBM Microelectronics Division (1994). |
Voldman, Steven H., "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50-and 0.25-.mu.m Channel Length CMOS Technologies," Essex Junction, VT: IBM Microelectronics Division (1994). |
Divisions (1)
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Number |
Date |
Country |
Parent |
555463 |
Nov 1995 |
|