ESD protection for integrated circuits with multiple power domains

Abstract

An integrated circuit with ESD protection for multiple power domains is disclosed. A first ESD protection circuit is coupled in between the power pad of the first power domain and the ground pad of the second power domain to dissipate energy from electrostatic discharges. Similarly, a second ESD protection circuit is coupled in between the power pad of the second power domain and the ground pad of the first power domain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a conventional integrated circuit.

FIG. 2 is a simplified block diagram of a conventional integrated circuit with multiple power domains.

FIG. 3 is a simplified block diagram of a conventional integrated circuit with multiple power domains and discharge paths between the power domains.

FIG. 4 is a simplified block diagram of an integrated circuit with multiple power domains and discharge paths between the power domains.

FIG. 5 is a simplified block diagram of an integrated circuit in accordance with one embodiment of the present invention.

FIGS. 6( a) and 6(b) show ESD protection circuits in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

As explained above, conventional integrated circuit with multiple power domains with electrostatic discharge protection have several problems, such as constrained voltage levels in the power domains, noise coupling, and power up sequence issues. FIG. 4 is a simplified block diagram of an integrated circuit 400 that provides protection against electrostatic discharge while allowing power domains to have different voltage levels. FIG. 4 is very similar to FIG. 3 (and FIG. 2) and similar components are labeled with the same reference numerals. Therefore the description of these components is not repeated. FIG. 4 replaces ESD protection circuits 310 and 320 with ESD protection circuits 410 and 420 respectively. ESD protection circuits 410 and 420 replaces each diode of ESD protection circuits 310 and 320 with multiple diodes in series. Specifically, ESD protection circuit 410 includes diodes 411, 412, and 413 coupled in series with the input terminal of diode 411 coupled to power pad 210A and the output terminal of diode 413 coupled to power pad 210B. ESD protection circuit 410 also includes diodes 415, 416, and 417 coupled in series with the input terminal of diode 415 coupled to power pad 210B and the output terminal of diode 417 coupled to power pad 210A. ESD protection circuit 420 includes diodes 421, 422, and 423 coupled in series with the input terminal of diode 421 coupled to ground pad 220A and the output terminal of diode 423 coupled to ground pad 220B. ESD protection circuit 420 also includes diodes 425, 426, and 427 coupled in series with the input terminal of diode 425 coupled to ground pad 220B and the output terminal of diode 427 coupled to ground pad 220A. The diodes coupled in series in FIG. 4 provide the same basic functionality as the single diode in FIG. 3. However, due by putting several diodes in series, the voltage level on of the power domain can be different by as much as the sum of the threshold voltages of the diodes in series. Thus, for example with three diodes are coupled in series between power pad 210A and power pad 210B, the voltage level on power pad 210A and power pad 210B can be different by as much as three times the threshold voltage of a single diode. Thus, using a series of diodes in ESD protection circuit 410 allows power domains to have different voltages. However, the other problems such as the high series resistance of the diodes, which reduces the effectiveness of the ESD protection, are actually worsened.

FIG. 5 is a simplified block diagram of an integrated circuit 500 in accordance with one embodiment of the present invention. FIG. 3 is very similar to FIG. 2 and similar components are labeled with the same reference numerals. Therefore the description of these components is not repeated. FIG. 5 adds ESD protection circuits 510 and 520 to the circuits of FIG. 2. Specifically, an ESD protection circuit 510 is coupled between Ground pad 220A and power pad 210B, while ESD protection circuit 520 is coupled between ground pad 220B and Power pad 210A. As explained above ESD protection circuits are designed to have very high impedance at normal operating voltages. Thus, during normal operating voltages ESD protection circuit 510 and ESD protection circuit 520 would be non-conducting. However during an electrostatic discharge that creates a large voltage imbalance between power pad 210B and ground pad 220A, ESD protection circuit 510 protects logic circuits 230A and 230B by becoming conducting and dissipates the energy from the electrostatic discharge. Similarly, during an electrostatic discharge that creates a large voltage imbalance between power pad 210A and ground pad 220B, ESD protection circuit 520 protects logic circuits 230A and 230B by becoming conducting and dissipates the energy from the electrostatic discharge.

For example, in one embodiment of the present invention, ESD protection circuit 510 is a diode that is reverse biased between power pad 210B and ground pad 220A. The reverse breakdown voltage of the diode is set to be greater than the typical operating voltage applied to power pad 210B. Therefore, during normal operation the reverse biased diode prevents current from flowing from power pad 210B to ground pad 220A. However, if a positive electrostatic discharge occurs between power pad 210B and Ground pad 220A (i.e. the voltage on power pad 210B is driven significantly higher than the voltage at ground pad 220A), the diode would conduct if the electrostatic discharge voltage is greater than the reverse breakdown voltage of the diode. Thus, the power of the electrostatic discharge can be dissipated through the diode. Furthermore, if a negative electrostatic discharge occurs between power pad 210B and ground pad 220A (i.e. the voltage on ground pad 220A is driven higher than the voltage at power pad 210B) the diode becomes forward biased and would become conducting, which allows the power of the electrostatic discharge to be dissipated. ESD protection circuit 520 would work similarly between power pad 210A and ground pad 220B.

The presence of ESD protection circuit 510 and ESD protection circuit 520 provides protection against electrostatic discharges between any bonding pad across the power domains. For example, if an electrostatic discharge occurs between ground pad 220B and input/output pad 240A, the power from the electrostatic discharge is dissipated through ESD protection circuit 260A and ESD protection circuit 520. Some of the power may also be dissipated through ESD protection circuits 270A, ESD protection circuit 250A, and ESD protection circuit 520 or through ESD protection circuit 270A, ESD protection circuit 510, and ESD protection circuit 250B.

Because, the present invention provides ESD protection circuits between power pads and ground pads rather than between power pads of different power domains, the voltages of the different power domains are not tied together and can thus use different voltage levels. Furthermore, noise fluctuation from one power domain is not injected into the other power domain.

FIG. 6( a) is one embodiment for ESD protection circuit 510 in accordance with the present invention. The embodiment of FIG. 6(a) is a NMOS transistor 610 having a first power terminal coupled to power pad 210B, a second power terminal coupled to ground pad 220A and a control terminal coupled to ground pad 220A. During normal operation, NMOS transistor 610 is non-conducting due to having its control terminal coupled to ground pad 220A. However, if an electrostatic discharge raises the voltage of ground pad 220A to be greater than the voltage of power pad 210B plus the threshold voltage of NMOS transistor 610, NMOS transistor 610 becomes conducting and can dissipate the energy from the electrostatic discharge. In addition, if an electrostatic discharge raises the voltage of power pad 210B to be greater than the breakdown voltage of NMOS transistor 610, NMOS transistor 610 becomes conducting and can dissipate the energy from the electrostatic discharge.

FIG. 6( b) is a second embodiment for ESD protection circuit 510 in accordance with the present invention. The embodiment of FIG. 6(b) is a PMOS transistor 620 having a first power terminal coupled to power pad 210B, a second power terminal coupled to ground pad 220A and a control terminal coupled to power pad 210B. During normal operation, PMOS transistor 610 is non-conducting due to having its control terminal coupled to power pad 210B. However, if an electrostatic discharge raises the voltage of ground pad 220A to be greater than the voltage of power pad 210B plus the threshold voltage of PMOS transistor 620, PMOS transistor 610 becomes conducting and can dissipate the energy from the electrostatic discharge. In addition, if an electrostatic discharge raises the voltage of power pad 210B to be greater than the breakdown voltage of PMOS transistor 620, PMOS transistor 620 becomes conducting and can dissipate the energy from the electrostatic discharge.

The embodiments of ESD protection circuit 510 in FIGS. 6(a) and 6(b) can also be used for ESD protection circuit 520. However as explained above, the present invention is applicable for almost any ESD protection circuits and the specific type of ESD protection circuit used in an integrated circuit is not an integral part of the present invention.

In a particular embodiment of the present invention, a mixed signal integrated circuit has an analog power domain operating at 3.3 Volts and a digital power domain operating at 1.8 volts. In this integrated circuit, ESD protection circuit 510, i.e. the ESD protection circuit between the power pad of the analog power domain and the ground of the digital power domain is an NMOS transistor having a width of 360 micrometers, a length of 0.18 micrometers, threshold voltage of approximately 0.5 V and breakdown voltage of about 10 V. ESD protection circuit 520, i.e. the ESD protection circuit between the power pad of the digital power domain and the ground of the analog power domain is a similar NMOS transistor.

In the various embodiments of the present invention, novel circuits and methods have been described for creating an integrated circuit with protection against electrostatic discharge. The various embodiments of the structures and methods of this invention that are described above are illustrative only of the principles of this invention and are not intended to limit the scope of the invention to the particular embodiments described. For example, in view of this disclosure those skilled in the art can define other power domains, power pads, ground pads, ESD protection circuits, transistors, and so forth, and use these alternative features to create a method, or system according to the principles of this invention. Thus, the invention is limited only by the following claims.

Claims

1. An integrated circuit having a first power domain and a second power domain, the integrated circuit comprising: a first-power-domain power pad for the first power domain;a first-power-domain ground pad for the first power domain;a fist-power-domain logic circuit coupled between the first-power-domain power pad and the first-power-domain ground pad;a second-power-domain power pad for the second power domain;a second-power-domain ground pad for the second power domain;a second-power-domain-logic circuit coupled between the second-power-domain power pad and the second-power-domain ground pad; anda first ESD protection circuit coupled between the first-power-domain power pad and the second-power-domain ground pad.

2. The integrated circuit of claim 1, further comprising a second ESD protection circuit coupled between the second-power-domain power pad and the first-power-domain ground pad.

3. The integrated circuit of claim 2, wherein the second ESD protection circuit comprises a NMOS transistor.

4. The integrated circuit of claim 3, wherein the NMOS transistor comprises: a first power terminal coupled to the second-power-domain power pad;a second power terminal coupled to the first-power-domain ground pad; anda control terminal coupled to the first-power-domain ground pad.

5. The integrated circuit of claim 2, wherein the second ESD protection circuit comprises a PMOS transistor.

6. The integrated circuit of claim 5, wherein the PMOS transistor comprises: a first power terminal coupled to the second-power-domain power pad;a second power terminal coupled to the first-power-domain ground pad; anda control terminal coupled to the second-power-domain power pad.

7. The integrated circuit of claim 2, wherein the second ESD protection circuit is a diode.

8. The integrated circuit of claim 1, wherein the first ESD protection circuit comprises a NMOS transistor.

9. The integrated circuit of claim 8, wherein the NMOS transistor comprises: a first power terminal coupled to the first-power-domain power pad;a second power terminal coupled to the second-power-domain ground pad; anda control terminal coupled to the second-power-domain ground pad.

10. The integrated circuit of claim 1, wherein the first ESD protection circuit comprises a PMOS transistor.

11. The integrated circuit of claim 10, wherein the PMOS transistor comprises: a first power terminal coupled to the first-power-domain power pad;a second power terminal coupled to the second-power-domain ground pad; anda control terminal coupled to the first-power-domain power pad.

12. The integrated circuit of claim 1, wherein the first ESD protection circuit comprises a diode.

13. The integrated circuit of claim 1, further comprising: a first-power-domain input/output pad coupled to the first-power-domain logic circuit;a second ESD protection circuit coupled between the first-power-domain input/output pad and the first-power-domain ground pad.

14. The integrated circuit of claim 12; further comprising a third ESD protection circuit coupled between the first-power-domain input/output pad and the first-power-domain power pad; anda fourth ESD protection circuit coupled between the first-power-domain power pad and the first-power-domain ground pad.

15. The integrated circuit of claim 1, wherein the first power domain is an analog domain and the second power domain is a digital domain.

16. The integrated circuit of claim 1, wherein the first power domain has a first voltage, the second power domain has a second voltage, and the first voltage is greater than the second voltage.

17. A method of protecting an integrated circuit having a first power domain and a second power domain from an electrostatic discharge, the method comprising: conducting power of the electrostatic discharge from a second-power-domain power pad of the second power domain to a first-power-domain ground pad of the first power domain when the electrostatic discharge raises the voltage of the second-power-domain power pad; andconducting power of the electrostatic discharge from the first-power-domain ground pad to the second-power-domain power pad when the electrostatic discharge raises the voltage of the first-power-domain ground pad.

18. The method of claim 17, further comprising: conducting power of the electrostatic discharge from a first-power-domain power pad of the first power domain to a second-power-domain ground pad of the second power domain when the electrostatic discharge raises the voltage of the first-power-domain power pad; andconducting power of the electrostatic discharge from the second-power-domain ground pad of the second power domain to the first-power-domain power pad when the electrostatic discharge raises the voltage of the second-power-domain ground pad.

19. An integrated circuit having a first power domain and a second power domain, the integrated circuit comprising: means for conducting power of an electrostatic discharge from a second-power-domain power pad of the second power domain to a first-power-domain ground pad of the first power domain when the electrostatic discharge raises the voltage of the second-power-domain power pad; andmeans for conducting power of the electrostatic discharge from the first-power-domain ground pad to the second-power-domain power pad when the electrostatic discharge raises the voltage of the first-power-domain ground pad.

20. The integrated circuit of claim 19, further comprising: means for conducting power of the electrostatic discharge from a first-power-domain power pad of the first power domain to a second-power-domain ground pad of the second power domain when the electrostatic discharge raises the voltage of the first-power-domain power pad; andmeans for conducting power of the electrostatic discharge from the second-power-domain ground pad of the second power domain to the first-power-domain power pad when the electrostatic discharge raises the voltage of the second-power-domain ground pad.