The Authoritative Dicitionary of IEEE Standards Terms, (Seventh Edition) pp. 1165,1151.* |
United States Statutory Invention Registration, Reg. No. H707, Published Nov. 7, 1989, By Hu et al. Cypress Data Book CD-ROM, Winter 1997 S. (5 pages) F. Summer 1996. |
Capacitive Coupling of Floating Body Well to Sensitive Nodes Prevents High-Resistance CMOS Circuit From Latching-Up, By M. Bafleur et al., Electronics Letters Jun. 22nd, 1989, vol. 25, No. 13, pp. 860-861. |
Preventing latch-up in CMOS DACs, By Mark Alexander, Electronic Product Design, Feb. 1989, pp. 91-95. |
Mixed-Voltage Interface ESD Protection Circuits For Advanced Microprossors In Shallow Trench and LOCOS Isolation CMOS Technologies, By Steven H. Voldman et al., 1994 IEEE, pp. 10.3.1-10.3.4. |
CMOS Technologies for Logic Applications, By H. Mingam, Microelectronic Engineering 15 (1991), pp. 243-251. |
Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow, By T. Polgreen et al., 1989 EOS/ESD Symposium Proceedings, pp. 167-174. |
Preventing latchup in CMOS DACs, By Mark Alexander, Electronic Product Design, Feb. 1989, pp. 91-95. |
Peter Voss et al., U.S.S.N. 08/933,562, Method and Apparatus to Prevent Latch-up in CMOS Devices, filed Sep. 19, 1997. |
Preventing Latchup in CMOS DACs, By Mark Alexander, PCIM, Nov. 1988, pp. 54-59. |
On-Chip Decoupling Capacitor Design to Reduce Switching-Noise-Induced Instability in CMOS/SOI VLSI, By L.K. Wang et al., Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 100-101. |
An Advanced Submicron CMOS Technology With 2βm Pitch At All Levels, By M.H. El-Diwany et al., 1987 IEEE (4 pages). pp. 917-920. |
Core Clamps For Low Voltage Technologies, By S. Dabral et al., EOS/ESD Symposium 94-142, pp. 3.6.1-3.6.9. |
High-energy ion implantation for ULSI, By K. Tsukamoto et al., Nuclear Instruments and Methods in Physics Research B59/60 (1991), pp. 584-591. |
New Riverside University Dictionary (3 pages). (1984 Edn.). |
“Applications of MeV Ion Implantation in Semiconductor Device Manufacturing”, John O. Borland, 1995 Materials Research Society, vol. 354, pp 123-33. |
“Characteristics and Operation of MOS Field-Effect Devices”, Paul Richman, McGraw-Hill Book Company, 1967, pp 99-120. |
“Device Electronics for Integrated Circuits”, 2nd Ed., Richard S. Muller and Theodore I. Kamins, John Wiley & Sons, Inc., 1977, pp 454-467. |
“Dramatic Increases in Latchup Holding Voltage for Sub-0.5 βm CMOS Using Shallow S/D Junctions”, Jeffrey Lutze, et al., IEEE vol. 15, No. 11, 11/94. |
“High Density and Reduced Latchup Susceptibility CMOS Technology for VLSI”, J. Manoliu, et al., IEEE vol. EdL-4, No. 7, 7/83, pp 233-235. |
“Materials Processing and Advanced Well Structures Using High Energy Implantation for EPI Replacement”, D. Wristers, et al., SPIE, vol. 2635. |
“Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Conduction”, Thaddeus Gabara, IEEE, vol. 23, No. 5, 10/88, pp 1224-1232. |
“Structure to Prevent Latch-Up of CMOS Devices”, IBM Corp. 1986, IBM Technical Disclosure Bulletin, vol. 28, No. 10, 3/86, p 4277. |