S. Turgis et al, “A Novel Macromodel for Power Estimation in CMOS Structures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 11, Nov. 1998 with Abstract. |
Najm, F.N., “A survey of Power Estimation Techniques in VLSI Circuits”, IEEE Transactions on Very Large Scale Integration Systems, vol. 2, Issue 4, pp. 446-455, Dec. 1994.* |
Nemani et al., “Towards a High-Level Power Estimation Capability [Digital ICs]”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, Issue 6, pp. 588-598, Jun. 1996.* |
Landman, P., “High-Level Power Estimation”, International Symposium on Low Power Electronics and Design, 1996, pp. 29-35, Aug. 1996.* |
Wu et al., “Cycle-Accurate Macro-Models for RT-Level Power Analysis”, IEEE Transactions on Very Large Scale Integration Systems, vol. 6, Issue 4, pp. 520-528, Dec. 1998.* |
Gupta et al., “Power Macromodeling for High Level Power Estimation”, Proceedings of the 34th Design Automation Conference, pp. 365-370, Jun. 1997.* |
Givarlis et al., “Interface Exploration for Reduced Power in Core-Based Systems”, Proceedings 11th International Symposium on System Synthesis, pp. 117-122, Dec. 1998.* |
Fornaciari et al., “System-Level Power Evaluation Metrics”, Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon, pp. 323-330, Oct. 1997.* |
Yeh et al., “OPERAS/spl minus/an Object-Oriented Signal Processing System Architecture Simulator”, 27th Annual Simulation Symposium, pp. 198-207, Apr. 1994. |