Claims
- 1. A method for generating a mask layout file to eliminate antenna effects in an integrated circuit, comprising:
analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region, the feature moved based on a second design rule; placing a grounding feature in the space; and automatically connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.
- 2. The method of claim 1, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to a polysilicon over field area.
- 3. The method of claim 1, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to a metal over field area.
- 4. The method of claim 1, wherein connecting the grounding feature to the gate feature comprises:
creating a break in a polysilicon feature connected to the gate feature, the break separating the polysilicon feature and the gate feature; and connecting the gate feature and the polysilicon feature with a metal feature.
- 5. The method of claim 1, wherein the grounding feature comprises a diffusion diode.
- 6. The method of claim 5, wherein connecting the grounding feature to the gate feature comprises connecting the diffusion diode to a metal feature connected to the gate feature.
- 7. The method of claim 1, wherein moving the feature comprises maintaining connectivity associated with the feature.
- 8. The method of claim 1, further comprising the second design rule operable to prevent a violation from being created when moving the feature from the identified region.
- 9. The method of claim 1, further comprising compacting the pattern in the mask layout file in order to move the feature.
- 10. The method of claim 1, wherein moving the feature comprises moving the feature from a first layer to a second layer.
- 11. The method of claim 1, further comprising:
placing the grounding feature outside of the identified region; and creating an electrical connection from the grounding feature to the gate feature in order to maintain connectivity.
- 12. The method of claim 1, wherein the mask layout file is hierarchical.
- 13. A computer system for generating a mask layout file to eliminate antenna effects in an integrated circuit, comprising:
a processing resource; a computer readable memory; and processing instructions encoded in the computer readable memory, the processing instructions, when executed by the processing resource, operable to perform operations comprising:
analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region, the feature moved based on a second design rule; placing a grounding feature in the space; and connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.
- 14. The system of claim 13, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to polysilicon over field area.
- 15. The system of claim 13, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to a metal over field area.
- 16. The system of claim 13, wherein connecting the grounding feature to the gate feature comprises:
creating a break in a polysilicon feature connected to the gate feature, the break separating the polysilicon feature and the gate feature; and connecting the gate feature and the polysilicon feature with a metal feature.
- 17. The system of claim 13, wherein:
the grounding feature comprises a diffusion diode; and connecting the grounding feature to the gate feature comprises connecting the diffusion diode to a metal feature connected to the gate feature.
- 18. The system of claim 13, wherein moving the feature comprises maintaining connectivity associated with the feature.
- 19. The system of claim 13, further comprising the second design rule operable to prevent a violation from being created when moving the feature from the identified region.
- 20. The system of claim 13, further comprising the processing instructions operable to perform operations including compacting the pattern in the mask layout file in order to move the feature.
- 21. Software for generating a mask layout file to eliminate antenna effects in an integrated circuit, the software being embodied in computer-readable media and when executed operable to:
analyze a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; move a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region, the feature moved based on a second design rule; place a grounding feature in the space; and connect the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.
- 22. The software of claim 21, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to polysilicon over field area.
- 23. The software of claim 21, wherein the antenna ratio comprises a ratio of a polysilicon over diffusion area to a metal over field area.
- 24. The software of claim 21, wherein connecting the grounding feature to the gate feature comprises:
creating a break in a polysilicon feature connected to the gate feature, the break separating the polysilicon feature and the gate feature; and connecting the gate feature and the polysilicon feature with a metal feature.
- 25. The software of claim 21, wherein:
the grounding feature comprises a diffusion diode; and connecting the grounding feature to the gate feature comprises connecting the diffusion diode to a metal feature connected to the gate feature.
- 26. The software of claim 21, wherein moving the feature comprises maintaining connectivity associated with the feature.
- 27. The software of claim 21, further comprising the second design rule operable to prevent a violation from being created when moving the feature from the identified region.
- 28. The software of claim 21, further operable to compact the pattern in the mask layout file in order to move the feature.
Priority Claims (4)
Number |
Date |
Country |
Kind |
9711992.9 |
Jun 1997 |
GB |
|
9717346.2 |
Aug 1997 |
GB |
|
9803061.2 |
Feb 1998 |
GB |
|
9803202.2 |
Feb 1998 |
GB |
|
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09/684,793, filed Oct. 10, 2000 and entitled “AUTOMATIC DIFFUSION DIODE (‘ANTENNA’) CONSTRUCTION, PLACEMENT AND CONNECTION IN IC MASK LAYOUT DATABASE METHOD AND COMPUTER SOFTWARE.”
Continuations (1)
|
Number |
Date |
Country |
Parent |
09445265 |
Jun 2000 |
US |
Child |
10391156 |
Mar 2003 |
US |