Even order term mixer

Abstract

An even order term mixer for mixing two ac input signals includes two bipolar junction transistors (each having a base-emitter junction forward bias threshold voltage V.sub.T) with mutually connected collectors and cross-coupled bases and emitters. Each transistor receives a dc emitter bias current I.sub.E and both transistors each receive two single-ended ac input signals V.sub.1 (=.vertline.V.sub.1 .vertline..cos[2.pi.f.sub.1 t]) and V.sub.2 (=.vertline.V.sub.2 .vertline..cos[2.pi.f.sub.2 t]). Each transistor mixes its two ac input signals V.sub.1, V.sub.2 and produces a collector current representing the result thereof. The two collector currents sum at the interconnected collectors and produce across a resistor R.sub.C also connected thereto an ac output voltage V.sub.0 having even order terms and virtually no odd order terms of the mixing products (e.g. sum of and difference between the frequencies) of the two ac input signals.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to analog signal mixers, and in particular, to analog signal mixers in which the harmonic content of the output signal is limited.

2. Description of the Related Art

An important component used in virtually all wireless transmission and reception systems is an analog signal mixer. A mixer is variously used to modulate, demodulate and frequency-translate signals. A mixer can be used to up-convert a signal, i.e. translate a signal's frequency up, with or without modulation, and also to down-convert i.e. translate a signal's frequency down, with or without demodulation.

Referring to FIG. 1, a common conventional mixer configuration is that of a multiplier mixer, which can be realized in a number of different ways. A multiplier mixer typically receives a local oscillator ("LO") signal V.sub.1 and a radio frequency ("RF") signal V.sub.2, and multiplies them to produce an output signal V.sub.0. The magnitude and frequency of the output signal V.sub.0 are dependent upon the respective magnitudes and frequencies of the input signals V.sub.1 and V.sub.2. This dependence can be represented as follows: ##EQU1## where: V.sub.0 =output signal voltage

.vertline.V.sub.1 .vertline.=magnitude of carrier signal voltage f.sub.1 =frequency of carrier signal in Hertz .vertline.V.sub.2 .vertline.=magnitude of modulating signal voltage f.sub.2 =frequency of modulating signal in Hertz t=time in seconds cos[x]=cosine function of "x"

Referring to FIG. 2, one conventional mixer design is that of a Gilbert multiplier, sometimes referred to as a quad mixer. This type of mixer receives a dc bias voltage V.sub.CC via two resistors R.sub.C and a dc bias current I.sub.EE, as shown. The LO signal V.sub.1 is applied differentially to parallel differential amplifiers, each comprising two matched transistors. The RF signal V.sub.2 is applied differentially to another differential amplifier, also comprising two matched transistors as shown. The output signal V.sub.0, taken across the outputs of the parallel differential amplifiers, as shown, is a function of the two input signals V.sub.1 and V.sub.1, as follows:

V.sub.0 =I.sub.EE R.sub.C.tanh[V.sub.1 /(2V.sub.T)].tanh[V.sub.2 /(2V.sub.T)] where: V.sub.0 =output signal voltage I.sub.EE =emitters' dc supply current in amperes R.sub.C =collectors' output resistor in ohms V.sub.1 =.vertline.V.sub.1 .vertline..cos(2.pi.f.sub.1 t) V.sub.T =transistor base-emitter junction forward bias threshold voltage (.apprxeq.25 millivolts) V.sub.2 =.vertline.V.sub.2 .vertline..cos(2.pi.f.sub.2 t) tanh[x]=hyperbolic tangent function of "x"

Advantages of a Gilbert multiplier mixer included conversion gain, direct multiplication of the input signals and good compatibility with monolithic silicon integration techniques. However, disadvantages include "noisy" operation, distortion at signal levels above 2V.sub.T (unless degeneration is used) and poor operation under low voltage conditions, e.g. with V.sub.CC below three volts.

Referring to FIG. 3, another conventional mixer design uses the non-linear device characteristics of a semiconductor such as a bipolar junction transistor ("BJT"). A BJT in a common emitter configuration with collector V.sub.CC and base V.sub.BB bias voltages, receives its LO signal V.sub.1 and RF signal V.sub.2, summed together, at its base. Due to the inherent non-linearity of the transistor's operating characteristics, the output voltage V.sub.0 is a function of the input signals V.sub.1 and V.sub.2, as follows: ##EQU2## where: V.sub.CC =dc supply voltage (to collector)

I.sub.C =collector current in amperes I.sub.S =BJT saturation current in amperes ##EQU3## V.sub.BB =dc supply voltage (to base) K.sub.C =scalar constant, where C {0, 1, 2, . . . } n!=(n) (n-1) (n-2) . . . (1), where n {1,2,3, . . . }

Advantages of a "non-linear device" mixer include conversion gain, simplicity of design and good performance with respect to noise. However, a major disadvantage is the generation of undesired frequency terms, or harmonics, namely signal energy at frequency multiples of the mixing products of the input signals (e.g. signal energy at frequency multiples of the input signal frequencies, as well as combinations of multiples of, sums of and differences between the input signal frequencies).

Referring to FIG. 4, another conventional mixer design is a diode ring mixer. A ring of four diodes (or sometimes eight diodes) are connected in a bridge configuration to the center-tapped secondary windings of two transformers, as shown. The LO signal V.sub.1 and RF signal V.sub.2 are applied to the primary windings of the transformers, and the output signal V.sub.0 is taken from the center tap of one of the transformers, as shown. Similar to the non-linear device mixer discussed above, the output signal V.sub.0 is dependent upon the two input signals V.sub.1 and V.sub.2.

Advantages of a diode ring mixer include good performance with respect to noise, and a wide frequency range of use (e.g. up to many gigahertz). However, disadvantages include the need for a highlevel LO signal V.sub.1 and the need for transformers (or hybrid couplers) which thereby renders this design poorly suited to monolithic silicon integration techniques.

Accordingly, it would be desirable to have an improved mixer design which combines more of the advantages with fewer of the disadvantages of the foregoing conventional mixer designs.

SUMMARY OF THE INVENTION

A mixer in accordance with the present invention receives and mixes ac input signals to provide an ac output signal which includes even and odd order terms of the mixing products of the input signals. The output signal energy at each of the even order terms is greater than the output signal energy at adjacent ones of the odd order terms. A first mixing element receives and mixes the ac input signals to provide a first ac mixed signal. A second mixing element receives and mixes the ac input signals to provide a second ac mixed signal. A combining element coupled to the first and second mixing elements receives and combines the first and second ac mixed signals to provide an ac output signal. The ac output signal includes even and odd order terms of mixing products of the ac input signals, wherein each of the even order terms is greater in magnitude than adjacent ones of the odd order terms.

In a preferred embodiment of the present invention, each of the first and second mixing elements includes a transistor with two input ports and an output port. One input port receives one of the ac input signals, and the other input port receives another ac input signal via a coupling impedance. The two output ports provide the first and second ac mixed signals to a substantially nonreactive impedance (e.g. resistor) for combining therein to provide the ac output signal.

In an alternative preferred embodiment of the present invention, each of the first and second mixing elements includes two mutually coupled transistors, each of which has an input port and one of which has an output port. One input port receives one of the ac input signals, the other input port receives another ac input signal, and the output port produces one of the ac mixed signals. The combining element includes a resistor which receives and combines the ac mixed signals to produce the ac output signal.

A mixer having a circuit topology in accordance with a preferred embodiment of the present invention advantageously has input signal ports having input impedances which closely approximate the typical characteristic impedances of most video, radio frequency ("RF") and microwave systems, and therefore interfaces well with typical, standard video, RF and microwave circuits, equipment and instruments.

These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional functional block diagram for a multiplier mixer.

FIG. 2 is a schematic diagram of a conventional Gilbert multiplier mixer circuit.

FIG. 3 is a schematic diagram of a conventional non-linear device mixer circuit.

FIG. 4 is a schematic diagram of a conventional diode ring mixer circuit.

FIG. 5 is a block diagram of an ac circuit model of a mixer in accordance with the present invention.

FIGS. 6A, 6B, 6C and 6D illustrate the terminal configurations for transistors which can be used in a mixer in accordance with the present invention.

FIG. 7 illustrates a general ac signal model of a transistor.

FIG. 8 illustrates the circuit model of FIG. 5 using the transistor model of FIG. 7.

FIG. 9 is a schematic diagram of a preferred embodiment of a mixer in accordance with the present invention.

FIG. 10 is a schematic diagram for the ac signal model of the mixer of FIG. 9.

FIG. 11 is a schematic diagram of an alternative preferred embodiment of a mixer in accordance with the present invention.

FIG. 12 is a schematic diagram of another alternative preferred embodiment of a mixer in accordance with the present invention.

FIG. 13 illustrates the frequency content of the output signal of a mixer in accordance with the present invention.

FIG. 14A illustrates a circuit model used in computing the input impedance of a common emitter amplifier.

FIG. 14B illustrates a circuit model used in computing the input impedance of a common base amplifier.

FIG. 14C illustrates a circuit model used in computing the input impedance of a portion of a mixer in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 5, a mixer in accordance with the present invention can be modeled as shown. Two transistors Q.sub.A and Q.sub.B each receive two ac input signals from two ac signal sources V.sub.1 and V.sub.2. The transistors Q.sub.A and Q.sub.B mix their respective ac input signals and produce two ac mixed signals which are combined in a load, or output, impedance Z.sub.0 to provide an output voltage V.sub.0.

Referring to FIGS. 6A, 6B, 6C and 6D, the transistors Q.sub.A and Q.sub.B can selectively be of several types: bipolar junction transistors ("BJTs"; FIG. 6A); metal oxide semiconductor field-effect transistors ("MOSFETs"; FIG. 6B); junction field-effect transistors ("JFETs"; FIG. 6C); or Schottky Barrier Gate field-effect transistors ("MESFETs"; FIG. 6D); with their terminal connections as shown. of which transistor type is used, each transistor can be modeled as shown in FIG. 7. In accordance with this model, each transistor has an input impedance Z.sub.I across which an input voltage V.sub.I is applied, and an output current generator producing an output current I.sub.0 which is a function of the input voltage V.sub.I, i.e. I.sub.0 =f(V.sub.I). For the foregoing transistor types, this relationship between the output current I.sub.0 and the input voltage V.sub.I can be expressed as follows:

BJT: I.sub.0 =I.sub.S.exp[V.sub.I /V.sub.TB ] MOSFET: I.sub.0 =B(W/L)(V.sub.I -V.sub.TM).sup.2 JFET: I.sub.0 =I.sub.DSS (1-V.sub.I /V.sub.TJ).sup.2 MESFET: I.sub.0 =I.sub.DSM (1-V.sub.I /V.sub.PM).sup.2 where: I.sub.s =BJT saturation current in amperes I.sub.DSS =JFET drain-to-source current with gate shorted to source I.sub.DSM =MESFET drain-to-source current with gate shorted to source V.sub.TB =BJT thermal voltage (.apprxeq.25 millivolts at 25.degree. C.) V.sub.TM =MOSFET threshold voltage V.sub.TJ =JFET pinch-off voltage V.sub.PM =MESFET pinch-off voltage B=MOSFET conduction constant .apprxeq..mu.C.sub.0X W/(2L) .mu.=MOSFET channel mobility C.sub.0X =MOSFET gate oxide capacitance (farads) W=MOSFET channel width in microns L=MOSFET channel length in microns

Referring to FIG. 8, using the generalized transistor model of FIG. 7 in the mixer model of FIG. 5, a general expression for the output voltage V.sub.0 can be found as follows: ##EQU4##

Expanding f(V.sub.A)+f(V.sub.B):

f(V.sub.A)=a.sub.0 +a.sub.1 V.sub.A.sup.2 +a.sub.3 V.sub.A.sup.3 +a.sub.4 V.sub.A.sup.4 . . . f(V.sub.B)=b.sub.0 +b.sub.1 V.sub.B.sup.2 +b.sub.3 V.sub.B.sup.3 +b.sub.4 V.sub.B.sup.4 . . . where: a.sub.0 ="0th" scalar coefficient b.sub.0 ="0th" scalar coefficient a.sub.m ="mth" scalar coefficient b.sub.m ="mth" scalar coefficient m {1, 2, 3, 4, . . . }

Accordingly: ##EQU5##

Assuming a.sub.n .apprxeq.b.sub.n, where n {0, 1, 2, . . . }:

V.sub.0 .apprxeq.-Z.sub.0 [2a.sub.0 +2a.sub.2 (V.sub.1 -V.sub.2).sup.2 +2a.sub.4 (V.sub.1 -V.sub.2).sup.4 +. . . ]

Hence, from the foregoing it can be seen that while a dc term and the even-order terms, e.g. the even harmonics, of the mixing products of the input signals remain, the odd-order terms of the mixing products of the input signals are virtually eliminated. However, even if it cannot be assumed that a.sub.n .apprxeq.b.sub.n, the odd order terms will nonetheless be substantially suppressed relative to the even order terms since their scalar coefficients will be substantially less, i.e. .vertline.a.sub.n -b.sub.n .vertline.<<.vertline.a.sub.n +b.sub.n .vertline..

From the foregoing it can be further seen that if the two input signals have the same fundamental frequency, then a mixer in accordance with the present invention can be used as frequency doubler. In other words, since virtually only the even order terms of the mixing products of the input signals are produced and the second-order term is significant in magnitude compared to the fourth-order and higher terms, then with equal-frequency inputs, the present mixer can function well as a frequency doubler.

Referring to FIG. 9, a preferred embodiment of a mixer in accordance with the present invention includes two BJTs 102 ("Q.sub.1 "), 104 ("Q.sub.2 "), with mutually coupled collectors connected to a resistor 106 ("R.sub.C "). The emitter of the first transistor Q.sub.1 is coupled to the base of the second transistor Q.sub.2 via a serial impedance 114 consisting of a resistor 114R ("R.sub.E1 ") and capacitor 114C ("C.sub.E1 "). The emitter of the second transistor Q.sub.2 is coupled to the base of the first transistor Q.sub.1 via a serial impedance 116 consisting of a resistor 116R ("R.sub.E2 ") and capacitor 116C ("C.sub.E2 "). The transistors Q.sub.1 and Q.sub.2 are biased at their collectors by a dc voltage source 108 via their shared collector resistor R.sub.C, and at their respective emitters by dc current sources 110, 112. The transistors Q.sub.1 and Q.sub.2 are matched to each other, as are the passive components, i.e. resistors R.sub.E1 and R.sub.E2, and capacitors C.sub.E1 and C.sub.E2. The dc current sources 110, 112 provide equal emitter bias currents I.sub.E to the transistors Q.sub.1 and Q.sub.2. The capacitors C.sub.E1 and C.sub.E2 provide dc isolation between the base and emitter circuits of the transistors Q.sub.1 and Q.sub.2. Preferred values for the dc bias voltage V.sub.CC and currents I.sub.E, and for the passive components R.sub.1, R.sub.2, R.sub.C, R.sub.E1, R.sub.E2, C.sub.E1 and C.sub.E2 are as indicated in FIG. 9.

One ac input signal V.sub.1 is applied, via a resistor 118 ["R.sub.1 " ](e.g. the internal, or source, resistance of the first ac signal source 122), to the base of the first transistor Q.sub.1 and to the emitter of the second transistor Q.sub.1 via the serial coupling impedance 116. A second ac input signal V.sub.1 is applied, via a resistor 120 ["R.sub.2 "] (e.g. the internal, or source, resistance of the second ac signal source 124), to the base of the second transistor Q.sub.2 and to the emitter of the first transistor Q.sub.1 via the serial impedance 114. With the dc bias signals V.sub.CC and I.sub.E, and the ac input signals V.sub.1 and V.sub.2 applied as shown, collector currents I.sub.C1 and I.sub.C2 for the transistors Q.sub.1 and Q.sub.2, respectively, are generated. These collector currents I.sub.C1 and I.sub.C2 are produced from the mixing of currents within transistors Q.sub.1 and Q.sub.2, respectively, which are induced from the applications of input signals V.sub.1 and V.sub.2. These collector currents I.sub.C1 and I.sub.C2 combine in the collector resistor R.sub.C. The resulting ac signal voltage produced across the collector resistor R.sub.C constitutes the output signal V.sub.0.

Referring to FIG. 10, wherein the ac signal model for the mixer circuit 100 of FIG. 9 is shown, and in accordance with the foregoing discussion, the ac output signal V.sub.0 is generated substantially in accordance with the following: ##EQU6## where: R.sub.C =collector resistor value in ohms

I.sub.C1 =Q1 collector current in amperes I.sub.C2 =Q2 collector current in amperes I.sub.S =BJT saturation current in amperes I.sub.E =emitter current in amperes V.sub.BE0 32 base-emitter dc junction voltage V.sub.1 =carrier ("LO") signal voltage =.vertline.V.sub.1 .vertline..cos(2.pi.f.sub.1 t) V.sub.2 =modulating ("RF") signal voltage =.vertline.V.sub.2 .vertline..cos(2.pi.f.sub.2 t) V.sub.T =transistor base-emitter junction forward bias threshold voltage (.apprxeq.25 millivolts at 25.degree. C.) f.sub.1 =frequency of carrier signal f.sub.2 =frequency of modulating signal t=time in seconds exp[x]=e.sup.x cosh[x]=hyperbolic cosine function of "x"

From the foregoing it can be seen that the frequency spectrum of the output signal V.sub.0 includes even order terms and substantially suppressed odd order terms of the mixing products of the input signals V.sub.1 and V.sub.2. (The even order terms include Af.sub.1 +Bf.sub.2, Bf.sub.1 +Af.sub.2, .vertline.Af.sub.1 --Bf.sub.2 .vertline., and .vertline.Bf.sub.1 -Af.sub.2 .vertline., and the odd order terms include Cf.sub.1 +Df.sub.2, Df.sub.1 +Cf.sub.2, .vertline.Cf.sub.1 -Df.sub.2 .vertline. and .vertline.Df.sub.1 -Cf.sub.2 .vertline., where (A+B) {2, 4, 6, . . . } and (C+D) {1, 3, 5, . . . }.) Further, it should be appreciated that this limited frequency content in the output signal V.sub.0 has been achieved without the need for discrete reactive components, such as capacitors or inductors, or tuned elements, such as transmission line elements (e.g. open or shorted stubs), which are typically used to perform filtering functions (e.g. highpass, lowpass, bandpass or bandstop).

A mixer in accordance with the present invention has several additional advantages, such as good noise performance, low distortion and the ability to operate at low quiescent currents and with a low dc bias voltage (e.g. three volts and below). Further, a mixer in accordance with the present invention provides conversion gain and has a design structure well suited to monolithic silicon integration techniques, particularly since only one type of active device (e.g. NPN BJT) is needed. One drawback of the mixer of FIG. 9 is a relatively low isolation between the two input signals V.sub.1 and V.sub.2.

Exemplary comparisons of several operating characteristics between a mixer in accordance with the present invention and a conventional Gilbert multiplier mixer are shown below in Table 1:

TABLE 1______________________________________COMPARISON OF CONVENTIONAL MIXERS WITHEVEN ORDER TERM MIXERMixer Gilbert Mult. Gilbert Mult. Even OrderType Vcc = 5V, Vcc = 3V, Vcc = 3VPara- Zo = 50 Zo = 200 Zo = 200meter Ohms Ohms Ohms Unit______________________________________Noise Figure 17 9.4 5 dBConversion 1.8 0.9 2.4 dBGainOutput Level 0.29 0.63 0.53 Vpp("PldB")Supply 8.1 6.3 5 mACurrentLO-to-RF .apprxeq.30 .apprxeq.30 .apprxeq.6 dBRejection______________________________________

Referring to FIG. 11, an alternative preferred embodiment of a mixer in accordance with the present invention includes active and passive components interconnected substantially as discussed above and shown in FIG. 9, with the addition of some passive elements 226 ("R.sub.B1 "), 232 ("C.sub.B1 "), 228 ("R.sub.B2 "), 234 ("C.sub.B2 ") in the base circuits of the transistors 202 ("Q.sub.1 "), 204 ("Q.sub.2 "), and a dc base biasing voltage V.sub.BB, as shown.

The second dc voltage source 230 applies a dc bias voltage V.sub.BB via base resistors R.sub.B1 and R.sub.B2 to the bases of the transistors Q.sub.1 and Q.sub.2. The first ac input signal V.sub.1, via the series resistor 218 ("R.sub.1 "), is coupled to the base of the first transistor Q.sub.1 via a series coupling capacitor 232 ("C.sub.B1 "). The second ac input signal V.sub.2, via the series resistor 220 ("R.sub.2 " is coupled to the base of the second transistor Q.sub.2 via a series coupling capacitor 234 ("C.sub.B2 ").

Referring to FIG. 12, another alternative preferred embodiment of a mixer in accordance with the present invention includes two NPN BJTs 302 ("Q.sub.1 "), 304 ("Q.sub.2 "), two PNP BJTs 342 ("Q.sub.3 "), 344 ("Q.sub.4 ") and a collector resistor 306 ("R.sub.C "), connected substantially as shown. A dc voltage source 308 applies a dc bias voltage V.sub.CC, via the resistor R.sub.C, to the collectors of transistors Q.sub.1 and Q.sub.2. The base and emitter of transistor Q.sub.1 are coupled to the emitter of transistor Q.sub.3 and base of transistor Q.sub.4, respectively. The base and emitter of transistor Q.sub.2 are coupled to the emitter of transistor Q.sub.4 and base of transistor Q.sub.3, respectively. The collectors of transistors Q.sub.3 and Q.sub.4 are grounded. The dc current sources 346, 348 apply equal dc bias currents I.sub.B to the nodes which couple the base and emitter of transistors Q.sub.1 and Q.sub.3, and the base and emitter of transistors Q.sub.2 and Q.sub.4, respectively.

The first ac input signal V.sub.1 (e.g. LO) is applied to the base of transistor Q.sub.3 and emitter of transistor Q.sub.2. The second ac input signal V.sub.2 (e.g. RF) is applied to the base of transistor Q.sub.4 and emitter of transistor Q.sub.1. In accordance with the foregoing discussion regarding the mixer circuits of FIGS. 9 and 11, collector currents I.sub.C1 and I.sub.C2 are produced, which in turn combine in resistor R.sub.C and produce the output signal voltage V.sub.0 substantially in accordance with the following:

V.sub.0 .apprxeq.-2KI.sub.B R.sub.C.cosh[(V.sub.1 -V.sub.2)/V.sub.T ] where: V.sub.0 =output signal (volts) I.sub.B =base bias current (amperes) R.sub.C =collectors' output resistor (ohms) V.sub.1 =carrier ("LO") signal (volts) =.vertline.V.sub.1 .vertline..cos(2.pi.f.sub.1 t) V.sub.2 =modulating ("RF") signal (volts) =.vertline.V.sub.2 .vertline..cos(2.pi.f.sub.1 t) V.sub.T =transistor base-emitter junction forward bias threshold voltage (.apprxeq.25 millivolts at 25.degree. C.) f.sub.1 =frequency of carrier signal (Hz) f.sub.2 =frequency of modulating signal (Hz) t=time (seconds) K=constant relating collector currents =I.sub.SN /I.sub.SP .apprxeq.(I.sub.CN /I.sub.CP).exp[(V.sub.BEP -V.sub.BEN)/V.sub.T ] I.sub.SN =NPN BJT saturation current (amperes) I.sub.SP =PNP BJT saturation current (amperes) I.sub.CN =NPN BJT collector current (amperes) I.sub.CP =PNP BJT collector current (amperes) V.sub.BEP =PNP BJT base-emitter voltage V.sub.BEN =NPN BJT base-emitter voltage exp[x]=e.sup.x cosh[x]=hyperbolic cosine function of "x"

Referring to FIG. 13, an exemplary frequency spectrum of the output signal V.sub.0 is illustrated. In accordance with the foregoing discussion, the V.sub.0 frequency spectrum includes even order terms and suppressed odd order terms (e.g. <-40dB) of the mixing products of the input signals V.sub.1 and V.sub.2. (The even order terms include Af.sub.1 +Bf.sub.2, Bf.sub.1 +Af.sub.2, .vertline.Af.sub.1 --Bf.sub.2 .vertline. and .vertline.Bf.sub.1 -Af.sub.2 .vertline., and the odd order terms include Cf.sub.1 +Df.sub.2, Df.sub.1 +Cf.sub.2, .vertline.Cf.sub.1 -Df.sub.2 .vertline. and .vertline.Df.sub.1 -Cf.sub.2 .vertline., where (A+B) {2, 4, 6, . . .} and (C+D) {1, 3 , 5, . . . }.)

The exemplary output signal V.sub.0 frequency spectrum of FIG. 13 was computed in accordance with the discussion above for the preferred embodiment of FIGS. 9 and 10 as follows: ##EQU7## where: 0.03162.tbd.-20 dBm in a 50-ohm system

0.01.tbd.-30 dBm in a 50-ohm system f.sub.1 =1 gigahertz=1.times.10.sup.9 Hz f.sub.2 =900 megahertz=900.times.10.sup.6 Hz

The relative amplitudes for the even order terms (in decibels ["dB" ] relative to the second order term .vertline.f.sub.1 -f.sub.2 .vertline.) shown in FIG. 13 are listed below in Table 2. (The odd order terms are at least 40 dB down from the second order term .vertline.f.sub.1 -f.sub.2 .vertline..)

TABLE 2______________________________________Term Order Amplitude (dB)______________________________________.vertline.f.sub.1 - f.sub.2 .vertline. 2 02.vertline.f.sub.1 - f.sub.2 .vertline. 4 -31.22f.sub.2 2 -14.7.vertline.f.sub.1 + f.sub.2 .vertline. 2 02f.sub.1 2 +3.63f.sub.1 - f.sub.2 4 -24.92.vertline.f.sub.1 + f.sub.2 .vertline. 4 -31.23f.sub.1 + f.sub.2 4 -24.94f.sub.1 4 -26.9______________________________________

A mixer having a circuit topology in accordance with the foregoing preferred embodiments of the present invention advantageously has input signal ports with input impedances which closely approximate the typical characteristic impedances of most video, RF and microwave signal systems. Accordingly, such a mixer interfaces well with typical, standard video, RF and microwave circuits, equipment and instruments. This can be better understood while referring to FIGS. 14A-14C during the following discussion.

A typical BJT exhibits a base terminal impedance of several hundred ohms when operated in a common emitter configuration with a few milliamperes of collector bias current. This impedance is too high for efficient power transfer into the base terminal in typical 50-ohm or 75-ohm video, RF or microwave signal systems.

Referring to FIG. 14A, a common circuit model used when analyzing the input impedance of a common emitter amplifier is illustrated. Based upon this model, the input impedance Z.sub.in can be computed as follows:

Z.sub.in =.beta.(r.sub.e +Z.sub.e)=.beta.(V.sub.T /I.sub.C +Z.sub.e) where: .beta.=common emitter current gain =f(.OMEGA.)=f(2.pi.f) r.sub.e =intrinsic emitter resistance Z.sub.e =emitter circuit impedance V.sub.T =base-emitter junction forward bias threshold voltage I.sub.C =collector current Assuming that .beta.=50, V.sub.T =0.0259 volts, I.sub.C =2 mA and Z.sub.e =0 (typical exemplary operating conditions), then: ##EQU8##

As can be seen from the foregoing, the input impedance for a common emitter amplifier operating under typical conditions is much higher than 50 ohms, and therefore provides a poor match for a 50-ohm signal source. At higher frequencies, the transistor current gain .beta. [which is a function of frequency, i.e. .beta.=f(.OMEGA.)=f(2.pi.f)] decreases and acquires a phase lag. Accordingly, although the input impedance may therefore be reduced at higher frequencies, the current phase lag introduced by .beta. causes the input of the amplifier to appear capacitive. This causes the amplifier to continue to present a poor match to a 50-ohm signal source.

On the other hand, when operated in a common base configuration with a few milliamperes of collector bias current, a typical BJT exhibits an emitter terminal impedance on the order of a few ohms. This impedance is too low for efficient power transfer from a 50- or 75-ohm signal source.

Referring to FIG. 14B, a common circuit model used when analyzing the input impedance of a common base amplifier is illustrated. Based upon this model, the input impedance Z.sub.in can be computed as follows:

Z.sub.in =(1/g.sub.m +Z.sub.b /.beta.)=(V.sub.T /I.sub.C +Z.sub.b /.beta.) where: g.sub.m =transistor transconductance Z.sub.b =base circuit impedance Assuming that V.sub.T =0.0259 volts, I.sub.C =2 mA, Z.sub.b =0 and .beta.=50 (typical exemplary operating conditions), then: ##EQU9##

From the foregoing it can be seen that the input impedance for a common base amplifier operating under typical conditions is much lower than 50 ohms, and is therefore also a poor match for a 50-ohm signal source. Quite often the input impedance rises at higher frequencies due to combined effects of decreasing transistor current gain .beta. (as noted above) and the presence of a parasitic ohmic base resistance. Because of the phase lag associated with .beta. (as also noted above), the rising input impedance appears inductive. Thus, the input impedance continues to present a poor match to a 50-ohm signal source.

However, for a mixer topology in accordance with the present invention, when operated at a few milliamperes of bias current, the input terminal impedance is quite close to the typical characteristic impedances of most video, RF and microwave signal systems.

Referring to FIG. 14C, the input impedance of a mixer in accordance with a preferred embodiment of the present invention (e.g. as shown in FIG. 9) can be computed as follows: ##EQU10## Assuming that V.sub.T =0.0259 volts, I.sub.C =2 mA, Z.sub.S =50 and .beta.=50 (typical exemplary operating conditions), then: ##EQU11##

From the foregoing it can be seen that the input impedance of a mixer in accordance with the present invention is close to the typical 50-ohm impedance of a signal source that is driving the other input. Hence, with both inputs driven by such sources, the input impedance of either input becomes approximately 62 ohms. This represents a standing wave ratio ("SWR") of 1.23:1 in a 50-ohm system. Hence, both signal sources are reasonably well matched.

This match is maintained at moderately high frequencies for two reasons. First, inductive impedance effects observed due to an increase in the intrinsic emitter resistance r.sub.e are reduced, since to affect the input impedance, r.sub.e must increase relative to the summation of it and the source impedance (i.e. r.sub.e +Z.sub.s) rather than just r.sub.e, as for the common base amplifier. Second, a decrease in the transistor current gain .beta. has only a small effect on the input impedance and also partially cancels an increase in r.sub.e due to frequency-dependent .beta. decreasing at higher frequencies.

Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of this invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such a specific embodiments.

Claims

1. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

first mixer means for receiving and mixing first and second ac input signals to provide a first ac mixed signal, wherein said first mixer means is de-biased in a first linear operating region and has a first input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said first input impedance;

second mixer means coupled to said first mixer means for receiving and mixing said first and second ac input signals to provide a second ac mixed signal, wherein said second mixer means is de-biased in a second linear operating region and has a second input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said second input impedance; and

combiner means coupled to said first and second mixer means for receiving and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

2. A signal mixer as recited in claim 1, wherein said first mixer means comprises:

a first serial impedance; and

a first transistor which includes a first terminal for receiving at least part of said first ac input signal, a second terminal coupled to said first serial impedance for receiving said second ac input signal, and a third terminal for providing said first ac mixed signal.

3. A signal mixer as recited in claim 2, wherein said second mixer means comprises:

a second serial impedance; and

a second transistor which includes a first terminal for receiving at least part of said second ac input signal, a second terminal coupled to said second serial impedance for receiving said first ac input signal, and a third terminal for providing said second ac mixed signal.

4. A signal mixer as recited in claim 1, wherein said combiner means comprises a resistor coupled to said first and second mixer means, said first and second ac mixed signals comprise first and second ac electrical currents, respectively, through said resistor and said ac output signal comprises an ac voltage.

5. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

a first transistor circuit which includes a first transistor which is dc-biased in a first linear operating region and has associated therewith a first input impedance with first and second opposing ends, a primary input circuit connected to said first end of said first input impedance for receiving a first ac input signal, a secondary input circuit connected to said second end of said first input impedance for receiving a first dc signal and at least part of a second ac input signal, and an output for providing a first ac mixed signal;

a second transistor circuit which includes a second transistor which is dc-biased in a second linear operating region and has associated therewith a second input impedance with first and second opposing ends, a primary input circuit connected to said first end of said second input impedance for receiving said second ac input signal, a secondary input circuit connected to said second end of said second input impedance for receiving a second dc signal and at least part of said first ac input signal, and an output for providing a second ac mixed signal, wherein said second transistor circuit output is coupled to said first transistor circuit output; and

a resistor coupled to said first and second transistor circuit outputs to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

6. A signal mixer as recited in claim 5, wherein said first transistor secondary input circuit comprises a transistor terminal and a coupling impedance connected thereto for coupling thereto said received at least part of said second ac input signal.

7. A signal mixer as recited in claim 6, wherein said second transistor secondary input circuit comprises a transistor terminal and a coupling impedance connected thereto for coupling thereto said received at least part of said first ac input signal.

8. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

a first transistor which includes a primary terminal for receiving a first dc signal, a secondary terminal for receiving a first ac input signal, and a tertiary terminal for providing a first ac mixed signal;

a second transistor which includes a primary terminal for receiving a second dc signal, a secondary terminal for receiving a second ac input signal, and a tertiary terminal for providing a second ac mixed signal, wherein said tertiary terminal of said second transistor is coupled to said tertiary terminal of said first transistor;

a third transistor which includes a primary terminal coupled to said secondary terminal of said second transistor, a secondary terminal coupled to said primary terminal of said first transistor, and a tertiary terminal;

a fourth transistor which includes a primary terminal coupled to said secondary terminal of said first transistor, a secondary terminal coupled to said primary terminal of said second transistor, and a tertiary terminal; and

a resistor coupled to said tertiary terminals of said first and second transistors to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

9. A signal mixer as recited in claim 8, wherein said first, second, third and fourth transistors comprise first, second, third and fourth bipolar junction transistors, respectively, with each having associated therewith a base-emitter junction forward bias threshold voltage, and wherein each one of said first and second bipolar junction transistors has associated therewith a first base-emitter voltage, a base current and a first collector current, and further wherein each one of said third and fourth bipolar junction transistors has associated therewith a second base-emitter voltage and a second collector current, and still further wherein said ac output signal is provided approximately in accordance with:

V.sub.0 .apprxeq.-2I.sub.B R.sub.C (I.sub.CN /I.sub.CP).exp[(V.sub.BEP -V.sub.BEN)V.sub.1 -V.sub.2)/V.sub.T ]

where:

V.sub.0 =voltage value of said ac output signal

I.sub.B =value of said base current

R.sub.C =resistance value of said resistor

V.sub.1 =voltage value of said first ac input signal

V.sub.2 =voltage value of said first ac input signal

V.sub.T =value of said base-emitter junction forward bias threshold voltage

I.sub.CN =value of said first collector current

I.sub.CP =value of said second collector current

V.sub.BEP =value of said second base-emitter voltage

V.sub.BEN 32 value of said first base-emitter voltage

exp[(V.sub.BEP -V.sub.BEN)/V.sub.T ]=exponential function of (V.sub.BEP -V.sub.BEN)/V.sub.T

cosh[(V.sub.1 -V.sub.2)/V.sub.T ]=hyperbolic cosine function of [(V.sub.1 -V.sub.2)/V.sub.T ].

10. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:

inputting first and second ac input signals to opposing ends of an input impedance of a first signal mixer which is dc-biased in a first linear operating region;

mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal;

inputting said first and second ac input signals to opposing ends of an input impedance of a second signal mixer which is dc-biased in a second linear operating region;

mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal; and

combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

11. A signal mixing method as recited in claim 10, wherein said step of mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal comprises:

inputting at least part of said first ac input signal to a first terminal of a first transistor;

inputting said second ac input signal to a first serial impedance coupled to a second terminal of said first transistor; and

outputting said first ac mixed signal from a third terminal of said first transistor.

12. A signal mixing method as recited in claim 11, wherein said step of mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal comprises:

inputting at least part of said second ac input signal to a fourth terminal of a second transistor;

inputting said first ac input signal to a second serial impedance coupled to a fifth terminal of said second transistor; and

outputting said second ac mixed signal from a sixth terminal of said second transistor.

13. A signal mixing method as recited in claim 10, wherein said step of combining said first and second ac mixed signals to provide an ac output signal comprises:

receiving first and second ac electrical currents as said first and second ac mixed signals, respectively;

combining said first and second ac electrical currents in a resistor; and

providing said ac output signal as an ac voltage across said resistor.

14. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:

inputting a first ac input signal to a primary input circuit of a first transistor circuit which includes a first transistor which is dc-biased in a first linear operating region and has associated therewith a first input impedance with first and second opposing ends, wherein said first transistor primary input circuit is connected to said first end of said first input impedance;

inputting a first dc signal and at least part of a second ac input signal to a secondary input circuit of said first transistor circuit, wherein said first transistor secondary input circuit is connected to said second end of said first input impedance;

outputting a first ac mixed signal from an output of said first transistor circuit;

inputting said second ac input signal to a primary input circuit of a second transistor circuit which includes a second transistor which is dc-biased in a second linear operating region and has associated therewith a second input impedance with first and second opposing ends, wherein said second transistor primary input circuit is connected to said first end of said second input impedance;

inputting a second dc signal and at least part of said first ac input signal to a secondary input circuit of said second transistor circuit, wherein said second transistor secondary input circuit is connected to said second end of said second input impedance;

outputting a second ac mixed signal from an output of said second transistor circuit;

inputting said first and second ac mixed signals to a resistor; and

outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

15. A signal mixing method as recited in claim 14, wherein said step of inputting a first dc signal and at least part of a second ac input signal to a secondary input circuit of said first transistor circuit comprises inputting said at least part of said second ac input signal to a coupling impedance which comprises a portion of said first transistor circuit.

16. A signal mixing method as recited in claim 15, wherein said step of inputting a second dc signal and at least part of said first ac input signal to a secondary input circuit of said second transistor circuit comprises inputting said at least part of said first ac input signal to a coupling impedance which comprises a portion of said second transistor circuit.

17. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

inputting a first dc signal to a node connecting a primary terminal of a first transistor and a secondary terminal of a third transistor;

inputting a first ac input signal to a secondary terminal of said first transistor and to a primary terminal of a fourth transistor;

outputting a first ac mixed signal from a tertiary terminal of said first transistor;

inputting a second dc signal to a node connecting a primary terminal of a second transistor and secondary terminal of said fourth transistor;

inputting a second ac input signal to a secondary terminal of said second transistor and to a primary terminal of said third transistor;

outputting a second ac mixed signal from a tertiary terminal of said second transistor;

inputting said first and second ac mixed signals to a resistor; and

outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

18. A signal mixing method as recited in claim 17, wherein said first, second, third and fourth transistors comprise first, second, third and fourth bipolar junction transistors, respectively, with each having associated therewith a base-emitter junction forward bias threshold voltage, and wherein each one of said first and second bipolar junction transistors has associated therewith a first base-emitter voltage, a base current and a first collector current, and further wherein each one of said third and fourth bipolar junction transistors has associated therewith a second base-emitter voltage and a second collector current, and still further wherein said step of outputting an ac output signal comprises outputting said ac output signal approximately in accordance with:

V.sub.0 .apprxeq.-2I.sub.B R.sub.C (I.sub.CN /I.sub.CP).exp[(V.sub.BEP -V.sub.BEN) /V.sub.T ].cosh[(V.sub.1 -V.sub.2)/V.sub.T ]

where:

V.sub.0 =voltage value of said ac output signal

I.sub.B =value of said base current

R.sub.C =resistance value of said resistor

V.sub.1 =voltage value of said first ac input signal

V.sub.2 =voltage value of said first ac input signal

V.sub.T =value of said base-emitter junction forward bias threshold voltage

I.sub.CN =value of said first collector current

I.sub.CP =value of said second collector current

V.sub.BEP =value of said second base-emitter voltage

V.sub.BEN =value of said first base-emitter voltage

exp[(V.sub.BEP -V.sub.BEN)/V.sub.T ]=exponential function of (V.sub.BEP -V.sub.BEN)/V.sub.T

cosh[(V.sub.1 -V.sub.2)/V.sub.T ]=hyperbolic cosine function of [(V.sub.1 -V.sub.2)/V.sub.T ].

19. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

first mixer means for receiving and mixing first and second ac input signals to provide a first ac mixed signal, wherein said first mixer means is dc-biased in a first linear operating region and includes:

a first transistor with a primary terminal, a secondary terminal for receiving said second ac input signal and a tertiary terminal for providing said first ac mixed signal, and

a second transistor with a primary terminal for receiving said first ac input signal, a secondary terminal coupled to said first transistor primary terminal and a tertiary terminal;

second mixer means coupled to said first mixer means for receiving and mixing said first and second ac input signals to provide a second ac mixed signal, wherein said second mixer means is dc-biased in a second linear operating region; and

combiner means coupled to said first and second mixer means for receiving and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

20. A signal mixer as recited in claim 19, wherein said second mixer means comprises:

a third transistor including a primary terminal, a secondary terminal for receiving said first ac input signal, and a tertiary terminal for providing said second ac mixed signal; and

a fourth transistor including a primary terminal for receiving said second ac input signal, a secondary terminal coupled to said third transistor primary terminal, and a tertiary terminal.

21. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:

a first transistor circuit which is dc-biased in a first linear operating region and includes a primary input circuit for receiving a first ac input signal, a secondary input circuit for receiving a first dc signal and at least part of a second ac input signal, and an output for providing a first ac mixed signal;

a second transistor circuit which is dc-biased in a second linear operating region and includes a primary input circuit for receiving said second ac input signal, a secondary input circuit for receiving a second dc signal and at least part of said first ac input signal, and an output for providing a second ac mixed signal, wherein said second transistor circuit output is coupled to said first transistor circuit output; and

a resistor coupled to said first and second transistor circuit outputs to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms;

wherein said first and second transistor circuits comprise first and second bipolar junction transistors, respectively, with each having a base-emitter junction forward bias threshold voltage associated therewith, and further wherein said ac output signal is provided approximately in accordance with:

V.sub.0 .apprxeq.-2IR.cosh[(V.sub.1 -V.sub.2)/V.sub.T ]

where:

V.sub.0 =voltage value of said ac output signal

I=current value of each of said first and second dc signals

R=resistance value of said resistor

V.sub.1 =voltage value of said first ac input signal

V.sub.2 =voltage value of said second ac input signal

V.sub.T =value of said base-emitter junction forward bias threshold voltage

cosh[(V.sub.1 -V.sub.2)/V.sub.T ]=hyperbolic cosine of (V.sub.1 -V.sub.2)/V.sub.T.

22. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:

inputting first and second ac input signals to a first signal mixer which is dc-biased in a first linear operating region;

mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal by:

inputting said second ac input signal to a secondary terminal of a first transistor,

inputting said first ac input signal to a primary terminal of a second transistor,

coupling a first intermediate signal from a secondary terminal of said second transistor to a primary terminal of said first transistor, and

outputting said first ac mixed signal from a tertiary terminal of said first transistor;

inputting said first and second ac input signals to a second signal mixer which is dc-biased in a second linear operating region;

mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal; and

combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.

23. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:

inputting a first ac input signal to a primary input circuit of a first transistor circuit which is dc-biased in a first linear operating region;

inputting a first dc signal and at least part of a second ac input signal to a secondary input circuit of said first transistor circuit;

outputting a first ac mixed signal from an output of said first transistor circuit;

inputting said second ac input signal to a primary input circuit of a second transistor circuit which is dc-biased in a second linear operating region;

inputting a second dc signal and at least part of said first ac input signal to a secondary input circuit of said second transistor circuit;

outputting a second ac mixed signal from an output of said second transistor circuit;

inputting said first and second ac mixed signals to a resistor; and

outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms;

wherein said first and second transistor circuits comprise first and second bipolar junction transistors, respectively, with each having a base-emitter junction forward bias threshold voltage associated therewith, and further wherein said step of outputting an ac output signal comprises outputting said ac output signal approximately in accordance with:

V.sub.0 .apprxeq.-2IR.cosh[(V.sub.1 -V.sub.2)/V.sub.T ]

where:

V.sub.0 =voltage value of said ac output signal

I=current value of each of said first and second dc signals

R=resistance value of said resistor

V.sub.1 =voltage value of said first ac input signal

V.sub.2 =voltage value of said second ac input signal

V.sub.T =value of said base-emitter junction forward bias threshold voltage

cosh[(V.sub.1 -V.sub.2)/V.sub.T ]=hyperbolic cosine of (V.sub.1 -V.sub.2)/V.sub.T.

24. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:

inputting first and second ac input signals to a first signal mixer which is dc-biased in a first linear operating region;

mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal by:

inputting said second ac input signal to a secondary terminal of a first transistor,

inputting said first ac input signal to a primary terminal of a second transistor,

coupling a first intermediate signal from a secondary terminal of said second transistor to a primary terminal of said first transistor, and

outputting said first ac mixed signal from a tertiary terminal of said first transistor;

inputting said first and second ac input signals to a second signal mixer which is dc-biased in a second linear operating region;

mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal by:

inputting said first ac input signal to a secondary terminal of a third transistor,

inputting said second ac input signal to a primary terminal of a fourth transistor,

coupling a second intermediate signal from a secondary terminal of said fourth transistor to a primary terminal of said third transistor, and

outputting said second ac mixed signal from a tertiary terminal of said third transistor;

combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.