EVENT HOLDING CIRCUIT

Abstract

An event holding circuit configured to monitor plural monitored boards, write collected event information, and hold the event information until a processor reads the event information, the event holding circuit includes a holding circuit including an OR gate, so that a logical sum output of the collected event information and holding event information is written in a memory where written contents until the last time have been read from an address area of the memory where the event information is to be written.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a related art transmission apparatus;

FIG. 2 is a sequence diagram of processing operations in the related art;

FIG. 3 is a view showing a memory in the related art;

FIG. 4 is a block diagram of another related art case where polling is applied;

FIG. 5 is a sequence diagram of processing operations by the polling;

FIG. 6 is a block diagram for explaining an embodiment of the present invention;

FIG. 7 is a timing chart of a holding circuit of the embodiment of the present invention; and

FIG. 8 is a timing chart of a clear circuit of the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description is given below, with reference to the FIG. 6 through FIG. 8 of embodiments of the present invention.

FIG. 6 is a block diagram for explaining an embodiment of the present invention. Referring to FIG. 6, in an event holding circuit of the embodiment of the present invention, plural monitored boards 2 such as main signal boards are monitored by a monitoring board 1. Collected event information such as alarm information is written and held in a memory such as a DP-RAM 9 until a processor 3 reads it out. The event holding circuit of the embodiment of the present invention has a holding circuit 12 including an OR gate, so that a logical sum output of the collected event information and holding event information is written in a memory where written contents until the last time have been read from an address area of the memory where this event information to be written.

First Embodiment of the Present Invention

In FIG. 6, “1” denotes a monitoring board. “2” denotes monitored boards of #1 through #m. “3” denotes a CPU. “4” denotes a monitored control interface part. “5” denotes a sending timing generation part. “6” denotes a sending part and “7” denotes a receiving part. “8” denotes a serial interface part. “9” denotes a DP-RAM. “AP” denotes an A port and “BP” denotes a B port. “10” denotes an address generating part. “11” denotes a WENA generating part (write enable signal generating part A). “12” denotes a holding circuit. “12a” denotes an OR gate, “12b” denotes a buffer gate, and “12c” denotes a buffer. “13” denotes a selector. “14” denotes a serial and parallel conversion part (S/P). “15” denotes a timing generation part. “16” denotes a Startbit detecting part. “17” denotes a clear circuit. “17a” denotes a buffer; “17b” denotes a buffer gate; “17c” denotes a selector; “17d” denotes a flip-flop (FF) as an address holding part. “18” denotes a WENA generating part (write enable signal generating part B). “adra”, “adrb”, and “Aftadrb” denote address signals (address information). “dtaorg”, “dtaq”, “dta”, “dtb”, or “Prdtb” denote data. “wena” and “wenb” denote enable signals. While the enable signals “wena” and “wenb” should be the write enable signals, in a case where read enable signals are necessary, they may be input to the DP-RAM 9 by known means.

The receiving part 7 includes the address generating part 10, the WENA generating part 11 configured to generate the enable signal “wena”, and the holding circuit 12.

The serial interface part 8 includes the selector 13, the serial and parallel conversion part (S/P) 14, the Start bit detecting part 16, and the timing generating part 15.

The clear circuit 17 is provided at the B port BP of the DP-RAM 9 where the processor 3 is connected. The clear circuit 17 includes the buffer 17a, the buffer gate 17b, the selector 17c, the flip flop 17d, the WENB generating part 18 configured to generate the enable signal “wenb”. The serial interface part 8 has a serial and parallel switching part (not shown in FIG. 6) provided at a front step of the selector 13 so that the sending data from the sending part 6 can be converted from the parallel date to the serial data.

The sending timing generation part 5, as well as the sending timing generation part 105 shown in FIG. 4, sends a start sending notification to the sending part 6 at a designated polling interval without receiving the instruction to start sending from the CPU 3. The sending timing generation part 5 inputs reading data indicating the contents (kinds) of the information collected from the monitored boards 2 to the sending part 6 and the address generation part 10 of the receiving part 7. The sending timing generating part 5 inputs the path setting information selecting the #1 through #m monitored boards 2 to the address generation part 10 of the receiving part 7 and the selector 13 of the serial interface part 8. The serial interface part 8 converts the sending data from the sending part 6 into the serial data by using the parallel and serial conversion part not shown in FIG. 6. The serial interface part 8 selects the monitored board 2 following the path setting information from the sending timing generation part 5 by using the selector 13 and sends the serial data.

When the serial data including the alarm information from the monitored board 2 are received at the serial interface part 8 of the monitoring board 1, the serial data are forwarded from the selector 13 to the serial and parallel conversion part 14 and the Start bit detecting part 16. When the Start bit detecting part 16 detects the Start bit, the detection signal of the Start bit is output to the timing generation part 15. The timing generation part 15 generates a master clock that is timing-synchronized with the Start bit so as to output it to the serial and parallel conversion part 14. The serial and parallel conversion part 14, following the master clock, converts the serial data from the selector 13 to the parallel data and forwards receiving data dtaorg as the parallel data to the receiving part 7. The timing signal that is output from the timing generation part 15 is input to the WENA generation part 11 and the address generation part 10 of the receiving part 7.

If the event information collected at the address area is written before the CPU 3 reads from the B port BP side of the DP-RAM 9, the holding event information previously written is rewritten (overwritten). Hence, it is necessary to hold the holding event information previously written until the CPU 3 reads it. Because of this, the holding circuit is formed by a logic circuit including the OR gate 12a so that the holding information that is previously written data can be held until the CPU 3 reads the data that are the event information. When the CPU 3 reads the data that are the event information, the data of the address area, namely the holding event information is cleared by the clear circuit 17. The address generation part 10, the WENA generation part 11, and the holding circuit 12 are connected to the A port AP where the event information of the DP-RAM 9 is written. While the holding circuit 12 has a structure corresponding to the number of bytes of the receiving data dtaorg, the holding circuit 12 can be realized under a simple structure, namely the OR gate 12a, the buffer 12b, and the buffer gate 12c.

For example, in a case where the data Cell 3 (See FIG. 3) of the monitored board #2 is collected, the start sending notification, the reading data, and the path setting data are output from the sending timing generation part 5 and the sending part 6. The sending data include the cell number (Cell 3). The sending data including the information of the cell number are output from the sending part 6 to the serial interface part 8. The selector 13 of the serial interface part 8 selects the path where the above-mentioned monitored board #2 is connected, following the path setting data from the sending timing generation part 5. As a result of this, the serial data including the cell number (Cell 3) required to obtain the event information is sent from the serial interface part 8 to the monitored board #2. The address generation part 10, based on the cell number included in the reading data from the sending timing generation part 5 and the path setting data, prepares to generate the address signal adra designating the cell number (Cell 3) of the monitored board #2.

When the serial data of the response from the monitored board #2 are received by the serial interface part 8, as discussed above, the start bit of a head of the serial data is detected by the Startbit detection part 16, the master clock synchronized with the detection signal is generated by the timing generation part 15, and the master clock is input to the serial and parallel conversion part 14. The received serial data are converted to the parallel data by the serial and parallel conversion part 14 so as to be input to the holding circuit 12. The timing signal from the timing generation part 15 is input to the address generation part 10 and the WENA generation part 11.

The address generation part 10, based on the timing signal, inputs the address signal adra designating the cell number (Cell 3) of the monitored board #2 generated and prepared previously to the A port AP of the DP-RAM 9. The address generation part 10 reads the event information from the address area of the address signal adra and inputs it to the buffer 12c of the holding circuit 12. The data dtaq from the buffer 12c and the data dtaorg converted to the parallel data by the serial and parallel conversion part 14 are input to the OR gate 12a.

The enable signal wena generated by following the timing signal from the timing generation part 15 is input to the A port AP of the DP-RAM 9 and the buffer gate 12b by the WENA generation part 11. As a result of this, a logical sum output of the collected event information (dtaorg) and the holding event information (dtaq) is input to the A port AP of the DP-RAM 9 via the buffer gate 12b. The logical sum is written in the address area following the address signal adra from the address generation part 10. A logical sum output of the newly collected event information and the event information before the CPU 3 reads it is written in the DP-RAM 9 so as to be capable of being held.

It is general practice that the clear process of the memory is implemented by writing “0” from the CPU 3. The clear circuit 17 is provided in order to reduce the processing workload of the CPU 3. As discussed above, the clear circuit 17 includes the buffer 17a, the buffer gate 17b, the selector 17c, the flip flop 17d, and the WENB generation part configured to generate the enable signal wenb. The buffer 17a and the buffer gate 17b are provided corresponding to the byte structure of the data Predtb.

When the CPU 3 reads the event information from the DP-RAM 9, the control signal and the address signal of the DP-RAM 9 are output. The selector 17c of the clear circuit 17 selects the flip flop side 17d when the enable signal wenb from the WENB generation part 18 is input. Before that, the selector 17c selects the CPU 3 side. Therefore, the address signal from the CPU 3 is input to the B port BP of the DP-RAM 9 via the selector 17c. The data Predtb (holding event information) is read from the DP-RAM 9 and input to the CPU 3 via the buffer 17a. In other words, the event information held by the DP-RAM 9 can be read by the CPU 3. Just after that, the enable signal wenb from the WENB generation part 18 is input to the selector 17c, the buffer gate 17b, and the DP-RAM 9. As a result of this, the selector 17c selects the flip flop 17d side and the address signal, when the previous holding event information has been read, is input to the B port BP of the DP-RAM 9 as the address signal Aftadrb and “0” is input from the buffer gate 17b to the B port BP of the DP-RAM 9. As discussed above, the address signal when the event information is read from the DP-RAM 9 is held by the flip flop 17d of the clear circuit 17 for a while and “0” is automatically written to the address area where the event information has been read via the buffer gate 17b of the clear circuit 17, so that the clearing process can be applied to the address area of the DP-RAM 9 where the event information has been read.

FIG. 7 shows an example of the timing chart of the holding circuit 7. More specifically, FIG. 7 shows the address signal adra from the address generation part 10, the receiving data dtaorg input to the OR gate 12a of the holding circuit 12, the data dta as the event information input to the A port AP of the DP-RAM 9, the data dtaq as the holding event information input to the OR gate 12a via the buffer 12c, the enable signal wena, and the write timing of the DP-RAM 9.

[7:00] indicates, as shown in FIG. 3, a case where the event information has 8 bytes D0 through D7 and a case where the data dtaorg, dta, and dtaq are all “0” in the primary state of collection of the event information. For example, in a case where the address area of 0 through 31 in the Cell 0 of the monitored board #1 of FIG. 3, a0 through an of the address signal adra are indicated as a0 through a31. In addition, xx indicates a state where the address bus is opened after the event information is written. Furthermore, arrows to the data dta and dtaq indicate a time order for inputting the data dta written in the DP-RAM 9 to the OR gate 12a via the buffer 12c.

In the primary state, “0000 0000” is written in a storage area of the event information of the DP-RAM 9. In a case where the address signal adra from the address generation part 10 is indicated as a0 and the collected event information is indicated as data dtaorg=“0000 0000”, “0000 0000” that is a logical sum output of the data dtaorg and the data dtaq that is read from the address area of the address signal adra=a0 and the input to the OR gate 12a is written in the address area of the DP-RAM 9 of the address signal adra=a0 by using a down timing of the enable signal wena as the write timing.

In a case where the collected event information corresponding to the address signal adra=a0 is “1000 0001”, “0000 0000” is held in the address area of the address signal adra=a0. Therefore, the data dta of the logical sum of the data dtaorg and data deaq are “1000 0001” and are written in the address area of the DP-RAM 9 of the address signal adra=a0 at the DP-RAM write timing of down of the enable signal wena. In a case where the next collected event information is dtaorg=“0100 0100”, “1000 0001” is written in the address area of the address signal adra=a0. The data dta of the logical sum of the data dtaq=“1000 0001” and the data dtaog=“0100 0100” are “1100 0101” and written in the address area of DP-RAM 9 of the address signal adra=a0. Similarly, in a case where the collected event information dtaorg is “0010 0000”, the data dta=“1110 0101” are written in the address area of the DP-RAM 9 of the address signal adra=a0. That is, when the reading of the event information is not implemented from the CPU 3, the data dta=“1110 0101” are written in the DP-RAM 0 in order as the logical sum output of the collected event information.

FIG. 8 shows an example of a timing chart of the clear circuit 17. More specifically, FIG. 3 shows the address signals adrb=a0, a1, a2, . . . from the CPU 3, the read timing of the CPU 3, the address signal Aftadrb via the flip flop 17d and the selector 17c, the enable signal wenb from the WENB generation part 18, and the write timing when “0” is written in the DP-RAM 3.

The address signal adrb=a0 is input from the CPU 3 to the selector 17c and the flip flop 17d. The up timing of the enable signal from the WENB generation part 18 is the CPU read timing. When the enable signal wenb is “1”, the buffer gate is closed, the selector 17c selects the CPU 3 side, and the address signal adrb=a0 is input to the B port BP of the DP-RAM 9. As a result of this, the holding event information as data dtb (See FIG. 6) is input to the CPU 3 from the address area of the DP-RAM 9 by the address signal adrb. That is, the CPU 3 can read the desirable event information.

When the enable signal wenb is reduced down to “0”, the down timing is the write timing to the DP-RAM 9. The selector 17c selects the flip flop 17d side by the enable signal wenb=“0”. As a result of this, the address signal adrb=a0 held at the flip flop 17d for a while is input to the B port BP of the DP-RAM 9 and the data of “0” are input to the B port BP of the DP-RAM 9 via the buffer gate 17b. As a result of this, “0” is written to the address area of the address signal Aftadrb=a0 at the timing indicating the DP-RAM “0” write timing. That is, the address area where the holding event information has been read by the CPU 3 can be cleared.

Next, the CPU 3 makes the address signal adrb to a1, a2, at the desirable timing. The holding event information is read from the address area of the DP-RA<9 by the address signal adrb at the CPU read timing. A “0” is written in the address area at the DP-RAM “0” write timing so as to make it clear. Therefore, the clearing process of the DP-RAM 9 by the CPU 3 is not necessary so that the processing workload can be reduced.

The present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. For example, a normal memory such as a RAM can be used as the DP-RAM 9.

Thus, according to the above-discussed embodiment of the present invention, it is possible to provide an event holding circuit configured to monitor plural monitored boards, write collected event information, and hold the event information until a processor reads the event information, the event holding circuit including a holding circuit including an OR gate, so that a logical sum output of the collected event information and holding event information is written in a memory where written contents until the last time have been read from an address area of the memory where the event information is to be written.

The memory may have a dual port structure having a port at a side where the event information collected from the monitored board is written and a port at a side where the processor reads the event information; the holding circuit may be provided at the port at the side where the collected event information is written; and the holding circuit includes the OR gate whereby the logical sum output of the collected event information and the holding event information may be written as event information to the address area where the written contents until the last time have been read from the address area where the event information is to be written

The event holding circuit as mentioned above may further include a clear circuit configured to hold address information for a while, the address information being at the time when the processor reads the event information from the memory and configured to, following the address information, perform clearing after the event information is read.

The memory may have a dual port memory structure having a port at a side where the event information collected from the monitored board is written and a port at a side where the processor reads the event information; and a clear circuit may be provided at the side where the event information is read, the clear circuit configured to hold address information for a while, the address information whereby the processor reads the event information and configured to, following the address information, make an address area clear, the address area follows the address information after the event information is read.

The clear circuit may include a write enable signal generation part configured to input to the memory a write enable signal for the memory just after the processor reads the event information from the memory; an address holding part configured to hold the address information whereby the processor reads the event information from the memory, for a while; a selector configured to input address information in the memory, the address information being held at the address holding part by the write enable signal from the write enable signal generation part; and a gate circuit configured to input clear data to the memory by the write enable signal from the write enable signal generation part.

According to the above-mentioned event holding circuit, until the event information indicating statuses of each of the monitored boards as byte correspondence is collected and written in the memory so that the processor reads the event information, the event information of the logical sum of the newly collected event information and the held event information is written as new event information in the memory. In this case, the holding circuit can have a simple logic structure of the OR gate or the like of the byte correspondence of the event information. Hence, compared to the flip flops, increase of the circuit size and cost are not required.

The logical sum output of the held event information and the collected new event information is written in the memory and held by the OR gate. Hence, even if the event information is read by the processor for an interval longer than the event information collecting interval, the event information collected until the processor reads the event information from the memory can be held in the memory by functions of the holding circuit. Hence, it is possible to reduce the processing workload of the processor and prevent the collected event information from being eliminated. In addition, since the clear circuit can be realized by the logic circuit, it is possible to reduce the processing workload of the processor without increasing the cost. Furthermore, in a system where the obstacle information at the monitored board is latched and the obstacle information is sent following the event information collection from the monitoring board so that the latch is lifted, since the obstacle information included in the collected event information is held in the memory, it is possible to send the notice to the processor.

This patent application is based on Japanese Priority Patent Application No. 2006-269073 filed on Sep. 29, 2006, the entire contents of which are hereby incorporated by reference.

Claims

1. An event holding circuit configured to monitor plural monitored boards, write collected event information, and hold the event information until a processor reads the event information, the event holding circuit comprising: a holding circuit including an OR gate, so that a logical sum output of the collected event information and holding event information is written in a memory where written contents until the last time have been read from an address area of the memory where the event information is to be written.

2. The event holding circuit as claimed in claim 1, wherein the memory has a dual port structure having a port at a side where the event information collected from the monitored board is written and a port at a side where the processor reads the event information;the holding circuit is provided at the port at the side where the collected event information is written; andthe holding circuit includes the OR gate whereby the logical sum output of the collected event information and the holding event information is written as event information to the address area where the written contents until the last time have been read from the address area where the event information is to be written

3. The event holding circuit as claimed in claim 1, further comprising: a clear circuit configured to hold address information for a while, the address information being at the time when the processor reads the event information from the memory and configured to, following the address information, perform clearing after the event information is read.

4. The event holding circuit as claimed in claim 1, wherein the memory has a dual port memory structure having a port at a side where the event information collected from the monitored board is written and a port at a side where the processor reads the event information; anda clear circuit is provided at the side where the event information is read, the clear circuit configured to hold address information for a while, the address information whereby the processor reads the event information and configured to, following the address information, make an address area clear, the address area follows the address information after the event information is read.

5. The event holding circuit as claimed in claim 3, wherein the clear circuit includes:a write enable signal generation part configured to input to the memory a write enable signal for the memory just after the processor reads the event information from the memory;an address holding part configured to hold the address information whereby the processor reads the event information from the memory, for a while;a selector configured to input address information in the memory, the address information being held at the address holding part by the write enable signal from the write enable signal generation part; anda gate circuit configured to input clear data to the memory by the write enable signal from the write enable signal generation part.

6. The event holding circuit as claimed in claim 4, wherein the clear circuit includes:a write enable signal generation part configured to input to the memory a write enable signal for the memory just after the processor reads the event information from the memory;an address holding part configured to hold the address information whereby the processor reads the event information from the memory, for a while;a selector configured to input address information in the memory, the address information being held at the address holding part by the write enable signal from the write enable signal generation part; anda gate circuit configured to input clear data to the memory by the write enable signal from the write enable signal generation part.