Instruction Issue Logic for High-Performance, Interruptable, Multiple Functional Unit, Pipelined Computers Sohi IEEE Trans on Comp vol. 39 No. 3 Mar. 1990 pp. 349-359. |
Hwu & Patt, "Checkpoint Repair for High Performance Out-of-Order Execution Machines" Dec. 1987 IEEE Transactions on Computers vol. C36 pp. 1496-1514. |
Hwu & Patt "Checkpoint Repair for Out-of-Order Execution Machines" 1987 pp. 18-26. |
"A Multiple Out-of-Order Instruction Issuing System for Superscalar Processors" Harry Dwyer III Aug. 1991 Chapter 7. |
"Checkpoint Repair for High-Performance Out-of-Order Execution Machines", IEEE Transactions on Computers, (C6), Wen-Mei W. Hwu and Yale N. Patt, Dec. 1987, pp. 1496-1514. |
Sohi, et al.; Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors; Computer Sciences Dept., University of Wisconsin-Madison, ACM 1987; pp. 27-34. |
Weiss, et al.; Instruction Issue Logic in Pipelined Supercomputers; IEEE Transactions on Computers, vol. c-33, No. 11, Nov. 1984; pp. 1013-1022. |
Robert M. Keller; Look-Ahead Processors; Computing Surveys, vol.7, No. 4, Dec. 1975; pp. 177-195. |
Riseman, et al.; The Inhibition of Potential Parallelism by Conditonal Jumps; IEEE Transactions of Computers, Dec. 1972; pp. 1405-1411. |
Tjaden, et al.; Detection and Parallel Execution of Independent Instructions; IEEE Transactions on Computers, vol. C-19, No. 10, Oct. 1970; pp. 889-895. |
Foster, et al.; Percolation of Code to Enhance Parallel Dispatching and Execution; IEEE Transactions on Computers, Dec. 1972; pp. 1411-1415. |
James E. Smith; Implementation of Precise Interrupts in Pipelined Processors; IEEE, 1985; pp. 36-44. |
Hwu, et al.; HPSm2: A Redefined Single-ship Microengine: System Sciences; The Computer Society of the IEEE 1988; pp. 30-39. |
Hwu, et al.; Exploiting Horizontal and Vertical Concurrency via the HPSm Microprocessor; ACM 089791-250-0/87/0012/0154 1987; pp. 154-161. |
Hwu, et al.; Design Choices for the PHSm Microprocessor Chip; Computer Science Sivision, University of California, Berkeley; Proc. of the 20th Annual Hawaii International Conf. on System Sciences, Kona, Jan. 1987; (seven pages). |
Hwu, et al.; HPSm, a High Performance Retricted Data Flow Architecture Having Minimal Functionality; IEEpp. 297-306. |
Gharachorloo, et al.; Detecting Violations of Sequential Consistency; to appear in SPAA '91; pp. 1-11. |
Gharachorloo, et al.; Two Techniques to Enhance the Performance of Memory Consistency Models; To appear in ICPP '91; pp. |
R.M. Tomasulo; An Efficient Algorithm for Exploiting Multiple Arithmetic Units; IBM Technical Journal, vol. 11, Jan. 1967 pp. 25-33. |
V. Popescu, et al., "The Metaflow Architecture", IEEE Micro, 1991, pp. 10-13, and 63-73. |
Mike Johnson, "Superscalar Microprocessor Design", Prentice Hall, 1991. |