Patent Application
20190310856
The present disclosure relates to executing instructions, and more specifically, but not exclusively, to executing instructions based on a shared physical register.
According to embodiments described herein, a system for executing instructions can include a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. The processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
In embodiments, a method for executing instructions can include detecting a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. The method can also include executing the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the method can include executing additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
In yet another embodiment, a computer program product for executing instructions can include a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se. The program instructions can be executable by a processor to cause the processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. The program instructions can also be executable by a processor to cause the processor to execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Additionally, the program instructions can be executable by a processor to cause the processor to execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:
Central processing units (CPUs) can include any suitable number of general purpose registers that are used to execute instructions. For example, the general purpose registers can store retrieved data from any number of cache devices or memory devices. In some examples, the general purpose registers can also store the result of an operation. For example, the result of a mathematical operation, logical operation, and the like, can be stored in a general purpose register. In some embodiments, CPUs can execute instructions out of the order in which the instructions are received. For example, the CPU can read and decode a received instruction by mapping logical registers referenced in the instructions to physical general purpose registers. In some embodiments, CPUs can enable a physical register to release a result from a previously executed instruction.
In some embodiments, a device can assign multiple instructions to a single shared physical register, which can enable the execution of additional out of order instructions. For example, the device can detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. A destructive instruction, as referred to herein, can include any instruction that is dependent on a previously executed instruction or supports a dependent instruction to be executed. For example, a destructive instruction can include an instruction that calculates a result which is used in subsequent instructions. Alternatively, a destructive instruction can include an instruction that calculates a value based on a source value previously calculated in another instruction. In some embodiments, the device can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. For example, a first instruction can store a result of a calculation in the shared physical register and a second instruction can used the result in calculating a second result that overrides the result stored in the shared physical register. Furthermore, the device can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
Accordingly, the techniques described herein can reduce the number of physical registers used to execute instructions. Therefore, the techniques described herein can prevent adding physical registers to a CPU, which would consume additional power and space. The techniques also enable executing a larger number of out of order instructions.
With reference now to
The computing device 100 may include a processor 102 that is adapted to execute stored instructions, a memory device 104 to provide temporary memory space for operations of said instructions during operation. The processor can be a single-core processor, multi-core processor, computing cluster, or any number of other configurations. The memory device 140 can include random access memory (RAM), read only memory, flash memory, or any other suitable memory systems.
The processor 102 may be connected through a system interconnect 106 (e.g., PCI®, PCI-Express®, etc.) to an input/output (I/O) device interface 108 adapted to connect the computing device 100 to one or more I/O devices 110. The I/O devices 110 may include, for example, a keyboard and a pointing device, wherein the pointing device may include a touchpad or a touchscreen, among others. The I/O devices 110 may be built-in components of the computing device 100, or may be devices that are externally connected to the computing device 100.
The processor 102 may also be linked through the system interconnect 106 to a display interface 112 adapted to connect the computing device 100 to a display device 114. The display device 114 may include a display screen that is a built-in component of the computing device 100. The display device 114 may also include a computer monitor, television, or projector, among others, that is externally connected to the computing device 100. In addition, a network interface controller (NIC) 116 may be adapted to connect the computing device 100 through the system interconnect 106 to the network 118. In some embodiments, the NIC 116 can transmit data using any suitable interface or protocol, such as the internet small computer system interface, among others. The network 118 may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. A remote server 120 may connect to the computing device 100 through the network 118.
The processor 102 may also be linked through the system interconnect 106 to a storage device 122 that can include a hard drive, an optical drive, a USB flash drive, an array of drives, or any combinations thereof. In some examples, the storage device 122 may include data used to execute instructions by the processor 102. In some examples, the processor 102 can include a destructive instruction manager 124, an instruction execution pipe 126, and an instruction execution pipe 126. In some embodiments, the destructive instruction manager 124 can detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In some embodiments, the instruction execution pipe 126 can execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. In some embodiments, the instruction execution pipe 126 can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
It is to be understood that the block diagram of
At block 202, the destructive instruction manager 124 can detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In some embodiments, a destructive instruction, as referred to herein, can include any instruction that is dependent on a previously executed instruction or supports a dependent instruction to be executed. For example, a destructive instruction can include an instruction that calculates a result which is used in subsequent instructions. Alternatively, a destructive instruction can include an instruction that calculates a value based on a source value previously calculated in another instruction. Accordingly, a pair of destructive instructions can include two instructions in which a first instruction corresponds to a calculation that depends on a value set by a previous second operation. For example, a pair of destructive instructions can include a first instruction that sets a value of a logical register R1 and the second instruction can include a mathematical operation that depends on the logical register R1 value determined by the first instruction. For example, the second instruction can include a mathematical operation setting the value of R1 based on an addition of R1 and any suitable additional value. Accordingly, the second instruction and the first instruction assign a value to a shared target logical register, e.g. R1. In some embodiments, the pair of destructive instructions comprise a first instruction and a second instruction, wherein the second instruction depends on the value stored in the shared physical register by the first instruction. In some examples, the first instruction and the second instruction comprise mathematical operations.
In some embodiments, the additional value is to be loaded into a physical register prior to execution of the second calculation. For example, the additional value may not be speculative, so the destructive instruction manager 124 can verify that the additional value is loaded from memory into a physical register prior to execution of the second instruction. Therefore, the second instruction comprises non-speculative source values stored in physical source registers. By contrast, speculative values loaded into physical registers correspond to memory addresses that have not been analyzed to determine if the speculative values are the actual requested values.
Additionally, in some embodiments, the predetermined number of instructions is limited based at least on a number of physical registers. In some embodiments, the pair of destructive instructions are consecutive instructions. In some examples, the pair of destructive instructions are separated by at least one non-destructive instruction. In some examples, the predetermined number of instructions is not based only on the number of physical registers, but also on the size of the instruction queue (e.g. hardware that stores instructions waiting to be executed), the number of threads (e.g. how many processes are running in parallel), and the like.
At block 204, the instruction execution pipe 126 can execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. For example, the instruction execution pipe 126 may be executed by a processor that supports out of order instruction execution. For example, the processor may execute a group of instructions out of the order in which the instructions were received and store a result for each instruction in a separate physical register. Accordingly, a processor may in some instances store a result of a pair of destructive instructions in separate physical registers. For example, a processor may store a result from a first instruction in a first physical register and a result from a second instruction that depends from the first instruction in a second physical register. The instruction execution pipe 126 can modify the processor instruction set architecture to store the result from a first instruction and a second instruction in a pair of destructive instructions in the same shared physical register. Accordingly, in some embodiments, the instruction execution pipe 126 can modify a physical register assignment of the second instruction to store the result of the second instruction in the shared physical register, wherein the shared physical register previously stored the result of the first instruction.
At block 206, the instruction execution pipe 126 can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register. For example, the instruction execution pipe 126 can cause a processor to execute additional instructions using the value stored in the shared physical register by the second instruction of a pair of destructive instructions. Accordingly, the instruction execution pipe 126 enables a processor to execute additional instructions without determining whether to use a stored value from a physical register corresponding to the first destructive instruction or a separate physical register corresponding to the second destructive instruction. Rather, additional instructions are executed based on the value stored in the shared physical register.
The process flow diagram of
In some embodiments, the instruction 304 can include two source values stored in logical register R1312 and R5314 and generate a result stored in logical register R4316. The instruction 306 can include two source values or operands stored in logical register R6318 and logical register R7320. The result of instruction 306 can be stored in logical register R1312.
Accordingly, instruction 306 is independent of the previous instructions 302 and 304. If instruction 304 is waiting for data from memory for logical register R5314, instruction 306 can be executed before instruction 304. In this example, the order of execution will be instruction 302, instruction 306, and instruction 304. However, instruction 304 will get the wrong value of logical register R1312 because instruction 304 will read the value that instruction 306 stored in logical register R1312 rather than the value that instruction 302 stored in logical register R1312. To prevent such an issue, a processor can implement register mapping, which maps each instance of a logical register to a separate physical register. For example, the first instance of logical register R1312 in instruction 302 can be mapped to a first physical register, which instruction 302 will access. However, the instruction 306 will store a result for the instance of logical register R1312 in a separate physical register, such as physical register 2, or any physical register distinct from the first physical register. Accordingly, if instruction 306 is executed before instruction 304, the result of instruction 306 stored in an instance of logical register R1312 will not alter the result of instruction 304. Therefore, the processor can execute instruction 306 in any suitable order because instruction 306 is not dependent on instruction 302 or 304. Accordingly, the processor can execute instruction 306 before executing instruction 302, before executing instruction 304, or after executing instruction 304.
In some embodiments, the instruction 324 can include two source values stored in logical registers R4334 and R5336 and generate a result stored in logical register R6338. The processor can execute instruction 324 in any suitable order because instruction 324 is not dependent on instruction 322 or 326. Accordingly, the processor can execute instruction 324 before executing instruction 322, before executing instruction 326, or after executing instruction 326.
In some examples, the instruction 326 can include a mathematical or logical calculation that is dependent on instruction 322. For example, the instruction 326 can perform a calculation based on logical register R1332 and an additional value stored in a logical register R5336. The processor can store the result of the calculation of instruction 326 in logical register R1332 rather than storing the result in a separate physical register. For example, the processor can assign a value stored in local register R1332 on the left side of instruction 326 to a different physical register than the local register R1 of instruction 322. Therefore, two local registers can be used to store a value for a logical register R1 used in separate instructions. The use of two local registers is redundant and wasteful because instruction 326 is dependent on logical register R1332 (the logical register appearing on the right hand side of instruction 326). Therefore, instruction 326 will be executed after instruction 322 due to the dependency. In addition, the instruction 324 is independent of logical register R1, so swapping the order of instruction 324 and 326 will not alter the result, even if the processor is to map both logical register R1 of instruction 322 and logical register R1 of instruction 326 to the same physical register. Thus, the present techniques add circuitry to a processor that determines if a register mapper can allocate a shared physical register for executing an instruction based in part on the dependency between the instructions being executed.
The sets of instructions 300A and 300B of
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
Referring now to
Furthermore, the tangible, non-transitory, computer-readable medium 400 may include code to direct the processor 402 to perform the operations of the current method. For example, a destructive instruction manager 406 can detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In some embodiments, an instruction execution pipe 408 can execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. In some embodiments, the instruction execution pipe 408 can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
It is to be understood that any number of additional software components not shown in
Referring now to
Referring now to
Hardware and software layer 600 includes hardware and software components. Examples of hardware components include mainframes, in one example IBM® zSeries® systems; RISC (Reduced Instruction Set Computer) architecture based servers, in one example IBM pSeries® systems; IBM xSeries® systems; IBM BladeCenter® systems; storage devices; networks and networking components. Examples of software components include network application server software, in one example IBM WebSphere® application server software; and database software, in one example IBM DB2® database software. (IBM, zSeries, pSeries, xSeries, BladeCenter, WebSphere, and DB2 are trademarks of International Business Machines Corporation registered in many jurisdictions worldwide).
Virtualization layer 602 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers; virtual storage; virtual networks, including virtual private networks; virtual applications and operating systems; and virtual clients. In one example, management layer 604 may provide the functions described below. Resource provisioning provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources may comprise application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal provides access to the cloud computing environment for consumers and system administrators. Service level management provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.
Workloads layer 606 provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation; software development and lifecycle management; virtual classroom education delivery; data analytics processing; transaction processing; and executing instructions based on a shared physical register.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
