Claims
- 1. A network device, comprising:
a switching fabric; and a plurality of network processors connected to communicate via the switching fabric, the network processors including:
a plurality of input register files, a plurality of output register files, and an execution unit configured to perform a plurality of protocol-processing functions on data received via the input register files and output the data via the output register files, the execution unit comprising:
a plurality of specialized registers configured to store the data during performance of the protocol-processing functions, and a memory that performs a plurality of functions depending on which of the protocol-processing functions is performed by the execution unit.
- 2. The network device of claim 1, wherein the memory includes:
a plurality of fast memories.
- 3. The network device of claim 2, wherein the fast memories operate together to form at least one of:
a set of high-bandwidth scratchpad memories, a set of control memories, and a set of byte-indexed table memories.
- 4. The network device of claim 1, wherein the protocol-processing functions include at least two of stuffing and unstuffing, bit movement, space/time byte switching, table lookup, and cryptography primitive operations.
- 5. The network device of claim 4, wherein the stuffing and unstuffing operations include High-Level Data Link Control (HDLC) bit-stuffing, HDLC bit-unstuffing, Packet-Over-SONET (POS) byte-stuffing, and POS byte-unstuffing.
- 6. The network device of claim 4, wherein the bit movement operations include any combination of arithmetic or logical shift or rotate operations, extraction or insertion of one or more fields of the data, clearing of one or more sub-fields of the data, sign-extension of one or more of the sub-fields of the data, and insertion or deletion of one or more bits or bytes of the data.
- 7. The network device of claim 4, wherein the space/time byte switching operations include SONET channel multiplexing and demultiplexing.
- 8. The network device of claim 4, wherein the table lookup operations include parallel byte-mapping operations.
- 9. The network device of claim 4, wherein the cryptography primitive operations include round calculations for an Advanced Encryption Standard encryption or decryption.
- 10. The network device of claim 1, wherein the specialized registers include:
one or more input registers, at least one control register, and one or more output registers.
- 11. The network device of claim 10, further comprising:
a crossbar connecting the one or more input registers to the one or more output registers.
- 12. The network device of claim 10, further comprising:
a plurality of multiplexers connected to provide data to the one or more input registers and the one or more output registers.
- 13. An execution unit within a network processor that performs a plurality of protocol-processing functions, comprising:
a plurality of specialized registers configured to store data during performance of the protocol-processing functions, the specialized registers including:
one or more input registers, at least one control register, and one or more output registers; and a memory system that includes a plurality memories configured to operate together to facilitate performance of the protocol-processing functions by the execution unit.
- 14. The execution unit of claim 13, wherein the memories operate together to form at least one of:
a set of high-bandwidth scratchpad memories, a set of control memories, and a set of byte-indexed table memories.
- 15. The execution unit of claim 13, wherein the protocol-processing functions include at least two of stuffing and unstuffing, bit movement, space/time byte switching, table lookup, and cryptography primitive operations.
- 16. The execution unit of claim 15, wherein the stuffing and unstuffing operations include High-Level Data Link Control (HDLC) bit-stuffing, HDLC bit-unstuffing, Packet-Over-SONET (POS) byte-stuffing, and POS byte-unstuffing.
- 17. The execution unit of claim 15, wherein the bit movement operations include any combination of arithmetic or logical shift or rotate operations, extraction or insertion of one or more fields of the data, clearing of one or more sub-fields of the data, sign-extension of one or more of the sub-fields of the data, and insertion or deletion of one or more bits or bytes of the data.
- 18. The execution unit of claim 15, wherein the space/time byte switching operations include SONET channel multiplexing and demultiplexing.
- 19. The execution unit of claim 15, wherein the table lookup operations include parallel byte-mapping operations.
- 20. The execution unit of claim 15, wherein the cryptography primitive operations include round calculations for an Advanced Encryption Standard encryption or decryption.
- 21. The execution unit of claim 13, further comprising:
a crossbar connecting the one or more input registers to the one or more output registers.
- 22. The execution unit of claim 13, further comprising:
a plurality of multiplexers connected to provide data to the one or more input registers and the one or more output registers.
- 23. The execution unit of claim 13, wherein the memories include 16 64×128 memories.
- 24. A method for performing bit movement functions by an execution unit within a network processor, the execution unit including a plurality of specialized registers and a crossbar element, the method comprising:
loading a first operand into a first one of the registers; loading a second operand into a second one of the registers; providing the first and second operands to the crossbar element; writing an output of the crossbar element to third and fourth ones of the registers; storing contents of the fourth one of the registers to the second one of the registers; and outputting contents of the third and fourth ones of the registers.
- 25. The method of claim 24, wherein the settings of the crossbar element are controlled by a control memory.
- 26. A method for performing a table lookup function by an execution unit within a network processor, the execution unit including a plurality of specialized registers and a memory system that includes a plurality of memories, the method comprising:
loading an operand into a first one of the registers; receiving an address of a table stored in one or more of the memories; using the operand to access a value in the table; writing the value from the table into a second one of the registers; and outputting contents of the second one of the registers.
- 27. A method for performing time-space switching by an execution unit within a network processor, the execution unit including a plurality of specialized registers and a memory system that includes a plurality of memories, the method comprising:
(a) writing input data into a first one of the registers; (b) storing a first input control word in a second one of the registers; (c) storing a second input control word in a third one of the registers; (d) writing the input data into the memories based on the first and second input control words; (e) storing a first output control word in the second one of the registers; (f) storing a second output control word in the third one of the registers; and (g) outputting the input data from the memories based on the first and second output control words.
- 28. The method of claim 27, wherein acts (b) through (g) are performed in a pipelined fashion.
- 29. The method of claim 27, wherein the writing the input data to the memories includes:
storing bytes of the input data in different ones of the memories based on the first and second input control words.
- 30. The method of claim 29, wherein the outputting the input data from the memories includes:
reading the bytes of the input data from the different ones of the memories based on the first and second output control words.
RELATED APPLICATION
[0001] This application claims priority under 35 U.S.C. §119 based on U.S. Provisional Application No. 60/327,094, filed Oct. 4, 2001, the disclosure of which is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60327094 |
Oct 2001 |
US |