BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computer-aided electronic circuit simulation, and more particularly, to a method of extracting semiconductor device model parameters for use in integrated circuit simulation.
2. Description of Related Art
Computer aids for electronic circuit designers are becoming more prevalent and popular in the electronic industry. This move toward electronic circuit simulation was prompted by the increase in both complexity and size of circuits. As circuits have become more complex, traditional breadboard methods have become burdensome and overly complicated. With increased computing power and efficiency, electronic circuit simulation is now standard in the industry. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as, SPICE2 or SPICE3, also developed at UC Berkeley; HSPICE, developed by Meta-software and now owned by Avant!; PSPICE, developed by Micro-Sim; and SPECTRE, developed by Cadence. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators.
SPICE is a program widely used to simulate the performance of analog electronic systems and mixed mode analog and digital systems. SPICE solves sets of non-linear differential equations in the frequency domain, steady state and time domain and can simulate the behavior of transistor and gate designs. In SPICE, any circuit is handled in a node/element fashion; it is a collection of various elements (resistors, capacitors, etc.). These elements are then connected at nodes. Thus, each element must be modeled to create the entire circuit. SPICE has built in models for semiconductor devices, and is set up so that the user need only specify model parameter values.
An electronic circuit may contain any variety of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), and metal-on-silicon field effect transistors (MOSFET), etc. A SPICE circuit simulator makes use of built-in or plug-in models for semiconductor device elements such as diodes, BJTs, JFETs, and MOSFETs. If model parameter data is available, more sophisticated models can be invoked. Otherwise, a simpler model for each of these devices is used by default.
A model for a device mathematically represents the device characteristics under various bias conditions. For example, for a MOSFET device model, in DC and AC analysis, the inputs of the device model are the drain-to-source, gate-to-source, bulk-to-source voltages, and the device temperature. The outputs are the various terminal currents. A device model typically includes model equations and a set of model parameters. The model parameters, along with the model equations in the device model, directly affect the final outcome of the terminal currents. In order to represent actual device performance, a successful device model is tied to the actual fabrication process used to manufacture the device represented. This connection is represented by the model parameters, which are dependent on the fabrication process used to manufacture the device.
SPICE has a variety of preset models. However, in modern device models, such as BSIM (Berkeley Short-Channel IGFET Model) and its derivatives, BSIM3, BSIM4, and BSIMPD (Berkeley Short-Channel IGFET Model Partial Depletion), all developed at UC Berkeley, only a few of the model parameters can be directly measured from actual devices. The rest of the model parameters are extracted using nonlinear equations with complex extraction methods. See Daniel Foty, “MOSFET Modeling with Spice—Principles and Practice,” Prentice Hall PTR, 1997.
Since the sets of equations utilized in a modern semiconductor device model are complex with numerous unknowns, there is a need to extract the model parameters in the equations in an efficient and accurate manner so that using the extracted parameters, the model equations will closely emulate the actual process.
SUMMARY OF THE INVENTION
The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIM4 model. The device model parameters for the device model includes a plurality of base parameters, DC model parameters, temperature dependent related parameters, and AC parameters. The method includes steps for extracting the DC model parameters, such of Vth related parameters, Igb related parameters, Igidl related parameters, Igd and Igs related parameter, Leff, Rd and Rs related parameters, mobility and Weff related parameters, Vth geometry related parameters, sub-threshold region related parameters, drain induced barrier lower related parameters; Idsat related parameters, and additional DC related parameters, based on the terminal current data corresponding to various bias conditions measured from a set of test devices.
The present invention also includes a method for extracting device model parameters including the steps of extracting a portion of the DC model parameters based on the terminal current data, modifying the terminal current data based on the extracted portion of the DC model parameters, and extracting a second portion of the DC model parameters based on the modified terminal current data.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a system according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a modeling process in accordance with an embodiment of the present invention;
FIG. 3A is a block diagram of a model definition input file in accordance with an embodiment of the present invention;
FIG. 3B is a block diagram of an object definition input file in accordance with an embodiment of the present invention;
FIG. 4 is a diagrammatic cross sectional view of a MOSFET device for which model parameters are extracted in accordance with an embodiment of the present invention;
FIG. 5 is a graph illustrating sizes of test devices used to obtain experimental data for model parameter extraction in accordance with an embodiment of the present invention;
FIG. 6 is a graph illustrating sizes of test devices used to obtain experimental data for model parameter extraction in accordance with an alternative embodiment of the present invention;
FIGS. 7A-7D are examples of current-voltage (I-V) curves representing some of the terminal current data for the test devices;
FIG. 8 is a flow chart illustrating in further detail a parameter extraction process in accordance with an embodiment of the present invention; and
FIG. 9 is a flow chart illustrating in further detail a DC parameter extraction process in accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
As shown in FIG. 1, system 100, according to one embodiment of the invention, comprises a central processing unit (CPU) 102, which includes a RAM, and a disk memory 110 coupled to the CPU 102 through a bus 108. The system 100 further comprises a set of input/output (I/O) devices 106, such as a keypad, a mouse, and a display device, also coupled to the CPU 102 through the bus 108. The system 100 may further include an input port 104 for receiving data from a measurement device (not shown), as explained in more detail below. The system 100 may also include other devices 122. An example of system 100 is a Pentium 233 PC/Compatible computer having RAM larger than 64 MB and a hard disk larger than 1 GB.
Memory 110 has computer readable memory spaces such as database 114 that stores data, memory space 112 that stores operating system 112 such as Windows 95/98/NT4.0/2000, which has instructions for communicating, processing, accessing, storing and searching data, and memory space 116 that stores program instructions (software) for carrying out the method of the present invention. Memory space 116 may be further subdivided as appropriate, for example to include memory portions 118 and 120 for storing modules and plug-in models, respectively, of the software.
A set of model parameters for a semiconductor device is often referred to as a model card for the device. Together with the model equations, the model card is used by a circuit simulator to emulate the behavior of the semiconductor device in an integrated circuit. A model card may be determined by process 200 as shown in FIG. 2. Process 200 begins by loading 210 the input files into the RAM of the CPU 102. The input files may include a model definition file and an object definition file. The object definition file provides information of the object (device) to be simulated. The model definition file provides information associated with the device model for modeling the behavior of the object. These files are discussed in further detail below in conjunction with FIGS. 3A and 3B.
Next, the measurement data is loaded 220 from database 114. The measurement data includes physical measurements from a set of test devices, as will be explained in more detail below. Once the data has been loaded, the next step is extraction 230 of the model parameters. The parameter extraction step 230 is discussed in detail in connection with FIGS. 8, and 9 below.
After the parameters are extracted, binning 240 may be performed. Binning is an optional step depending on whether the device model is binnable or not. The next step is verification 250. Verification checks the quality of the extracted model parameters. Once verified, the extracted parameters are output 260 as model card, an error report is generated 270, and the process 200 is then complete. More detailed discussion about the binning step 240 and verification step 250 can be found in the BSIMPro+User Manual—Basic Operation, by Celestry Design Technologies, released in September, 2001, which is incorporated by reference in its entirety herein.
Referring to FIG. 3A, model definition file 300A comprises a general model information field 310, a parameter definition field 320, an intermediate variable definition field 330, and an operation point definition field 340. The general model information field 310 includes general information about the device model, such as model name, model version, compatible circuit simulators, model type and binning information. The parameter definition field 320 defines the parameters in the model. As an example, a list of the model parameters in the BSIM4 model are provided in Appendix A. For each parameter, the model definition file specifies information associated with the parameter, such as parameter name, default value, parameter unit, data type, and optimization information. The operation point definition section 340 defines operation point or output variables, such as device terminal currents, threshold voltage, etc., used by the model.
Referring to FIG. 3B, object definition file 300B defines object related information, including input variables 350, output variables 360, instance variables 370, object and node information 380. Input variables 350 and output variables 360 are associated with the inputs and outputs, respectively, of the device in an integrated circuit. The instance variables 370 are associated with the geometric characteristics of the device to be modeled. The object node information 380 is the information regarding the nodes or terminals of the device to be modeled.
Process 200 can be used to generate model cards for models describing semiconductor devices such as BJTs, JFETs, and MOSFETs, etc. Discussions about the use of some of these models can be found in the BSIMPro+User Manual—Device Modeling Guide, by Celestry Design Technologies, released in September, 2001, which is incorporated by reference in its entirety herein. As an example, the BSIM4 model, which was developed by UC Berkeley to model MOSFET devices, is used here to further describe the parameter extraction step 230 of the process 200. The model equations for the BSIM4 model are provided in Appendix B. More detailed discussion about the BSIM4 model can be found in the BSIM4.2.0 MOSFET Model Users' Manual by the Department of Electrical Engineering and Computer Sciences, UC Berkeley, Copyright 2001, which is incorporated by reference in its entirety herein.
Preferred embodiments of the present invention, thus may be further understood by reference to an exemplary parameter extraction process for a MOSFET device. As shown in FIG. 4, a MOSFET device 400 includes a source 430 and a drain 450 formed in a substrate 440. The MOSFET also includes a gate 410 over the substrate 440 and is separated from the substrate 440 by a thin layer of gate oxide 420.
The MOSFET as described can be considered a four terminal (node) device. The four terminals are the gate terminal (node g), the source terminal (node s), the drain terminal (node d), and the substrate or body terminal (node b). Nodes g, s, b, and d, can be connected to different voltage sources.
For ease of further discussion, Table I below lists the symbols corresponding to the physical variables associated with the operation of MOSFET device 400.
TABLE I
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Cbd -body to drain capacitance
CbS -body to source capacitance
Id -current through drain (d) node
Idgidl -gate induced leakage current at the drain
Ids -current flowing from source to drain
Idsat -drain saturation current
Ib -current through substrate node
Igb -gate oxide tunneling current to substrate
Igs -current flowing from gate to source
Igd -current flowing from gate to drain
Igc -current flowing from gate to channel
Isub -impact ionization current
Is -current through source (s) node
Lgisl -gate induced source leakage current at the source
Ldrawn -drawn channel length
Leff -effective channel length
Rd -drain resistance
Rs -source resistance
Rds -drain/source resistance
Rout -output resistance
Vbs -voltage between node b and node s
Vd -drain voltage
VDD -maximum operating DC voltage
Vds -voltage between node d and node s
Vb -substrate voltage
Vg -gate voltage
Vgs -voltage between node g and node s
Vs -source voltage
Vth -threshold voltage
Wdrawn -drawn channel width
Weff -effective channel width
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In order to model the behavior of the MOSFET device 400 using the BSIM4 model, experimental data are used to extract model parameters associated with the model. These experimental data include terminal current data and capacitance data measured in test devices under various bias conditions. In one embodiment of the present invention, the measurement is done using a conventional semiconductor device measurement tool that is coupled to system 100 through input port 104. The measured data are thus organized by CPU 102 and stored in database 114. The test devices are typically manufactured using the same or similar process technologies for fabricating the MOSFET device. In one embodiment of the present invention, a set of test devices having different device sizes, meaning different channel widths and channel lengths are used for the measurement. The device size requirement can vary with different applications. Ideally, as shown in FIG. 5, the set of devices include:
- one largest device, meaning the device with the longest drawn channel length and widest drawn channel width that is available, as represented by dot 502;
- one smallest device, meaning the device with the shortest drawn channel length and smallest drawn channel width that is available, as represented by dot 516;
- one device with the smallest drawn channel width and longest drawn channel length, as represented by dot 510;
- one device with the widest drawn channel length and shortest drawn channel length, as represented by dot 520;
- three devices having the widest drawn channel width and different drawn channel lengths, as represented by dots 504, 506, and 508;
- two devices with the shortest drawn channel length and different drawn channel widths, as represented by dots 512 and 514;
- two devices with the longest drawn channel length and different drawn channel widths, as represented by dots 522 and 524;
- (optionally) up to three devices with smallest drawn channel width and different drawn channel lengths, as represented by dots 532, 534, and 536; and
- (optionally) up to three devices with medium drawn channel width (about halfway between the widest and smallest drawn channel width) and different drawn channel lengths, as represented by dots 538, 540, and 542.
If in practice, it is difficult to obtain measurements for all of the above required devices sizes, a smaller set of different sized devices can be used. For example, the different device sizes shown in FIG. 6 are sufficient according to an alternative embodiment of the present invention. The test devices as shown in FIG. 6 include:
- one largest device, meaning the device with the longest drawn channel length and widest drawn channel width, as represented by dot 502;
- one smallest device, meaning the device with the shortest drawn channel length and smallest drawn channel width, as represented by dot 516;
- (optional) one device with the smallest drawn channel width and longest drawn channel length, as represented by dot 510;
- one device with the widest drawn channel width and shortest drawn channel length, as represented by dot 520;
- one device and two optional devices having the widest drawn channel width and different drawn channel lengths, as represented by dots 504 (optional), 506 (optional), and 508, respectively;
- (optional) two devices with the shortest drawn channel length and different drawn channel widths, as represented by dots 512 and 514.
For each test device, terminal currents are measured under different terminal bias conditions. These terminal current data are put together as I-V curves representing the I-V characteristics of the test device. In one embodiment of the present invention, for each test device, the following I-V curves are obtained:
- 1. Linear region Id vs. Vgs curves for a set of Vb values. These curves are obtained by grounding the s node, setting Vd to a low value, such as 0.05V, and for each of the set of Vb values, measuring Id while sweeping Vg in step values across a range such as from 0 to VDD. (−VDD for NMOS and VDD for PMOS).
- 2. Saturation region Id vs. Vgs curves for a set of Vb values. These curves are obtained by grounding the s node, setting Vd to a high value, such as VDD, and for each of the set of Vb values, measuring Id while sweeping Vg in step values across a range such as from 0 to VDD. (−VDD for NMOS and VDD for PMOS).
- 3. Saturation region Id VS Vds curves for a set of Vg values. These curves are obtained by grounding the s node, setting Vb to 0 and for each set of Vg values, measuring Id while sweeping Vd in step values across a range such as Vth+0.02 to VDD.
- 4. Linear region Id vs Vds curves for a set of Vg values with substrate biased. These curves are obtained by grounding the s node, setting Vb to −VDD and for each set of Vg values, measuring Id while sweeping Vd in step values across a range such as Vth+0.02 to VDD.
- 5. Ib vs. Vgs curves for different Vd values, obtained by grounding the s and b nodes, and for each of the set of Vd values, measuring Ib while sweeping Vg in step values across a range such as from 0 to VDD.
- 6. Ig vs. Vbs curves obtained by grounding d, g, and s nodes, measuring Ig while sweeping Vb in step values across a range such as from −VDD to 0.7.
- 7. Ig/Id/Is vs. Vgs curves for different Vd values, obtained by grounding s and b nodes, and for each of a set of Vd values sweeping Vg in step values across a range such as from 0 to VDD.
- 8. Is vs. Vgd curves for different Vb and Vs values, obtained by grounding d node, and for each combination of Vb, and Vs values, measuring Is while sweeping Vg in step values across a range such as from 0 to −VDD.
As examples, FIG. 7A shows a set of linear region Id vs. Vgs curves for different Vbs values, FIG. 7B shows a set of saturation region Id vs. Vds curves for different Vgs values, FIG. 7C shows a set of Ig vs. Vgs curves for different Vds values; and FIG. 7D shows a set of Ig vs. Vgs curves for different Vbd values.
In addition to the terminal current data, for each test device, capacitance data are also collected from the test devices under various bias conditions. The capacitance data can be put together into capacitance-current (C-V) curves. In one embodiment of the present invention, the following C-V curves are obtained:
- 1. Cbs VS. Vbs curve obtained by grounding s node, setting Id to zero, or to very small values, and measuring Cbs while sweeping Vb in step values across a range such as from −VDD to VDD.
- 2. Cbd vs. Vbs curve obtained by grounding s node, setting Is to zero, or to very small values, and measuring Cbd while sweeping Vb in step values across a range such as from −VDD to VDD.
As shown in FIG. 8, in one embodiment of the present invention, the parameter extraction step 230 comprises extracting base parameters 810; extracting other DC model parameters 820; extracting temperature dependent related parameters 830; and extracting AC parameters 840. In base parameters extraction step 810, base parameters, such as Vth (the threshold voltage at Vbs=0), K1 (the first order body effect coefficient), and K2 (the second order body effect coefficient) are extracted based on process parameters corresponding to the process technology used to fabricate the MOSFET device to be modeled. The base parameters are then used to extract other DC model parameters at step 820, which is explained in more detail in connection with FIG. 9 below.
The temperature dependent parameters are parameters that may vary with the temperature of the device and include parameters such as: Kt1 (temperature coefficient for threshold voltage); Ua1 (temperature coefficient for Ua), and Ub1 (temperature coefficient for Ub), etc. These parameters can be extracted using a conventional parameter extraction method.
The AC parameters are parameters associated with the AC characteristics of the MOSFET device and include parameters such as: CLC (constant term for the short channel model) and moin (the coefficient for the gate-bias dependent surface potential), etc. These parameters can also be extracted using a conventional parameter extraction method.
As shown in FIG. 9, the DC parameter extraction step 820 further comprises: extracting Vth related parameters (step 902); extracting Igb related parameters (step 904); extracting Igidl related parameters (step 906); extracting Igd and Igs related parameters (step 908); extracting Igc and its partition (Igcs and Igcd) related parameters (step 910); extracting Leff related parameters, Rd related parameters, and Rs related parameters (step 912); extracting mobility related parameters and Weff related parameters (step 914); extracting Vth geometry related parameters (step 916); extracting sub-threshold region related parameters (step 918); extracting parameters related to drain-induced barrier lower than regular (DIBL) (step 920); extracting Idsat related parameters (step 922); extracting Isub related parameters (step 924); and extracting junction parameters (step 926).
The equation numbers below refer to the equations set forth in Appendix B.
In step 902, threshold voltage Vth related parameters, such as Vth0, k1, k2, and Ndep, are extracted by using the linear Id vs Vgs curves measured from the largest device.
In step 904, the tunneling current, Igb, related parameters are extracted. The tunneling current is comprised of two components as defined by the following equation:
Igb=Igbacc+Igbinv
Igbacc and Igbinv related parameters are extracted separately in step 904. For the extraction of Igbacc related parameters, the Ig vs. Vbs curves for Vds=0 and Vgs=0 are used. Vds and Vgs are set to zero to minimize the effects of other currents. Then model parameters Aigbacc, Bigbacc, and Cigbacc are extracted with nonlinear-square-fit, using Equation 4.3.1. Once these parameters are extracted, Nigbacc is obtained by linear interpolation of Equation 4.3.1b using maximum slope position in the Ig vs. Vbs curves.
For the extraction of Igbinv related parameters, the Ib vs. Vgs curves when Vds=0 and Vbs=0 are used. Vds and Vbs are set to zero to minimize the effects of other currents. Model parameters Aigbinv, Bigbinv, Cigbinv are then extracted with nonlinear-square-fit, using Equation 4.3.2. Then Nigbinv and Eigbinv are obtained using Equation 4.3.2a by conventional optimization methods such as the Newton-Raphson algorithm.
In step 906, Igidl-related parameters, such as parameters AGIDL, BGIDL, CGIDL, and EGIDL, are extracted. Igidl represents the gate-induced drain leakage current, and the parameters are extracted using the device with the maximum width, W, and data from the Id VS Vgs and Is vs Vgs curves measured at the condition of Vgs<0 for NMOS (Vgs>0 for PMOS) and at different Vds and Vbs bias conditions. Isub is negligible where Vgs<0 and therefore the Ib vs Vgs curve can be used for this extraction. These assumptions and curves are used in conjunction with the extracted Vth, related parameters from step 902 and the following equation:
CGIDL is extracted using the Ib vs Vgs curve data for varying Vds. Next AIGDL and BIGDL are extracted using a conventional non-linear square fit. Finally EGIDL is obtained by optimizing AGIDL, BGIDL, and EGIDL simultaneously using a conventional optimizer such as the Newton-Raphson algorithm.
In step 908, the gate to source, Igs, and gate to drain, Igd current parameters are extracted. Igs represents the gate tunneling current between the gate and the source diffusion region, Igd represents the gate tunneling current between the gate and the drain diffusion region. Parameters extracted in step 908 include DLCIG, AIGSD, BIGSD, and CIGSD. The values of the parameters POXEDGE, TOXREF, and NTOX are set to their default values. These parameters are extracted using the Id vs Vgs and Is vs Vgs curves measured at the condition of Vds=0 and Vbs=0. Vds and Vbs are set equal to zero to minimize the effects of other currents such as channel current. This extraction utilizes the device with the maximum Ldrawn*Wdrawn, where Ldrawn is the device channel length and Wdrawn is the device width, and the extracted Vth, related parameters from step 902.
The following equations are utilized:
Igs=WeffDLCIG·A·ToxRatioEdge·Vgs·V′gs·exp[−B·TOXE·POXEDGE·(AIGSD−BIGSD·V′gs)·(1+CIGSD·V′gs)]
and
Igd=WeffDLCIG·A·ToxRatioEdge·Vgd·V′gd·exp[−B·TOXE·POXEDGE·(AIGSD−BIGSD·V′gd)·(1+CIGSD·V′gd)]
where
and
V′gs{square root}{square root over ((Vgs−Vfbsd)2+1.0e−4)}
Vgd={square root}{square root over ((Vgd−Vfbsd)2+1.0e−4)}
DLCIG is set equal to 0.7 *Xj which is a proven experimental value. Then AIGSD, BIGSD, and CIGSD are extracted from the Id/Is vs Vgs curve using the non-linear square fit method.
In step 910, the gate to current, Igc, and it's partition related parameters are extracted. Parameters extracted in step 910 includes: AIGC, BIGC, CIGC, NIGC and Pigcd. These parameters are extracted using the device with the maximum Ldrawn*Wdrawn and the data from the Ig vs Vgs curve measured at the condition of Vds=0 and Vbs=0. Vds and Vbs are set equal to zero to minimize the effects of other currents such as channel current. The data of Ig includes Igc, Igs and Igd data and is characterized by the following equation.
Ig=Igc+Igs+Igd
Since Igs and Igd are extracted in earlier steps, these effects can easily be removed with the calculated Igs and Igd. Igc is then calculated using the extracted Vth, related parameters from step 902, in coordination data from the Ig vs Vgs curve and the following equation:
Igc=WeffLeff·A·ToxRatio·VgseVaux·exp[−B·TOXE(AIGC−BIGC·Voxdepinv)·(1+CIGC·Voxdepinv)]
Where
Using a non-linear square fit, AIGC, BIGC, and CIGC are extracted. NIGC is then extracted at Vgs=Vth0 using linear interpolation.
Once calculated, Igc is then divided into its two components Igcs and Igcd
and
In step 912, parameters related to the effective channel length Leff, the drain resistance Rd and source resistance Rs are extracted. The Leff, Rd and Rs related parameters include parameters such as Lint, and Rdsw, and are extracted using data from the linear Id vs Vgs curves as well as the extracted Vth related parameters from step 902.
In step 914, parameters related to the mobility and effective channel width Weff, such as μ0, Ua, Ub, Uc, Wint, Wr, Prwb, Wr, Prwg, Rdsw, Dwg, and Dwb, are extracted, using the linear Id VS Vgs curves and the extracted Vth, related parameters from step 902.
Steps 902, 912, and 914 can be performed using a conventional BSIM4 model parameter extraction method. Discussions about some of the parameters involved in these steps can be found in the following:
- Liu, William “MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4,” John Wiley & Sons, Inc. 2001
which is incorporated by reference herein.
In step 916, the threshold voltage Vth geometry related parameters, such as DVT0, DVT1, DVT2, NLX1, DVT0W, DVT1W, DVT2W, k3, and k3b, are extracted, using the linear Id vs Vgs curve, the extracted Vth, Leff, and mobility and Weff related parameters from steps 902, 912, and 914, and Equations 2.5.5-2.5.7.
In step 918, sub-threshold region related parameters, such as Cit, Nfactor, Voff, Ddsc, and Cdscd, are extracted, using the linear Id vs Vgs curves, the extracted Vth, Leff and Rd and Rs and mobility and Weff related parameters from steps 902, 912, and 914, and Equations (3.2.1-3.2.3.
In step 920, DIBL related parameters, such as Dsub, Eta0 and Etab, are extracted, using the saturation Id vs Vgs curves and the extracted Vth related parameters from step 902, and Equations 2.5.5-2.5.7.
In step 922, the drain saturation current Idsat related parameters, such as B0, B1, A0, Keta, and Ags, are extracted using the saturation Id VS Vds curves, the extracted Vth, Leff and Rd and Rs, mobility and Weff, Vth geometry, sub-threshold region, and DIBL related parameters from steps 902, 912, 914, 916, 918, and 920 and Equation 14.1.
In step 924, the impact ionization current Iii related parameters, such as α0, α1, and β0, are extracted using the data from the linear Id VS Vgs curve and Equations 6.1.1-6.1.2.
In step 926, the junction parameters, such as Cjswg, Pbswg, and Mjswg, are extracted using the Cbs VS. Vbs and Cbd vs. Vbs curves, and Equations 10.2.1-10.2.7.
In performing the DC parameter extraction steps (steps 902-926), it is preferred that after the Igb, Igd, Igs Igidl, and Igc related parameters are extracted in steps 904 through 910, Igb, Igd, Igs, Igidl, and Igc are calculated based on these parameters and the model equations. This calculation is done for the bias condition of each data point in the measured I-V curves. The I-V curves are then modified for the first time based on the calculated Igb, Igd, Igs, Igidl, and Igc values. In one embodiment of the present invention, the I-V curves are first modified by subtracting the calculated Igb, Igd, Igs, Igidl, and Igc values from respective Is, Id, and Ib data values. For example, for a test device having drawn channel length Ldrn and drawn channel width Wdrn, if under bias condition where Vs=VsT, Vd=VdT, Vp=VpT, Ve=VeT, and Vg=VgT, the measured drain current is IdT, then after the first modification, the drain current will be Idfirst-modified=IdT−IgdT−IgidlT where IgdT and IgidlT, are calculated respectively, for the same test device under the same bias condition. The first-modified I-V curves are then used for additional DC parameter extraction. This results in higher degree of accuracy in the extracted parameters. In one embodiment the Igb, Igd, Igs, Igidl and Igc related parameters are extracted before extracting other DC parameters, so that I-V curve modification may be done for more accurate parameter extraction. However, if such accuracy is not required, one can choose not to do the above modification and the Igb, Igd, Igs, Igidl, and Igc related parameters can be extracted at any point in the DC parameter extraction step 820.
The forgoing descriptions of specific embodiments of the present invention are presented for purpose of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Furthermore, the order of the steps in the method are not necessarily intended to occur in the sequence laid out. It is intended that the scope of the invention be defined by the following claims and their equivalents.
APPENDIX A
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Parameter List
ParameterDefault
nameDescriptionvalueBinnable?Note
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A.1 BSIM 4.0.0 Model Selectors/Controllers
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(LEVELSPICE3 model selector14NABSIM4
SPICE3also set as
parameter)the default
model in
SPICE3
VERSIONModel version number4.0.0NABerkeley
Latest
official
release
BINUNITBinning unit selector1NA—
PARAMCHKSwitch for parameter value check1NAParameters
checked
MOBMODMobility model selector0NA—
RDSMODBias-dependent source/drain0NARds(V)
resistance model selectormodeled
internally
through IV
equation
IGCMODGate-to-channel tunneling current0NAOFF
model selector
IGBMODGate-to-substrate tunneling current0NAOFF
model selector
CAPMODCapacitance model selector2NA—
RGATEMODGate resistance model selector0
(Also an(no gate
instanceresistance)
parameter)
RBODYMODSubstrate resistance network model0NA—
(Also anselector(network
instanceoff)
parameter)
TRNQSMODTransient NQS model selector0NAOFF
(Also an
instance
parameter)
ACNQSMODAC small-signal NQS model0NAOFF
(Also anselector
instance
parameter)
FNOIMODFlicker noise model selector1NA—
TNOIMODThermal noise model selector0NA—
DIOMODSource/drain junction diode IV1NA—
model selector
PERMODWhether PS/PD (when given)1NA—
includes the gate-edge perimeter(including
the gate-
edge
perimeter)
GEOMODGeometry-dependent parasitics0NA—
(Also anmodel selector - specifying how the(isolated)
instanceend S/D diffusions are connected
parameter)
RGEOMODSource/drain diffusion resistance0NA—
(Instanceand contact model selector -(no S/D
parameterspecifying the end S/D contact type:diffusion
only)point, wide or merged, and howresistance)
S/D parasitics resistance is
computed
A.2 Process Parameters
|
EPSROXGate dielectric constant relative to3.9 (SiO2)NoTypically
vacuumgreater
than or
equal to
3.9
TOXEElectrical gate equivalent oxide3.0e−9mNoFataleno
thicknessr if not
positive
TOXPPhysical gate equivalent oxideTOXENoFatalerro
thicknessr if not
positive
TOXMTox at which parameters are extractedTOXENoFatal
error if
not
positive
DTOXDefined as (TOXE-TOXP)0.0 mNo—
XJS/D junction depth1.5e−7mYes—
GAMMA1Body-effect coefficient near the surfacecalculatedV1/2Note-1
(λ1 incalculated
equation)
GAMMA2Body-effect coefficient in the bulkcalculatedV1/2Note-1
(λ1 in
equation)
NDEPChannel doping concentration at1.7e17cm−3YesNote-2
depletion edge for zero body bias
NSUBSubstrate doping concentration6.0e16cm−3Yes—
NGATEPoly Si gate doping concentration0.0 cm−3Yes—
NSDSource/drain doping concentrationFatal1.0e20cm−3Yes—
error if not positive
VBXVb s at which the depletion regioncalculatedNoNote-3
width equalsXT(V)
XTDoping depth1.55e−7mYes—
RSHSource/drain sheet resistance0.0 ohm/NoShould
squarenot be
negative
RSHGGate electrode sheet resistance0.1 ohm/NoShould
squarenot be
negative
A.3 Basic Model Parameters
|
VTH0 orLong-channel threshold voltage at0.7 VYesNote-4
VTHOVbs = 0(NMOS)
−0.7 V
(PMOS)
VEBFlat-band voltage−1.0 VYesNote-4
PHLNNon-uniform vertical doping effect on0.0 VYes—
surface potential
K1First-order body bias coefficient0.5 V1/2YesNote-5
K2Second-order body bias coefficient0.0YesNote-5
K3Narrow width coefficient80.0Yes−
K3BBody effect coefficient of K30.0 V−1Yes—
W0Narrow width parameter2.5e−6mYes—
LPE0Lateral non-uniform doping parameter1.74e−7mYes—
at VbS = 0
LPEBLateral non-uniform doping effect on0.0 mYes—
K1
VBMMaximum applied body bias in VTHO−3.0 VYes—
calculation
DVT0First coefficient of short-channel effect2.2Yes—
on Vth
DVT1Second coefficient of short-channel0.53Yes—
effect on Vth
DVT2Body-bias coefficient of short-channel−0.032 V −1Yes—
effect on Vth
DVTPOFirst coefficient of drain-induced Vth0.0 mYesNot
shift due to for long-channel pocketmodeled
binned devicesif
binned
DVTPO
<=0.0
DVTP1First coefficient of drain-induced Vth0.0 V−1Yes—
chist due to for long-channel pocket
devices
Basic Model Parameters
|
DVT0WFirst coefficient of narrow width effect0.0Yes—
on Vth for small channel length
DVT1WSecond coefficient of narrow width5.3e6m−1Yes—
effect on Vth for small channel length
DVT2WBody-bias coefficient of narrow width−0.032 V−1Yes
effect for small channel length
U0Low-field mobility0.067Yes—
m2/(Vs)
(NMOS);
0.025
m2/(Vs)
PMOS
UACoefficient of first-order mobility1.0e−9 m/VYes—
degradation due to vertical field forMOBMOD =
0 and 1;
1.0e−15 m/V
for
MOBMOD = 2
UBCoefficient of secon-order mobility1.0e−19 m2/V2Yes—
degradation due to vertical field
UCCoefficient of mobility degradation−0.0465 V−1Yes—
due to body-
bias effect
for MOB-
MOD = 1;
−0.0465e−9
m/V2 for
MOBMOD =
0 and 2
EUExponent for mobility degradation of1.67—
MOBMOD = 2(NMOS);
1.0
(PMOS)
VSATSaturation velocity8.0e4m/sYes—
A0Coefficient of channel-length1.0Yes—
dependence of bulk charge effect
AGSCoefficient of Vgs dependence of bulk0.0 V−1Yes—
charge effect
B0Bulk charge effect coefficient for0.0 mYes—
channel width
B1Bulk charge effect width offset0.0 mYes—
KETABody-bias coefficient of bulk charge—0.047 V−1Yes—
effect
A1First non-saturation effect parameter0.0 V−1Yes
A2Second non-saturation factor1.0Yes—
WINTChannel-width offset parameter0.0 mNo—
LINTChannel-length offset parameter0.0 mNo—
DWGCoefficient of gate bias dependence of0.0 m/VYes—
Weff
DWBCoefficient of body bias dependence of0.0 m/V1/2Yes—
Weff
VOFFOffset voltage in subtbreshold−0.08 VYes—
region for large W and L
VOFFLChannel-length dependence of VOFF0.0 mVNo—
MINVVgsteff fitting parameter for moderate0.0Yes—
inversion condition
NFACTORSubthreshold swing factor1.0Yes—
ETA0DIBL coefficient in subthreshold region0.08Yes—
ETABBody-bias coefficient for the−0.07 V−1Yes—
subthreshold DTBL effect
DSUBDIBL coefficient exponent inDROUTYes—
subthreshold region
CITInterface trap capacitance0.0 F/m2Yes—
CDSCcoupling capacitance between2.4e−4F/m2Yes—
source/drain and channel
CDSCBBody-bias sensitivity of Cdsc0.0F/(Vm2)Yes—
CDSCDDrain-bias sensitivity of CDSC0.0(F/Vm2)Yes—
PCLMChannel length modulation parameter1.3Yes—
PDIBLC1Parameter for DIBL effect on Rout0.39Yes—
PDIBLC2Parameter for DIBL effect on Rout0.0086Yes—
PDIBLCBBody bias coefficient of DIBL effect on0.0V−1Yes—
Rout
DROUTChannel-length dependence of DIBL0.56Yes—
effect on Rout
PSCBE1First substrate current induced body-4.24e8VmYes—
effect parameter
PSCBE2Second substrate current induced body-1.0e−5m/VYes—
effect parameter
PVAGGate-bias dependence of Early voltage0.0Yes—
DELTAParameter for DC Vdseff0.01VYes—
(δ in
equation)
FPROUTEffect of pocket implant on Rout0.0 V/m0.5YesNot
degradationmodeled
if binned
FPROUT
not
positive
PDITSImpact of drain-induced Vth shift on0.0 V−1YesNot modeled
Routif Rout
binned
PDITS =
0;
Fatal
error if
binned
PDITS
negative
PDITSLChannel-length dependence of drain-0.0 m−NoFatal
induced Vth shift for Routerror if
PDITSL
negative
PDITSDVds dependence of drain-induced VthYes—
shift for Rout
A.4 Parameters for Asymmetric and Bias-Dependent Rds Model
|
RDSWZero bias LDD resistance per unit width200.0YesIf
for RDSMOD = 0ohmnegative,
(μm)WRreset to
0.0
RDSWMINLDD resistance per unit width at0.0No—
high Vgs and zero Vbsohm
for RDSMOD = 0(μm)WR
RDWZero bias lightly-doped drain resistance100.0Yes—
Rd(V) per unit width for RDS-MOD = 1ohm
(μm)WR
RDWMINLightly-doped drain resistance per unit0.0No—
width at high Vgs and zero Vbs forohm
RDSMOD = 1(μm)WR
RSWZero bias lightly-doped source100.0Yes—
resistance Rs(V) per unitohm
width for RDS-MOD = 1(μm)WR
RSWMINLightly-doped source resistance per unit0.0No—
width at high Vgs and zero Vbs for
RDSMOD = 1
PRWGGate-bias dependence of LDD1.0 V−1Yes—
resistance
PRWBBody-bias dependence of LDD0.0 V−0.5Yes—
resistance
WRChannel-width dependence parameter of1.0Yes—
LDD resistance
NRSNumber of source diffusion square1.0No—
(instance
parameter
only)
NRDNumber of drain diffusion squares1.0No—
(instance
parameter
only)
ALPHA0First parameter of impact ionization0.0 Am/VYes—
current
ALPHA1Isub parameter for length scaling0.0 A/VYes—
BETA0The second parameter of impact30.0 VYes—
ionization current
A.6 Gate-Induced Drain Leakage Model Parameters
|
AGIDLPre-exponential coefficient for GLDL0.0 mhoYesIgidl = 0.0
if binned
AGIDL =
0.0
BGIDLExponential coefficient for GIDL2.3e9 V/m YesIgidl = 0.0
if binned
BGIDL =
0.0
CGIDLParamter for body-bias effect on GIDL0.5 V3Yes—
DGIDLFitting parameter for band bending for0.8 VYes—
GIDL
A.7 Gate Dielectric Tunneling Current Model Parameters
|
AIGBACCParameter for Igb in accumulation0.43Yes—
(Fs2/g)0.5m−1
BIGBACCParameter for Igb in accumulation0.054Yes—
(Fs2/g)0.5
m−1V−1
CIGBACCParameter for Igb in accumulation0.075 V−1Yes—
NIGBACCParameter for Igb in accumulation1.0YesFatal error
if binned
value not
positive
AIGBINVParameter for Igb in inversion0.35Yes—
(Fs2/g)0.5m−1
BIGBINVParameter for Igb in inversion0.03Yes—
(Fs2/g)0.5
CIGBINVParameter for Igb in inversion0.006 V−1Yes—
EIGBINVParameter for Igb in inversion1.1 VYes—
NIGBINVParameter for Igb in inversion3.0YesFatal error
if binned
value not
positive
AIGCParameter for Igcs and Igcd0.054Yes—
(NMOS) and
0.31
(PMOS)
(Fs2/g)0.5m−1
BIGCParameter for Igcs and Igcd0.054Yes—
(NMOS) and
0.024
(PMOS)
(Fs2/g)0.5
m−1V−1
CIGGParameter for Igcs and Igcd0.075Yes—
(NMOS) and
0.03
(PMOS) V−1
AIGSDParameter for Igs and Igd0.43Yes—
(NMOS) and
0.31
(PMOS)
(Fs2/g)0.5m−1
BIGSDParameter for Igs and Igd0.054Yes—
(NMOS) and
0.024
(PMOS)
(Fs2/g)0.5
m−1V−1
CIGSDParameter for Igs and Igd0.075Yes—
(NMOS) and
0.03
(PMOS) V−1
DLCIGSource/drain overlap length for IgsLINTYes—
and Igd
NIGCParameter for Igcs, Igcd, Igs and Igd1.0YesFatal error
if binned
value not
positive
POXEDGEFactor for the gate oxide thickness in1.0YesFatal error
source/drain overlap regionsif binned
value not
positive
PIGCDVds dependence of Igcs and Igcd1.0YesFatal error
if binned
value not
positive
NTOXExponent for the gate oxide ratio1.0Yes—
TOXREFNominal gate oxide thickness for gate3.0e−9mNoFatal error
dielectric tunneling current modelif not positive
only
A.8 Charge and Capacitance Model Parameters
|
XPARTCharge partition parameter0.0No—
CGSONon LDD region source-gate overlapcalculatedNoNote-6
capacitance per unit channel width(F/m)
CGDONon LDD region drain-gate overlapcalculatedNoNote-6
capacitance per unit channel width(F/m)
CGBOGate-bulk overlap capacitance per0.0F/mNote-6
unit channel length
CGSLOverlap capacitance between gate and0.0 F/mYes—
lightly-doped source region
CGDLOverlap capacitance between gate and0.0 F/mYes—
lightly-doped source region
CKAPPASCoefficient of bias-dependent overlap0.6 VYes—
capacitance for the source side
CKAPPADCoefficient of bias-dependent overlapCKAPPASYes—
capacitance for the drain side
CFFringing field capacitancecalculatedYesNote-7
(F/m)
CLCConstant term for the short channel1.0e−7mYes—
model
CLEExponential term for the short channel0.6Yes—
model
DLCChannel-length offset parameter forLINT (m)No—
CV model
DWCChannel-width offset parameter forWINT (m)No—
CV model
VFBCVFlat-band voltage parameter (for—1.0 VYes—
CAPMOD = 0 only)
NOFFCV parameter in Vgsteff,CV for weak to1.0Yes—
strong inversion
VOFFCVCV parameter in Vgsteff,CV for week to0.0 VYes—
strong inversion
ACDEExponential coefficient for charge1.0 m/VYes—
thickness in CAPMOD = 2 for accumu-
lation and depletion regions
MOINCoefficient for the gate-bias depen-15.0Yes—
dent surface potential
A.9 High-Speed/RF Model Parameters
|
XRCRG1Parameter for distributed channel-12.0YesWarning
resistance effect for both intrinsic-message
input resistance and charge-deficitissued if
NQS modelsbinned
XRCRG1
<=0.0
XRCRG2Parameter to account for the excess1.0Yes—
channel diffusion resistance for both
intrinsic input resistance and charge-
deficit NQS models
RBPBResistance connected between50.0 ohmNoIf less than
(Also anbNodePrime and bNode1.0e−3ohm,
instancereset to
parameter)1.0e−3ohm
RBPDResistance connected between50.0 ohmNoIf less than
(Also anbNodePrime and dbNode1.0e−3ohm,
instancereset to
parameter)1.0e−3ohm
RBPSResistance connected between50.0 ohmNoIf less than
(Also anbNodePrime and sbNode1.0e−3ohm,
instancereset to
parameter)1.0e−3ohm
RBDBResistance connected between50.0 ohmNoIf less than
(Also andbNode and bNode1.0e−3ohm,
instancereset to
parameter)1.0e−3ohm
RBSBResistance connected between50.0 ohmNoIf less than
(Also ansbNode and bNode1.0e−3ohm,
instancereset to
parameter)1.0e−3ohm
GBMINConductance in parallel with each of1.0e−12mhoNoWarning
the five substrate resistances to avoidmessage
potential numerical instability due toissued if
unreasonably too large a substrateless than
resistance1.0e−20
mho
A.10 Flicker and Thermal Noise Model Parameters
|
NOIAFlicker noise parameter A6.25e41No—
(eV)−1s1−EFm−3
for NMOS;
6.188e40
(eV)−1s1−EFm−3
for PMOS
NOIBFlicker noise parameter B3.125e26No—
(eV)−1s1−EFm−1
for NMOS;
1.5e25
(eV)−1s1−EFm−1
for PMOS
NOICFlicker noise parameter C8.75No—
(eV)−1s1−EFm
EMSaturation field4.1e7V/mNo—
AFFlicker noise exponent1.0No—
EFFlicker noise frequency exponent1.0No—
KYFlicker noise coefficient0.0No—
A2−EFs1−EFF
NTNOINoise factor for short-channel devices1.0No−
for TNOIMOD = 0 only
TNOIACoefficient of channel-length depen-1.5No—
dence of total channel thermal noise
TNOIBChannel-length dependence parameter3.5No—
for channel thermal noise partitioning
A.11 Layout-Dependent Parasitics Model Parameters
|
DMCGDistance from S/D contact center to0.0 mNo—
the gate edge
DMCIDistance from S/D contact center toDMCGNo—
the isolation edge in the channel-
length direction
DMDGSame as DMCG but for merged0.0 mNo—
device only
DMCGTDMCG of test structures0.0 mNo—
NFNumber of device fingers1NoFatal error
(instanceif less than
parameterone
only)
DWJOffset of the S/D junction widthDWC (inNo—
CVmodel)
MINWhether to minimize the number of0No—
(instancedrain or source diffusions for even-(minimize
parameternumber fingered devicethe drain dif-
only)fusion number)
XGWDistance from the gate contact to the0.0 mNo—
channel edge
XGLOffset of the gate length due to varia-0.0 mNo—
tions in patterning
XLChannel length offset due to mask/0.0 mNo—
etch effect
XWChannel width offset due to mask/etch0.0 mNo—
effect
NGCONNumber of gate contacts1NoFatal error
if less than
one; if not
equal to I
or 2, warn-
ing mes-
sage issued
and reset to 1
A.12 Asymmetric Source/Drain Junction Diode Model Parameters
|
(separate for
source and drain
side as indicated
in the names)
IJTHSREVLimiting current in reverse bias regionIJTHSREV =NoIf not posi-
IJTHDREV0.1 Ative, reset
IJTHDREV =to 0.1 A
IJTHSREV
IJTHSFWDLimiting current in forward biasIJTHSFWD =NoIf not posi-
IJTHDFWDregion0.1 Ative, reset
IJTHDFWD =
IJTHSFWD
XJBVSFitting parameter for diode break-XJBVS = 1.0NoNote-8
XJBVDdownXJBVD =
XJBVS
BVSBreakdown voltageBVS = 10.0 VNoIf not posi
BVDBVD = BVStive, reset
to 10.0 V
JSSBottom junction reverse saturationJSS =No—
JSDcurrent density1.0e−4 A/m2
JSD = JSS
JSWSIsolation-edge sidewall reverse satura-JSWS =No—
JSWDtion current density0.0 A/m
JSWD =
JSWS
JSWGSGate-edge sidewall reverse saturationJSWGS =No—
JSWGDcurrent density0.0 A/m
JSWGD =
JSWGS
CJSBottom junction capacitance per unitCJS = 5.0e−4No—
CJDarea at zero biasF/m2
CJD = CJS
MJSBottom junction capacitance gratingMJS = 0.5No—
MIDcoefficientMJD = MJS
MJSWSIsolation-edge sidewall junctionMJSWS =No—
MJSWDcapacitance grading coefficient0.33
MJSWD =
MJSWS
CJSWSIsolation-edge sidewall junctionCJSWS =No—
CJSWDcapacitance per unit area5.0e−10
F/m
CJSWD =
CJSWS
CJSWGSGate-edge sidewall junction capaci-CJSWGS =No—
CJSWGDtance per unit lengthCJSWS
CJSWGD =
CJSWS
MISWGSGate-edge sidewall junction capaci-MJSWGS =No—
MJSWGDtance grading coefficientMJSWS
MJSWGD =
MJSWS
PBBottom junction bnilt-in potentialPBS = 1.0 VNo—
PBD = PBS
PBSWSIsolation-edge sidewall junction built-PBSWS =No—
PBSWDin potential1.0 V
PBSWD =
PBSWS
PBSWGSGate-edge sidewall junction built-inPBSWGS =No—
PBSWGDpotentialPBSWS
PBSWGD =
PBSWS
A.13 Temperature Dependence Parameters
|
TNOMTemperature at which parameters are27° C.No—
extracted
UTEMobility temperature exponent−1.5Yes—
KT1Temperature coefficient for threshold−0.11 VYes—
voltage
KT1LChannel length dependence of the0.0 VmYes—
temperature coefficient for threshold
voltage
KT2Body-bias coefficient of Vth tempera-0.022Yes—
ture effect
UA1Temperature coefficient for UA1.0e−9m/VYes—
UBITemperature coefficient for UB−1.Oe−18Yes—
(m/V)2
UC1Temperature coefficient for UC0.067 V−1 forYes—
MOBMOD = 1;
0.025 m/V2
for MOBMOD =
0 and 2
ATTemperature coefficient for satura-3.3e4m/sYes—
tion velocity
PRTTemperature coefficient for Rdsw0.0 ohm-mYes—
NIS, NJDEmission coefficients of junction forNJS = 1.0;No—
source and drain junctions, respec-NJD = NJS
tively
XTIS, XTIDJunction current temperature expo-XTIS = 3.0;No—
nents for source and drain junctions,XTID = XTIS
respectively
TPBTemperature coefficient of PB0.0 V/KNo—
TPBSWTemperature coefficient of PBSW0.0 V/KNo—
TPBSWGTemperature coefficient of PBSWG0.0 V/KNo—
TCJTemperature coefficient of CJ0.0 K−1No—
TCJSWTemperature coefficient of CJSW0.0 K−1No—
TCJSWGTemperature coefficient of CJSWG0.0 K−1No—
A.14 dW and dL Parameters
|
WLCoefficient of length dependence for0.0 mWLNNo—
width offset
WLNPower of length dependence of width1.0No—
offset
WWCoefficient of width dependence for0.0 mWWNNo—
width offset
WWNPower of width dependence of width1.0No—
offset
WWLCoefficient of length and width cross0.0No—
term dependence for width offsetmWWN+WLN
LLCoefficient of length dependence for0.0 mLLNNo—
length offset
LLNPower of length dependence for1.0No—
length offset
LWCoefficient of width dependence for0.0 mLWNNo—
length offset
LWNPower of width dependence for length1.0No—
offset
LWLCoefficient of length and width cross0.0No—
term dependence for length offsetmLWN+LLN
LLCCoefficient of length dependence forLLNo—
CV channel length offset
LWCCoefficient of width dependence forLWNo—
CV channel length offset
LWLCCoefficient of length and width cross-LWLNo—
term dependence for CV channel
length offset
WLCCoefficient of length dependence forWLNo—
CV channel width offset
WWCCoefficient of width dependence forWWNo—
CV channel width offset
WWLCCoefficient of length and width cross-WWLNo—
term dependence for CV channel
width offset
|
NOTES:
Note-1:
If γ1 is not given, it is calculated by
|
If γ2 is not given, it is calculated by
|
Note-2:
If NDEP is not given and γ1 is given, NDEP is calculated from
|
If both γ1 and NDEP are not given, NDEP defaults to 1.7e17 cm−3
and γ1 is calculated from NDEP.
Note-3:
If VBX is not given, it is calculated by
|
Note-4:
If VTH0 is not given, it is calculated by
|
where VFB = −1.0. If VTH0 is given, VFB defaults to
|
Note-5:
If K1 and K2 are not given, they are calculated by
|
Note-6:
If CGSO is not given, it is calculated by
If(DLC is given and > 0.0)
CGSO = DLC · Coxe − CGSL
if (CGSO < 0.0), CGSO = 0.0
Else
CGSO = 0.6 · XJ · Coxe
If CGDO is not given, it is calculated by
If(DLC is given and > 0.0)
CGDO = DLC · Coxe − CGDL
if(CGDO < 0.0), CGDO = 0.0
Else
CGDO = 0.6 · XJ · Coxe
If CGBO is not given, it is calculated by
CGBO = 2 · DWC · Coxe
Note-7:
If CF is not given, it is calculated by
|
Note-8:
For dioMod = 0, if XJBVS < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVS <= 0.0, it is reset to 1.0.
For dioMod = 0, if XJBVD < 0.0, it is reset to 1.0.
For dioMod = 2, if XJBVD <= 0.0, it is reset to 1.0.
Poly Silicon Gate Depletion
Vgs−VFB−Φs=VpolyVox (1.2.3)
a(Vgs−VFB−Φs−Vpoly)2Vpoly=0 (1.2.4)
where
Effective Channel Length and Width
Long Channel Model with Uniform Doping
Long Channel Model with Non-Uniform Doping
- where K1NDEP is the body-bias coefficient for Nsubstrate=NDEP,
Vth,NDEP=VTH0+K1NDEP({square root}{square root over (φs−Vbs)}−{square root}{square root over (φs)}) (2.2.2)
with a definition of
Vth=VTH0+K1({square root}{square root over (Φs−Vbs)}−{square root}{square root over (Φs)})−K2·Vbs (2.2.6)
where K2=qC01/Coxe, and the surface potential is defined as
where
PHIN=−qD10/εsi
K1=γ2−2K2{square root}{square root over (Φs−VBM)} (2.2.8)
Non-Uniform Lateral Doping
Short-Channel and DIBL Effect
ΔVth(SCE,DIBL)=−θth(Leff)·[2(Vbi−Φs)+Vds] (2.4.1)
Narrow Width Effect
Channel Charge Model
where
where
Subthreshold Swing
where
Voltage Across Oxide
Gate to Substrate Current
Gate to Channel Current
Partition
Igc=Igcs+Igcd
Drain Current Model
Bulk Charge Effect
Unified Mobility Model
- mobMod=0
- mobMod=1
- mobMod=2
Asymmetric and Bias Dependent Source/Drain Resistance Model
- rdsMod=0
- rdsMod=1
Drain Current for Triode Region
- rdsMod=1
- rdsMod=0
Velocity Saturation
Saturation Voltage Vdsat
Intrinsic
Extrinsic
c=(Vgsteff+2ν1)EsatLeff+2(Vgsteff+2ν1)2WeffVSATCoxeRds (5.6.2d)
λ=A1Vgsteff+A2 (5.6.2e)
Vdseff
Saturation-Region Output Conductance Model
Channel Length Modulation
Drain Induced Barrier Lower (DIBL)
Substrate Current Induced Body Effect (SCBE)
Drain Induced Threshold Shift (DITS)
Single Equation Channel Current Model
where NF is the number of device fingers, and
VA is written as (5.8.2)
VA=VAsat+VACLM (5.8.3)
Body Current Model
Iii Model
Igidl Model
Intrinsic Capacitance Modeling
Basic Formulation
- where Vgt=Vgse−Vth and
where i and j denote the transistor terminals, Cij satisfies
Short Channel Model
Single Equation Formulation
- depletion to inversion region
Accumulation to Depletion Region
Vfbzb=Vth|zeroVbsandVds−Φs−K1{square root}{square root over (Φs)} (7.2.14)
Linear to Saturation Region
Charge Petitioning
Charge—Thickness Capacitance Model
- where
Ccen=εsi/XDC
Accumulation and Depletion
- where Ldebye is Debye length, and XDC is in the unit of cm and (Vgse−Vbseff−VFBeff)/TOXE is in units of MV/Cm. For numerical statbility, (7.3.2) is replaced by (7.3.3)
where
X0=Xmax−XDC−δx
and Xmax=Ldebye/3; δx=10−3TOXE.
Inversion Charge
Body Charge Thickness in Inversion
qinv=−Coseff·(Vgseff,CV−φδ) (7.3.6)
Intrinsic Capacitance Model Equations
Accumulation Region
Qδ=WactiveLactiveCoxe(Vgs−Vbs−VFBCV)
Qsub=−Qs
Qinv=0
Subthreshold Region
Strong Inversion Region
Vth=VFBCV+φs+Klox{square root}{square root over (Φs−Vbseff)}
Linear Region
50/50 Partitioning:
Qs=Qd=0.5Qinv
40/60 Partitioning:
Qs=−(Qs+Qb+Qd)
0/100 Partitioning:
Qs=−(Qg+Qb+Qd)
Saturation Region
50/50 Partitioning:
40/60 Partitioning:
Qs=−(Qg+Qb+Qd)
0/100 Partitioning:
Qd=0
Qs=−(Qg+Qb)
capMod=1
Qg=−(Qinv+Qacc+Qsub0+δQsub)
Qb=−(Qacc+Qsub0+δQsub)
Qinv=Qs+Qd
Qacc=−WactiveLactiveCoxe·(VFBeff−Vfbzb)
50/50 Charge Partitioning:
40/60 Charge Partitioning:
0/100 Charge Partitioning:
capMod=2
50/50 Partitioning:
40/60 Partitioning:
0/100 Partitioning:
Fringe Capacitance Model
Bias-Dependent Overlap Capacitance Model
(i) Source Side
(ii) Drain Side
(iii) Gate Overlap Charge
Qoverlap,g=−(Qoverlap,d+Qoverlap,s+(CGBO·Lactive)·Vgb) (7.5.6)
Bias-Independent Overlap Capacitance Model
The gate-to-source overlap charge is expressed by
Qoverlap,s=Wactive·CGSO·Vgs
The gate-to-drain overlap charge is calculated by
Qoverlap,d=Wactive·CGDO·Vgd
The gate-to-substrate overlap charge is computed by
Qoverlap,b=Lactive·CGBO·Vgb
Charge-Deficit Non-Quasi Static Model
The Transient Model
The AC Model
Gate Electrode Electrode and Intrinsic-Input Resistance Model
Charge-Deficit Non-Quasi Static Model
The Transient Model
The AC Model
Gate Electrode Electrode and Intrinsic-Input Resistance Model
Channel Thermal Noise
Junction Diode IV Model
Source/Body Junction Diode
- dioMod=0
- dioMod=1
Drain/Body Junction Diode
- dioMod=0
- dioMod=1
Junction Diode CV Model
Source/Body Junction Diode
Cbs=AseffCjbs+PseffCjbasw+Weffcj·NF·Cjbsswg (10.2.1)
If Vbs<0, use equn. 10.2.2, otherwise use equn. 10.2.3
If Vbs<0, use equn. 10.2.4, otherwise use equn. 10.2.5
If Vbs<0, use equn. 10.2.6, otherwise use equn. 10.2.7
Drain/Body Junction Diode
Cbd=AdeffCjbd+PdeffCjbdsw+Weffcj·NF·Cjbdswg (10.2.8)
If Vbd<0, use equn. 10.2.9, otherwise use equn. 10.2.10
If Vbd<0, use equn. 10.2.11, otherwise use equn. 10.2.12
If Vbd<0, use equn. 10.2.13, otherwise use equn. 10.2.14
Layout Dependent Parasitic Models
Gate Electrode Resistance
Temperature Dependence Model
- Temperature Dependence of Threshold Voltage
Temperature Dependence of Mobility
U0(T)=U0(TNOM)·(T/TNOM)UTE (12.2.1)
UA(T)=UA(TNOM)+UA1(T/TNOM−1) (12.2.2)
UB(T)=UB(TNOM)+UB1·(T/TNOM−1) (12.2.3)
UC(T)=UC(TNOM)+UC1·(T/TNOM−1) (12.2.4)
Temperature Dependency of Saturation Velocity
VSAT(T)=VSAT(TNOM)−AT·(T/TNOM−1) (12.3.1)
Temperature Dependency of LDD Resistance
- rdsMod=0
RDSW(T)=RDSW(TNOM)+PRT·(T/TNOM−1) (12.4.1)
RDSWMIN(T)=RDSWMIN(TNOM)+PRT·(T/TNOM−1) (12.4.2) - rdsMod=1
RDW(T)=RDW(TNOM)+PRT·(T/TNOM−1) (12.4.3)
RDWMIN(T)=RDWMIN(TNOM)+PRT·(T/TNOM−1) (12.4.4)
RSW(T)=RSW(TNOM)+PRT·(T/TNOM−1) (12.4.5)
RSWMIN(T)=RSWMIN(TNOM)+PRT·(T/TNOM−1) (12.4.6)
Temperature Dependence of Junction Diode IV
Isbs=AseffJss(T)+PseffJssws(T)+Weffcj·NF·Jsswgs(T) (12.5.1)
drain side diode
Isbd=AdeffJsd(T)+PdeffJsswd(T)+Weffcj·NF·Jsswgd(T) (12.5.5)
Temperature Dependence of Junction Diode CV
- source side diode
CJS(T)=CJS(TNOM)·[1+TCJ·(T−TNOM)] (12.6.1)
CJSWS(T)=CJSWS(TNOM)+TCJSW·(T−TNOM) (12.6.2)
CJSWGS(T)=CJSWGS(TNOM)·[1+TCJSWG·(T−TNOM)] (12.6.3)
PBS(T)=PBS(TNOM)−TPB·(T−TNOM) (12.6.4)
PBSWS(T)=PBSWS(TNOM)−TPBSW·(T−TNOM) (12.6.5)
PBSWGS(T)=PBSWGS(TNOM)−TPBSWG·(T−TNOM) (12.6.6)
drain side diode
CJD(T)=CJD(TNOM)·[1+TCJ·(T−TNOM)] (12.6.7)
CJSWD(T)=CJSWD(TNOM)+TCJSW·(T−TNOM) (12.6.8)
CJSWGD(T)=CJSWGD(TNOM)·[1+TCJSWG·(T−TNOM)] (12.6.9)
PBD(T)=PBD(TNOM)−TPB·(T−TNOM) (12.6.10)
PBSWD(T)=PBSWD(TNOM)−TPBSW·(T−TNOM) (12.6.11)
PBSWGD(T)=PBSWGD(TNOM)−TPBSWG·(T−TNOM) (12.6.12)
Temperature Dependences of Eg and ni
Drain Saturation Current Parameters