Extracting semiconductor device model parameters

Information

  • Patent Application
  • 20050086033
  • Publication Number
    20050086033
  • Date Filed
    September 02, 2003
    21 years ago
  • Date Published
    April 21, 2005
    19 years ago
Abstract
The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIM4 model. The device model parameters for the device model includes a plurality of base parameters, DC model parameters, temperature dependent related parameters, and AC parameters. The method also includes steps for extracting various DC model parameters. The present invention also includes a method for extracting device model parameters including the steps of extracting a portion of the DC model parameters based on the terminal current data, modifying the terminal current data based on the extracted portion of the DC model parameters, and extracting a second portion of the DC model parameters based on the modified terminal current data.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention


The invention relates generally to computer-aided electronic circuit simulation, and more particularly, to a method of extracting semiconductor device model parameters for use in integrated circuit simulation.


2. Description of Related Art


Computer aids for electronic circuit designers are becoming more prevalent and popular in the electronic industry. This move toward electronic circuit simulation was prompted by the increase in both complexity and size of circuits. As circuits have become more complex, traditional breadboard methods have become burdensome and overly complicated. With increased computing power and efficiency, electronic circuit simulation is now standard in the industry. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as, SPICE2 or SPICE3, also developed at UC Berkeley; HSPICE, developed by Meta-software and now owned by Avant!; PSPICE, developed by Micro-Sim; and SPECTRE, developed by Cadence. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators.


SPICE is a program widely used to simulate the performance of analog electronic systems and mixed mode analog and digital systems. SPICE solves sets of non-linear differential equations in the frequency domain, steady state and time domain and can simulate the behavior of transistor and gate designs. In SPICE, any circuit is handled in a node/element fashion; it is a collection of various elements (resistors, capacitors, etc.). These elements are then connected at nodes. Thus, each element must be modeled to create the entire circuit. SPICE has built in models for semiconductor devices, and is set up so that the user need only specify model parameter values.


An electronic circuit may contain any variety of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), and metal-on-silicon field effect transistors (MOSFET), etc. A SPICE circuit simulator makes use of built-in or plug-in models for semiconductor device elements such as diodes, BJTs, JFETs, and MOSFETs. If model parameter data is available, more sophisticated models can be invoked. Otherwise, a simpler model for each of these devices is used by default.


A model for a device mathematically represents the device characteristics under various bias conditions. For example, for a MOSFET device model, in DC and AC analysis, the inputs of the device model are the drain-to-source, gate-to-source, bulk-to-source voltages, and the device temperature. The outputs are the various terminal currents. A device model typically includes model equations and a set of model parameters. The model parameters, along with the model equations in the device model, directly affect the final outcome of the terminal currents. In order to represent actual device performance, a successful device model is tied to the actual fabrication process used to manufacture the device represented. This connection is represented by the model parameters, which are dependent on the fabrication process used to manufacture the device.


SPICE has a variety of preset models. However, in modern device models, such as BSIM (Berkeley Short-Channel IGFET Model) and its derivatives, BSIM3, BSIM4, and BSIMPD (Berkeley Short-Channel IGFET Model Partial Depletion), all developed at UC Berkeley, only a few of the model parameters can be directly measured from actual devices. The rest of the model parameters are extracted using nonlinear equations with complex extraction methods. See Daniel Foty, “MOSFET Modeling with Spice—Principles and Practice,” Prentice Hall PTR, 1997.


Since the sets of equations utilized in a modern semiconductor device model are complex with numerous unknowns, there is a need to extract the model parameters in the equations in an efficient and accurate manner so that using the extracted parameters, the model equations will closely emulate the actual process.


SUMMARY OF THE INVENTION

The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIM4 model. The device model parameters for the device model includes a plurality of base parameters, DC model parameters, temperature dependent related parameters, and AC parameters. The method includes steps for extracting the DC model parameters, such of Vth related parameters, Igb related parameters, Igidl related parameters, Igd and Igs related parameter, Leff, Rd and Rs related parameters, mobility and Weff related parameters, Vth geometry related parameters, sub-threshold region related parameters, drain induced barrier lower related parameters; Idsat related parameters, and additional DC related parameters, based on the terminal current data corresponding to various bias conditions measured from a set of test devices.


The present invention also includes a method for extracting device model parameters including the steps of extracting a portion of the DC model parameters based on the terminal current data, modifying the terminal current data based on the extracted portion of the DC model parameters, and extracting a second portion of the DC model parameters based on the modified terminal current data.




BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a block diagram of a system according to an embodiment of the present invention;



FIG. 2 is a flow chart illustrating a modeling process in accordance with an embodiment of the present invention;



FIG. 3A is a block diagram of a model definition input file in accordance with an embodiment of the present invention;



FIG. 3B is a block diagram of an object definition input file in accordance with an embodiment of the present invention;



FIG. 4 is a diagrammatic cross sectional view of a MOSFET device for which model parameters are extracted in accordance with an embodiment of the present invention;



FIG. 5 is a graph illustrating sizes of test devices used to obtain experimental data for model parameter extraction in accordance with an embodiment of the present invention;



FIG. 6 is a graph illustrating sizes of test devices used to obtain experimental data for model parameter extraction in accordance with an alternative embodiment of the present invention;



FIGS. 7A-7D are examples of current-voltage (I-V) curves representing some of the terminal current data for the test devices;



FIG. 8 is a flow chart illustrating in further detail a parameter extraction process in accordance with an embodiment of the present invention; and



FIG. 9 is a flow chart illustrating in further detail a DC parameter extraction process in accordance with an embodiment of the present invention.




DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 1, system 100, according to one embodiment of the invention, comprises a central processing unit (CPU) 102, which includes a RAM, and a disk memory 110 coupled to the CPU 102 through a bus 108. The system 100 further comprises a set of input/output (I/O) devices 106, such as a keypad, a mouse, and a display device, also coupled to the CPU 102 through the bus 108. The system 100 may further include an input port 104 for receiving data from a measurement device (not shown), as explained in more detail below. The system 100 may also include other devices 122. An example of system 100 is a Pentium 233 PC/Compatible computer having RAM larger than 64 MB and a hard disk larger than 1 GB.


Memory 110 has computer readable memory spaces such as database 114 that stores data, memory space 112 that stores operating system 112 such as Windows 95/98/NT4.0/2000, which has instructions for communicating, processing, accessing, storing and searching data, and memory space 116 that stores program instructions (software) for carrying out the method of the present invention. Memory space 116 may be further subdivided as appropriate, for example to include memory portions 118 and 120 for storing modules and plug-in models, respectively, of the software.


A set of model parameters for a semiconductor device is often referred to as a model card for the device. Together with the model equations, the model card is used by a circuit simulator to emulate the behavior of the semiconductor device in an integrated circuit. A model card may be determined by process 200 as shown in FIG. 2. Process 200 begins by loading 210 the input files into the RAM of the CPU 102. The input files may include a model definition file and an object definition file. The object definition file provides information of the object (device) to be simulated. The model definition file provides information associated with the device model for modeling the behavior of the object. These files are discussed in further detail below in conjunction with FIGS. 3A and 3B.


Next, the measurement data is loaded 220 from database 114. The measurement data includes physical measurements from a set of test devices, as will be explained in more detail below. Once the data has been loaded, the next step is extraction 230 of the model parameters. The parameter extraction step 230 is discussed in detail in connection with FIGS. 8, and 9 below.


After the parameters are extracted, binning 240 may be performed. Binning is an optional step depending on whether the device model is binnable or not. The next step is verification 250. Verification checks the quality of the extracted model parameters. Once verified, the extracted parameters are output 260 as model card, an error report is generated 270, and the process 200 is then complete. More detailed discussion about the binning step 240 and verification step 250 can be found in the BSIMPro+User Manual—Basic Operation, by Celestry Design Technologies, released in September, 2001, which is incorporated by reference in its entirety herein.


Referring to FIG. 3A, model definition file 300A comprises a general model information field 310, a parameter definition field 320, an intermediate variable definition field 330, and an operation point definition field 340. The general model information field 310 includes general information about the device model, such as model name, model version, compatible circuit simulators, model type and binning information. The parameter definition field 320 defines the parameters in the model. As an example, a list of the model parameters in the BSIM4 model are provided in Appendix A. For each parameter, the model definition file specifies information associated with the parameter, such as parameter name, default value, parameter unit, data type, and optimization information. The operation point definition section 340 defines operation point or output variables, such as device terminal currents, threshold voltage, etc., used by the model.


Referring to FIG. 3B, object definition file 300B defines object related information, including input variables 350, output variables 360, instance variables 370, object and node information 380. Input variables 350 and output variables 360 are associated with the inputs and outputs, respectively, of the device in an integrated circuit. The instance variables 370 are associated with the geometric characteristics of the device to be modeled. The object node information 380 is the information regarding the nodes or terminals of the device to be modeled.


Process 200 can be used to generate model cards for models describing semiconductor devices such as BJTs, JFETs, and MOSFETs, etc. Discussions about the use of some of these models can be found in the BSIMPro+User Manual—Device Modeling Guide, by Celestry Design Technologies, released in September, 2001, which is incorporated by reference in its entirety herein. As an example, the BSIM4 model, which was developed by UC Berkeley to model MOSFET devices, is used here to further describe the parameter extraction step 230 of the process 200. The model equations for the BSIM4 model are provided in Appendix B. More detailed discussion about the BSIM4 model can be found in the BSIM4.2.0 MOSFET Model Users' Manual by the Department of Electrical Engineering and Computer Sciences, UC Berkeley, Copyright 2001, which is incorporated by reference in its entirety herein.


Preferred embodiments of the present invention, thus may be further understood by reference to an exemplary parameter extraction process for a MOSFET device. As shown in FIG. 4, a MOSFET device 400 includes a source 430 and a drain 450 formed in a substrate 440. The MOSFET also includes a gate 410 over the substrate 440 and is separated from the substrate 440 by a thin layer of gate oxide 420.


The MOSFET as described can be considered a four terminal (node) device. The four terminals are the gate terminal (node g), the source terminal (node s), the drain terminal (node d), and the substrate or body terminal (node b). Nodes g, s, b, and d, can be connected to different voltage sources.


For ease of further discussion, Table I below lists the symbols corresponding to the physical variables associated with the operation of MOSFET device 400.

TABLE ICbd -body to drain capacitanceCbS -body to source capacitanceId -current through drain (d) nodeIdgidl -gate induced leakage current at the drainIds -current flowing from source to drainIdsat -drain saturation currentIb -current through substrate nodeIgb -gate oxide tunneling current to substrateIgs -current flowing from gate to sourceIgd -current flowing from gate to drainIgc -current flowing from gate to channelIsub -impact ionization currentIs -current through source (s) nodeLgisl -gate induced source leakage current at the sourceLdrawn -drawn channel lengthLeff -effective channel lengthRd -drain resistanceRs -source resistanceRds -drain/source resistanceRout -output resistanceVbs -voltage between node b and node sVd -drain voltageVDD -maximum operating DC voltageVds -voltage between node d and node sVb -substrate voltageVg -gate voltageVgs -voltage between node g and node sVs -source voltageVth -threshold voltageWdrawn -drawn channel widthWeff -effective channel width


In order to model the behavior of the MOSFET device 400 using the BSIM4 model, experimental data are used to extract model parameters associated with the model. These experimental data include terminal current data and capacitance data measured in test devices under various bias conditions. In one embodiment of the present invention, the measurement is done using a conventional semiconductor device measurement tool that is coupled to system 100 through input port 104. The measured data are thus organized by CPU 102 and stored in database 114. The test devices are typically manufactured using the same or similar process technologies for fabricating the MOSFET device. In one embodiment of the present invention, a set of test devices having different device sizes, meaning different channel widths and channel lengths are used for the measurement. The device size requirement can vary with different applications. Ideally, as shown in FIG. 5, the set of devices include:

    • one largest device, meaning the device with the longest drawn channel length and widest drawn channel width that is available, as represented by dot 502;
    • one smallest device, meaning the device with the shortest drawn channel length and smallest drawn channel width that is available, as represented by dot 516;
    • one device with the smallest drawn channel width and longest drawn channel length, as represented by dot 510;
    • one device with the widest drawn channel length and shortest drawn channel length, as represented by dot 520;
    • three devices having the widest drawn channel width and different drawn channel lengths, as represented by dots 504, 506, and 508;
    • two devices with the shortest drawn channel length and different drawn channel widths, as represented by dots 512 and 514;
    • two devices with the longest drawn channel length and different drawn channel widths, as represented by dots 522 and 524;
    • (optionally) up to three devices with smallest drawn channel width and different drawn channel lengths, as represented by dots 532, 534, and 536; and
    • (optionally) up to three devices with medium drawn channel width (about halfway between the widest and smallest drawn channel width) and different drawn channel lengths, as represented by dots 538, 540, and 542.


      If in practice, it is difficult to obtain measurements for all of the above required devices sizes, a smaller set of different sized devices can be used. For example, the different device sizes shown in FIG. 6 are sufficient according to an alternative embodiment of the present invention. The test devices as shown in FIG. 6 include:
    • one largest device, meaning the device with the longest drawn channel length and widest drawn channel width, as represented by dot 502;
    • one smallest device, meaning the device with the shortest drawn channel length and smallest drawn channel width, as represented by dot 516;
    • (optional) one device with the smallest drawn channel width and longest drawn channel length, as represented by dot 510;
    • one device with the widest drawn channel width and shortest drawn channel length, as represented by dot 520;
    • one device and two optional devices having the widest drawn channel width and different drawn channel lengths, as represented by dots 504 (optional), 506 (optional), and 508, respectively;
    • (optional) two devices with the shortest drawn channel length and different drawn channel widths, as represented by dots 512 and 514.


For each test device, terminal currents are measured under different terminal bias conditions. These terminal current data are put together as I-V curves representing the I-V characteristics of the test device. In one embodiment of the present invention, for each test device, the following I-V curves are obtained:

    • 1. Linear region Id vs. Vgs curves for a set of Vb values. These curves are obtained by grounding the s node, setting Vd to a low value, such as 0.05V, and for each of the set of Vb values, measuring Id while sweeping Vg in step values across a range such as from 0 to VDD. (−VDD for NMOS and VDD for PMOS).
    • 2. Saturation region Id vs. Vgs curves for a set of Vb values. These curves are obtained by grounding the s node, setting Vd to a high value, such as VDD, and for each of the set of Vb values, measuring Id while sweeping Vg in step values across a range such as from 0 to VDD. (−VDD for NMOS and VDD for PMOS).
    • 3. Saturation region Id VS Vds curves for a set of Vg values. These curves are obtained by grounding the s node, setting Vb to 0 and for each set of Vg values, measuring Id while sweeping Vd in step values across a range such as Vth+0.02 to VDD.
    • 4. Linear region Id vs Vds curves for a set of Vg values with substrate biased. These curves are obtained by grounding the s node, setting Vb to −VDD and for each set of Vg values, measuring Id while sweeping Vd in step values across a range such as Vth+0.02 to VDD.
    • 5. Ib vs. Vgs curves for different Vd values, obtained by grounding the s and b nodes, and for each of the set of Vd values, measuring Ib while sweeping Vg in step values across a range such as from 0 to VDD.
    • 6. Ig vs. Vbs curves obtained by grounding d, g, and s nodes, measuring Ig while sweeping Vb in step values across a range such as from −VDD to 0.7.
    • 7. Ig/Id/Is vs. Vgs curves for different Vd values, obtained by grounding s and b nodes, and for each of a set of Vd values sweeping Vg in step values across a range such as from 0 to VDD.
    • 8. Is vs. Vgd curves for different Vb and Vs values, obtained by grounding d node, and for each combination of Vb, and Vs values, measuring Is while sweeping Vg in step values across a range such as from 0 to −VDD.


As examples, FIG. 7A shows a set of linear region Id vs. Vgs curves for different Vbs values, FIG. 7B shows a set of saturation region Id vs. Vds curves for different Vgs values, FIG. 7C shows a set of Ig vs. Vgs curves for different Vds values; and FIG. 7D shows a set of Ig vs. Vgs curves for different Vbd values.


In addition to the terminal current data, for each test device, capacitance data are also collected from the test devices under various bias conditions. The capacitance data can be put together into capacitance-current (C-V) curves. In one embodiment of the present invention, the following C-V curves are obtained:

  • 1. Cbs VS. Vbs curve obtained by grounding s node, setting Id to zero, or to very small values, and measuring Cbs while sweeping Vb in step values across a range such as from −VDD to VDD.
  • 2. Cbd vs. Vbs curve obtained by grounding s node, setting Is to zero, or to very small values, and measuring Cbd while sweeping Vb in step values across a range such as from −VDD to VDD.


As shown in FIG. 8, in one embodiment of the present invention, the parameter extraction step 230 comprises extracting base parameters 810; extracting other DC model parameters 820; extracting temperature dependent related parameters 830; and extracting AC parameters 840. In base parameters extraction step 810, base parameters, such as Vth (the threshold voltage at Vbs=0), K1 (the first order body effect coefficient), and K2 (the second order body effect coefficient) are extracted based on process parameters corresponding to the process technology used to fabricate the MOSFET device to be modeled. The base parameters are then used to extract other DC model parameters at step 820, which is explained in more detail in connection with FIG. 9 below.


The temperature dependent parameters are parameters that may vary with the temperature of the device and include parameters such as: Kt1 (temperature coefficient for threshold voltage); Ua1 (temperature coefficient for Ua), and Ub1 (temperature coefficient for Ub), etc. These parameters can be extracted using a conventional parameter extraction method.


The AC parameters are parameters associated with the AC characteristics of the MOSFET device and include parameters such as: CLC (constant term for the short channel model) and moin (the coefficient for the gate-bias dependent surface potential), etc. These parameters can also be extracted using a conventional parameter extraction method.


As shown in FIG. 9, the DC parameter extraction step 820 further comprises: extracting Vth related parameters (step 902); extracting Igb related parameters (step 904); extracting Igidl related parameters (step 906); extracting Igd and Igs related parameters (step 908); extracting Igc and its partition (Igcs and Igcd) related parameters (step 910); extracting Leff related parameters, Rd related parameters, and Rs related parameters (step 912); extracting mobility related parameters and Weff related parameters (step 914); extracting Vth geometry related parameters (step 916); extracting sub-threshold region related parameters (step 918); extracting parameters related to drain-induced barrier lower than regular (DIBL) (step 920); extracting Idsat related parameters (step 922); extracting Isub related parameters (step 924); and extracting junction parameters (step 926).


The equation numbers below refer to the equations set forth in Appendix B.


In step 902, threshold voltage Vth related parameters, such as Vth0, k1, k2, and Ndep, are extracted by using the linear Id vs Vgs curves measured from the largest device.


In step 904, the tunneling current, Igb, related parameters are extracted. The tunneling current is comprised of two components as defined by the following equation:

Igb=Igbacc+Igbinv


Igbacc and Igbinv related parameters are extracted separately in step 904. For the extraction of Igbacc related parameters, the Ig vs. Vbs curves for Vds=0 and Vgs=0 are used. Vds and Vgs are set to zero to minimize the effects of other currents. Then model parameters Aigbacc, Bigbacc, and Cigbacc are extracted with nonlinear-square-fit, using Equation 4.3.1. Once these parameters are extracted, Nigbacc is obtained by linear interpolation of Equation 4.3.1b using maximum slope position in the Ig vs. Vbs curves.


For the extraction of Igbinv related parameters, the Ib vs. Vgs curves when Vds=0 and Vbs=0 are used. Vds and Vbs are set to zero to minimize the effects of other currents. Model parameters Aigbinv, Bigbinv, Cigbinv are then extracted with nonlinear-square-fit, using Equation 4.3.2. Then Nigbinv and Eigbinv are obtained using Equation 4.3.2a by conventional optimization methods such as the Newton-Raphson algorithm.


In step 906, Igidl-related parameters, such as parameters AGIDL, BGIDL, CGIDL, and EGIDL, are extracted. Igidl represents the gate-induced drain leakage current, and the parameters are extracted using the device with the maximum width, W, and data from the Id VS Vgs and Is vs Vgs curves measured at the condition of Vgs<0 for NMOS (Vgs>0 for PMOS) and at different Vds and Vbs bias conditions. Isub is negligible where Vgs<0 and therefore the Ib vs Vgs curve can be used for this extraction. These assumptions and curves are used in conjunction with the extracted Vth, related parameters from step 902 and the following equation:
IGIDL=AGIDL·WeffCJ·Nf·Vds-Vgse-EGIDL3·Toxe·exp(-3·Toxe·BGIDLVds-Vgse-EGIDL)·Vdb3CGIDL+Vdb3

CGIDL is extracted using the Ib vs Vgs curve data for varying Vds. Next AIGDL and BIGDL are extracted using a conventional non-linear square fit. Finally EGIDL is obtained by optimizing AGIDL, BGIDL, and EGIDL simultaneously using a conventional optimizer such as the Newton-Raphson algorithm.


In step 908, the gate to source, Igs, and gate to drain, Igd current parameters are extracted. Igs represents the gate tunneling current between the gate and the source diffusion region, Igd represents the gate tunneling current between the gate and the drain diffusion region. Parameters extracted in step 908 include DLCIG, AIGSD, BIGSD, and CIGSD. The values of the parameters POXEDGE, TOXREF, and NTOX are set to their default values. These parameters are extracted using the Id vs Vgs and Is vs Vgs curves measured at the condition of Vds=0 and Vbs=0. Vds and Vbs are set equal to zero to minimize the effects of other currents such as channel current. This extraction utilizes the device with the maximum Ldrawn*Wdrawn, where Ldrawn is the device channel length and Wdrawn is the device width, and the extracted Vth, related parameters from step 902.


The following equations are utilized:

Igs=WeffDLCIG·A·ToxRatioEdge·Vgs·V′gs·exp[−B·TOXE·POXEDGE·(AIGSD−BIGSD·V′gs)·(1+CIGSD·V′gs)]

and

Igd=WeffDLCIG·A·ToxRatioEdge·Vgd·V′gd·exp[−B·TOXE·POXEDGE·(AIGSD−BIGSD·V′gd)·(1+CIGSD·V′gd)]

where
ToxRatioEdge=(TOXREFTOXE·POXEDGE)NTOX·1(TOXE·POXEDGE)2

and

V′gs{square root}{square root over ((Vgs−Vfbsd)2+1.0e−4)}
Vgd={square root}{square root over ((Vgd−Vfbsd)2+1.0e−4)}

DLCIG is set equal to 0.7 *Xj which is a proven experimental value. Then AIGSD, BIGSD, and CIGSD are extracted from the Id/Is vs Vgs curve using the non-linear square fit method.


In step 910, the gate to current, Igc, and it's partition related parameters are extracted. Parameters extracted in step 910 includes: AIGC, BIGC, CIGC, NIGC and Pigcd. These parameters are extracted using the device with the maximum Ldrawn*Wdrawn and the data from the Ig vs Vgs curve measured at the condition of Vds=0 and Vbs=0. Vds and Vbs are set equal to zero to minimize the effects of other currents such as channel current. The data of Ig includes Igc, Igs and Igd data and is characterized by the following equation.

Ig=Igc+Igs+Igd

Since Igs and Igd are extracted in earlier steps, these effects can easily be removed with the calculated Igs and Igd. Igc is then calculated using the extracted Vth, related parameters from step 902, in coordination data from the Ig vs Vgs curve and the following equation:

Igc=WeffLeff·A·ToxRatio·VgseVaux·exp[−B·TOXE(AIGC−BIGC·Voxdepinv)·(1+CIGC·Voxdepinv)]

Where
Vaux=NIGC·vt·log(1+exp(Vgse-VTH0NIGC·vt))

Using a non-linear square fit, AIGC, BIGC, and CIGC are extracted. NIGC is then extracted at Vgs=Vth0 using linear interpolation.


Once calculated, Igc is then divided into its two components Igcs and IgcdIgcs=Igc·PIGCD·Vds+exp(-PIGCD·Vds)-1+1.0e-4PIGCD2·Vds2+2.0e-4Igcd=Igc·1-(PIGCD·Vds+1)·exp(-PIGCD·Vds)+1.0e-4PIGCD2·Vds2+2.0e-4

and


In step 912, parameters related to the effective channel length Leff, the drain resistance Rd and source resistance Rs are extracted. The Leff, Rd and Rs related parameters include parameters such as Lint, and Rdsw, and are extracted using data from the linear Id vs Vgs curves as well as the extracted Vth related parameters from step 902.


In step 914, parameters related to the mobility and effective channel width Weff, such as μ0, Ua, Ub, Uc, Wint, Wr, Prwb, Wr, Prwg, Rdsw, Dwg, and Dwb, are extracted, using the linear Id VS Vgs curves and the extracted Vth, related parameters from step 902.


Steps 902, 912, and 914 can be performed using a conventional BSIM4 model parameter extraction method. Discussions about some of the parameters involved in these steps can be found in the following:

    • Liu, William “MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4,” John Wiley & Sons, Inc. 2001


      which is incorporated by reference herein.


In step 916, the threshold voltage Vth geometry related parameters, such as DVT0, DVT1, DVT2, NLX1, DVT0W, DVT1W, DVT2W, k3, and k3b, are extracted, using the linear Id vs Vgs curve, the extracted Vth, Leff, and mobility and Weff related parameters from steps 902, 912, and 914, and Equations 2.5.5-2.5.7.


In step 918, sub-threshold region related parameters, such as Cit, Nfactor, Voff, Ddsc, and Cdscd, are extracted, using the linear Id vs Vgs curves, the extracted Vth, Leff and Rd and Rs and mobility and Weff related parameters from steps 902, 912, and 914, and Equations (3.2.1-3.2.3.


In step 920, DIBL related parameters, such as Dsub, Eta0 and Etab, are extracted, using the saturation Id vs Vgs curves and the extracted Vth related parameters from step 902, and Equations 2.5.5-2.5.7.


In step 922, the drain saturation current Idsat related parameters, such as B0, B1, A0, Keta, and Ags, are extracted using the saturation Id VS Vds curves, the extracted Vth, Leff and Rd and Rs, mobility and Weff, Vth geometry, sub-threshold region, and DIBL related parameters from steps 902, 912, 914, 916, 918, and 920 and Equation 14.1.


In step 924, the impact ionization current Iii related parameters, such as α0, α1, and β0, are extracted using the data from the linear Id VS Vgs curve and Equations 6.1.1-6.1.2.


In step 926, the junction parameters, such as Cjswg, Pbswg, and Mjswg, are extracted using the Cbs VS. Vbs and Cbd vs. Vbs curves, and Equations 10.2.1-10.2.7.


In performing the DC parameter extraction steps (steps 902-926), it is preferred that after the Igb, Igd, Igs Igidl, and Igc related parameters are extracted in steps 904 through 910, Igb, Igd, Igs, Igidl, and Igc are calculated based on these parameters and the model equations. This calculation is done for the bias condition of each data point in the measured I-V curves. The I-V curves are then modified for the first time based on the calculated Igb, Igd, Igs, Igidl, and Igc values. In one embodiment of the present invention, the I-V curves are first modified by subtracting the calculated Igb, Igd, Igs, Igidl, and Igc values from respective Is, Id, and Ib data values. For example, for a test device having drawn channel length Ldrn and drawn channel width Wdrn, if under bias condition where Vs=VsT, Vd=VdT, Vp=VpT, Ve=VeT, and Vg=VgT, the measured drain current is IdT, then after the first modification, the drain current will be Idfirst-modified=IdT−IgdT−IgidlT where IgdT and IgidlT, are calculated respectively, for the same test device under the same bias condition. The first-modified I-V curves are then used for additional DC parameter extraction. This results in higher degree of accuracy in the extracted parameters. In one embodiment the Igb, Igd, Igs, Igidl and Igc related parameters are extracted before extracting other DC parameters, so that I-V curve modification may be done for more accurate parameter extraction. However, if such accuracy is not required, one can choose not to do the above modification and the Igb, Igd, Igs, Igidl, and Igc related parameters can be extracted at any point in the DC parameter extraction step 820.


The forgoing descriptions of specific embodiments of the present invention are presented for purpose of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. Furthermore, the order of the steps in the method are not necessarily intended to occur in the sequence laid out. It is intended that the scope of the invention be defined by the following claims and their equivalents.

APPENDIX AParameter ListParameterDefaultnameDescriptionvalueBinnable?NoteA.1 BSIM 4.0.0 Model Selectors/Controllers(LEVELSPICE3 model selector14NABSIM4SPICE3also set asparameter)the defaultmodel inSPICE3VERSIONModel version number4.0.0NABerkeleyLatestofficialreleaseBINUNITBinning unit selector1NAPARAMCHKSwitch for parameter value check1NAParameterscheckedMOBMODMobility model selector0NARDSMODBias-dependent source/drain0NARds(V)resistance model selectormodeledinternallythrough IVequationIGCMODGate-to-channel tunneling current0NAOFFmodel selectorIGBMODGate-to-substrate tunneling current0NAOFFmodel selectorCAPMODCapacitance model selector2NARGATEMODGate resistance model selector0(Also an(no gateinstanceresistance)parameter)RBODYMODSubstrate resistance network model0NA(Also anselector(networkinstanceoff)parameter)TRNQSMODTransient NQS model selector0NAOFF(Also aninstanceparameter)ACNQSMODAC small-signal NQS model0NAOFF(Also anselectorinstanceparameter)FNOIMODFlicker noise model selector1NATNOIMODThermal noise model selector0NADIOMODSource/drain junction diode IV1NAmodel selectorPERMODWhether PS/PD (when given)1NAincludes the gate-edge perimeter(includingthe gate-edgeperimeter)GEOMODGeometry-dependent parasitics0NA(Also anmodel selector - specifying how the(isolated)instanceend S/D diffusions are connectedparameter)RGEOMODSource/drain diffusion resistance0NA(Instanceand contact model selector -(no S/Dparameterspecifying the end S/D contact type:diffusiononly)point, wide or merged, and howresistance)S/D parasitics resistance iscomputedA.2 Process ParametersEPSROXGate dielectric constant relative to3.9 (SiO2)NoTypicallyvacuumgreaterthan orequal to3.9TOXEElectrical gate equivalent oxide3.0e−9mNoFatalenothicknessr if notpositiveTOXPPhysical gate equivalent oxideTOXENoFatalerrothicknessr if notpositiveTOXMTox at which parameters are extractedTOXENoFatalerror ifnotpositiveDTOXDefined as (TOXE-TOXP)0.0 mNoXJS/D junction depth1.5e−7mYesGAMMA1Body-effect coefficient near the surfacecalculatedV1/2Note-1(λ1 incalculatedequation)GAMMA2Body-effect coefficient in the bulkcalculatedV1/2Note-1(λ1 inequation)NDEPChannel doping concentration at1.7e17cm3YesNote-2depletion edge for zero body biasNSUBSubstrate doping concentration6.0e16cm3YesNGATEPoly Si gate doping concentration0.0 cm−3YesNSDSource/drain doping concentrationFatal1.0e20cm−3Yeserror if not positiveVBXVb s at which the depletion regioncalculatedNoNote-3width equalsXT(V)XTDoping depth1.55e−7mYesRSHSource/drain sheet resistance0.0 ohm/NoShouldsquarenot benegativeRSHGGate electrode sheet resistance0.1 ohm/NoShouldsquarenot benegativeA.3 Basic Model ParametersVTH0 orLong-channel threshold voltage at0.7 VYesNote-4VTHOVbs = 0(NMOS)−0.7 V(PMOS)VEBFlat-band voltage−1.0 VYesNote-4PHLNNon-uniform vertical doping effect on0.0 VYessurface potentialK1First-order body bias coefficient0.5 V1/2YesNote-5K2Second-order body bias coefficient0.0YesNote-5K3Narrow width coefficient80.0YesK3BBody effect coefficient of K30.0 V−1YesW0Narrow width parameter2.5e−6mYesLPE0Lateral non-uniform doping parameter1.74e−7mYesat VbS = 0LPEBLateral non-uniform doping effect on0.0 mYesK1VBMMaximum applied body bias in VTHO−3.0 VYescalculationDVT0First coefficient of short-channel effect2.2Yeson VthDVT1Second coefficient of short-channel0.53Yeseffect on VthDVT2Body-bias coefficient of short-channel−0.032 V −1Yeseffect on VthDVTPOFirst coefficient of drain-induced Vth0.0 mYesNotshift due to for long-channel pocketmodeledbinned devicesifbinnedDVTPO<=0.0DVTP1First coefficient of drain-induced Vth0.0 V−1Yeschist due to for long-channel pocketdevicesBasic Model ParametersDVT0WFirst coefficient of narrow width effect0.0Yeson Vth for small channel lengthDVT1WSecond coefficient of narrow width5.3e6m−1Yeseffect on Vth for small channel lengthDVT2WBody-bias coefficient of narrow width−0.032 V−1Yeseffect for small channel lengthU0Low-field mobility0.067Yesm2/(Vs)(NMOS);0.025m2/(Vs)PMOSUACoefficient of first-order mobility1.0e−9 m/VYesdegradation due to vertical field forMOBMOD =0 and 1;1.0e−15 m/VforMOBMOD = 2UBCoefficient of secon-order mobility1.0e−19 m2/V2Yesdegradation due to vertical fieldUCCoefficient of mobility degradation−0.0465 V−1Yesdue to body-bias effectfor MOB-MOD = 1;−0.0465e−9m/V2 forMOBMOD =0 and 2EUExponent for mobility degradation of1.67MOBMOD = 2(NMOS);1.0(PMOS)VSATSaturation velocity8.0e4m/sYesA0Coefficient of channel-length1.0Yesdependence of bulk charge effectAGSCoefficient of Vgs dependence of bulk0.0 V−1Yescharge effectB0Bulk charge effect coefficient for0.0 mYeschannel widthB1Bulk charge effect width offset0.0 mYesKETABody-bias coefficient of bulk charge—0.047 V−1YeseffectA1First non-saturation effect parameter0.0 V−1YesA2Second non-saturation factor1.0YesWINTChannel-width offset parameter0.0 mNoLINTChannel-length offset parameter0.0 mNoDWGCoefficient of gate bias dependence of0.0 m/VYesWeffDWBCoefficient of body bias dependence of0.0 m/V1/2YesWeffVOFFOffset voltage in subtbreshold−0.08 VYesregion for large W and LVOFFLChannel-length dependence of VOFF0.0 mVNoMINVVgsteff fitting parameter for moderate0.0Yesinversion conditionNFACTORSubthreshold swing factor1.0YesETA0DIBL coefficient in subthreshold region0.08YesETABBody-bias coefficient for the−0.07 V−1Yessubthreshold DTBL effectDSUBDIBL coefficient exponent inDROUTYessubthreshold regionCITInterface trap capacitance0.0 F/m2YesCDSCcoupling capacitance between2.4e−4F/m2Yessource/drain and channelCDSCBBody-bias sensitivity of Cdsc0.0F/(Vm2)YesCDSCDDrain-bias sensitivity of CDSC0.0(F/Vm2)YesPCLMChannel length modulation parameter1.3YesPDIBLC1Parameter for DIBL effect on Rout0.39YesPDIBLC2Parameter for DIBL effect on Rout0.0086YesPDIBLCBBody bias coefficient of DIBL effect on0.0V−1YesRoutDROUTChannel-length dependence of DIBL0.56Yeseffect on RoutPSCBE1First substrate current induced body-4.24e8VmYeseffect parameterPSCBE2Second substrate current induced body-1.0e−5m/VYeseffect parameterPVAGGate-bias dependence of Early voltage0.0YesDELTAParameter for DC Vdseff0.01VYes(δ inequation)FPROUTEffect of pocket implant on Rout0.0 V/m0.5YesNotdegradationmodeledif binnedFPROUTnotpositivePDITSImpact of drain-induced Vth shift on0.0 V−1YesNot modeledRoutif RoutbinnedPDITS =0;Fatalerror ifbinnedPDITSnegativePDITSLChannel-length dependence of drain-0.0 mNoFatalinduced Vth shift for Routerror ifPDITSLnegativePDITSDVds dependence of drain-induced VthYesshift for RoutA.4 Parameters for Asymmetric and Bias-Dependent Rds ModelRDSWZero bias LDD resistance per unit width200.0YesIffor RDSMOD = 0ohmnegative,(μm)WRreset to0.0RDSWMINLDD resistance per unit width at0.0Nohigh Vgs and zero Vbsohmfor RDSMOD = 0(μm)WRRDWZero bias lightly-doped drain resistance100.0YesRd(V) per unit width for RDS-MOD = 1ohm(μm)WRRDWMINLightly-doped drain resistance per unit0.0Nowidth at high Vgs and zero Vbs forohmRDSMOD = 1(μm)WRRSWZero bias lightly-doped source100.0Yesresistance Rs(V) per unitohmwidth for RDS-MOD = 1(μm)WRRSWMINLightly-doped source resistance per unit0.0Nowidth at high Vgs and zero Vbs forRDSMOD = 1PRWGGate-bias dependence of LDD1.0 V−1YesresistancePRWBBody-bias dependence of LDD0.0 V−0.5YesresistanceWRChannel-width dependence parameter of1.0YesLDD resistanceNRSNumber of source diffusion square1.0No(instanceparameteronly)NRDNumber of drain diffusion squares1.0No(instanceparameteronly)ALPHA0First parameter of impact ionization0.0 Am/VYescurrentALPHA1Isub parameter for length scaling0.0 A/VYesBETA0The second parameter of impact30.0 VYesionization currentA.6 Gate-Induced Drain Leakage Model ParametersAGIDLPre-exponential coefficient for GLDL0.0 mhoYesIgidl = 0.0if binnedAGIDL =0.0BGIDLExponential coefficient for GIDL2.3e9 V/m YesIgidl = 0.0if binnedBGIDL =0.0CGIDLParamter for body-bias effect on GIDL0.5 V3YesDGIDLFitting parameter for band bending for0.8 VYesGIDLA.7 Gate Dielectric Tunneling Current Model ParametersAIGBACCParameter for Igb in accumulation0.43Yes(Fs2/g)0.5m−1BIGBACCParameter for Igb in accumulation0.054Yes(Fs2/g)0.5m−1V−1CIGBACCParameter for Igb in accumulation0.075 V−1YesNIGBACCParameter for Igb in accumulation1.0YesFatal errorif binnedvalue notpositiveAIGBINVParameter for Igb in inversion0.35Yes(Fs2/g)0.5m−1BIGBINVParameter for Igb in inversion0.03Yes(Fs2/g)0.5CIGBINVParameter for Igb in inversion0.006 V−1YesEIGBINVParameter for Igb in inversion1.1 VYesNIGBINVParameter for Igb in inversion3.0YesFatal errorif binnedvalue notpositiveAIGCParameter for Igcs and Igcd0.054Yes(NMOS) and0.31(PMOS)(Fs2/g)0.5m−1BIGCParameter for Igcs and Igcd0.054Yes(NMOS) and0.024(PMOS)(Fs2/g)0.5m−1V−1CIGGParameter for Igcs and Igcd0.075Yes(NMOS) and0.03(PMOS) V−1AIGSDParameter for Igs and Igd0.43Yes(NMOS) and0.31(PMOS)(Fs2/g)0.5m−1BIGSDParameter for Igs and Igd0.054Yes(NMOS) and0.024(PMOS)(Fs2/g)0.5m−1V−1CIGSDParameter for Igs and Igd0.075Yes(NMOS) and0.03(PMOS) V−1DLCIGSource/drain overlap length for IgsLINTYesand IgdNIGCParameter for Igcs, Igcd, Igs and Igd1.0YesFatal errorif binnedvalue notpositivePOXEDGEFactor for the gate oxide thickness in1.0YesFatal errorsource/drain overlap regionsif binnedvalue notpositivePIGCDVds dependence of Igcs and Igcd1.0YesFatal errorif binnedvalue notpositiveNTOXExponent for the gate oxide ratio1.0YesTOXREFNominal gate oxide thickness for gate3.0e−9mNoFatal errordielectric tunneling current modelif not positiveonlyA.8 Charge and Capacitance Model ParametersXPARTCharge partition parameter0.0NoCGSONon LDD region source-gate overlapcalculatedNoNote-6capacitance per unit channel width(F/m)CGDONon LDD region drain-gate overlapcalculatedNoNote-6capacitance per unit channel width(F/m)CGBOGate-bulk overlap capacitance per0.0F/mNote-6unit channel lengthCGSLOverlap capacitance between gate and0.0 F/mYeslightly-doped source regionCGDLOverlap capacitance between gate and0.0 F/mYeslightly-doped source regionCKAPPASCoefficient of bias-dependent overlap0.6 VYescapacitance for the source sideCKAPPADCoefficient of bias-dependent overlapCKAPPASYescapacitance for the drain sideCFFringing field capacitancecalculatedYesNote-7(F/m)CLCConstant term for the short channel1.0e−7mYesmodelCLEExponential term for the short channel0.6YesmodelDLCChannel-length offset parameter forLINT (m)NoCV modelDWCChannel-width offset parameter forWINT (m)NoCV modelVFBCVFlat-band voltage parameter (for—1.0 VYesCAPMOD = 0 only)NOFFCV parameter in Vgsteff,CV for weak to1.0Yesstrong inversionVOFFCVCV parameter in Vgsteff,CV for week to0.0 VYesstrong inversionACDEExponential coefficient for charge1.0 m/VYesthickness in CAPMOD = 2 for accumu-lation and depletion regionsMOINCoefficient for the gate-bias depen-15.0Yesdent surface potentialA.9 High-Speed/RF Model ParametersXRCRG1Parameter for distributed channel-12.0YesWarningresistance effect for both intrinsic-messageinput resistance and charge-deficitissued ifNQS modelsbinnedXRCRG1<=0.0XRCRG2Parameter to account for the excess1.0Yeschannel diffusion resistance for bothintrinsic input resistance and charge-deficit NQS modelsRBPBResistance connected between50.0 ohmNoIf less than(Also anbNodePrime and bNode1.0e−3ohm,instancereset toparameter)1.0e−3ohmRBPDResistance connected between50.0 ohmNoIf less than(Also anbNodePrime and dbNode1.0e−3ohm,instancereset toparameter)1.0e−3ohmRBPSResistance connected between50.0 ohmNoIf less than(Also anbNodePrime and sbNode1.0e−3ohm,instancereset toparameter)1.0e−3ohmRBDBResistance connected between50.0 ohmNoIf less than(Also andbNode and bNode1.0e−3ohm,instancereset toparameter)1.0e−3ohmRBSBResistance connected between50.0 ohmNoIf less than(Also ansbNode and bNode1.0e−3ohm,instancereset toparameter)1.0e−3ohmGBMINConductance in parallel with each of1.0e−12mhoNoWarningthe five substrate resistances to avoidmessagepotential numerical instability due toissued ifunreasonably too large a substrateless thanresistance1.0e−20mhoA.10 Flicker and Thermal Noise Model ParametersNOIAFlicker noise parameter A6.25e41No(eV)−1s1−EFm−3for NMOS;6.188e40(eV)−1s1−EFm−3for PMOSNOIBFlicker noise parameter B3.125e26No(eV)−1s1−EFm−1for NMOS;1.5e25(eV)−1s1−EFm−1for PMOSNOICFlicker noise parameter C8.75No(eV)−1s1−EFmEMSaturation field4.1e7V/mNoAFFlicker noise exponent1.0NoEFFlicker noise frequency exponent1.0NoKYFlicker noise coefficient0.0NoA2−EFs1−EFFNTNOINoise factor for short-channel devices1.0Nofor TNOIMOD = 0 onlyTNOIACoefficient of channel-length depen-1.5Nodence of total channel thermal noiseTNOIBChannel-length dependence parameter3.5Nofor channel thermal noise partitioningA.11 Layout-Dependent Parasitics Model ParametersDMCGDistance from S/D contact center to0.0 mNothe gate edgeDMCIDistance from S/D contact center toDMCGNothe isolation edge in the channel-length directionDMDGSame as DMCG but for merged0.0 mNodevice onlyDMCGTDMCG of test structures0.0 mNoNFNumber of device fingers1NoFatal error(instanceif less thanparameteroneonly)DWJOffset of the S/D junction widthDWC (inNoCVmodel)MINWhether to minimize the number of0No(instancedrain or source diffusions for even-(minimizeparameternumber fingered devicethe drain dif-only)fusion number)XGWDistance from the gate contact to the0.0 mNochannel edgeXGLOffset of the gate length due to varia-0.0 mNotions in patterningXLChannel length offset due to mask/0.0 mNoetch effectXWChannel width offset due to mask/etch0.0 mNoeffectNGCONNumber of gate contacts1NoFatal errorif less thanone; if notequal to Ior 2, warn-ing mes-sage issuedand reset to 1A.12 Asymmetric Source/Drain Junction Diode Model Parameters(separate forsource and drainside as indicatedin the names)IJTHSREVLimiting current in reverse bias regionIJTHSREV =NoIf not posi-IJTHDREV0.1 Ative, resetIJTHDREV =to 0.1 AIJTHSREVIJTHSFWDLimiting current in forward biasIJTHSFWD =NoIf not posi-IJTHDFWDregion0.1 Ative, resetIJTHDFWD =IJTHSFWDXJBVSFitting parameter for diode break-XJBVS = 1.0NoNote-8XJBVDdownXJBVD =XJBVSBVSBreakdown voltageBVS = 10.0 VNoIf not posiBVDBVD = BVStive, resetto 10.0 VJSSBottom junction reverse saturationJSS =NoJSDcurrent density1.0e−4 A/m2JSD = JSSJSWSIsolation-edge sidewall reverse satura-JSWS =NoJSWDtion current density0.0 A/mJSWD =JSWSJSWGSGate-edge sidewall reverse saturationJSWGS =NoJSWGDcurrent density0.0 A/mJSWGD =JSWGSCJSBottom junction capacitance per unitCJS = 5.0e−4NoCJDarea at zero biasF/m2CJD = CJSMJSBottom junction capacitance gratingMJS = 0.5NoMIDcoefficientMJD = MJSMJSWSIsolation-edge sidewall junctionMJSWS =NoMJSWDcapacitance grading coefficient0.33MJSWD =MJSWSCJSWSIsolation-edge sidewall junctionCJSWS =NoCJSWDcapacitance per unit area5.0e−10F/mCJSWD =CJSWSCJSWGSGate-edge sidewall junction capaci-CJSWGS =NoCJSWGDtance per unit lengthCJSWSCJSWGD =CJSWSMISWGSGate-edge sidewall junction capaci-MJSWGS =NoMJSWGDtance grading coefficientMJSWSMJSWGD =MJSWSPBBottom junction bnilt-in potentialPBS = 1.0 VNoPBD = PBSPBSWSIsolation-edge sidewall junction built-PBSWS =NoPBSWDin potential1.0 VPBSWD =PBSWSPBSWGSGate-edge sidewall junction built-inPBSWGS =NoPBSWGDpotentialPBSWSPBSWGD =PBSWSA.13 Temperature Dependence ParametersTNOMTemperature at which parameters are27° C.NoextractedUTEMobility temperature exponent−1.5YesKT1Temperature coefficient for threshold−0.11 VYesvoltageKT1LChannel length dependence of the0.0 VmYestemperature coefficient for thresholdvoltageKT2Body-bias coefficient of Vth tempera-0.022Yesture effectUA1Temperature coefficient for UA1.0e−9m/VYesUBITemperature coefficient for UB−1.Oe−18Yes(m/V)2UC1Temperature coefficient for UC0.067 V−1 forYesMOBMOD = 1;0.025 m/V2for MOBMOD =0 and 2ATTemperature coefficient for satura-3.3e4m/sYestion velocityPRTTemperature coefficient for Rdsw0.0 ohm-mYesNIS, NJDEmission coefficients of junction forNJS = 1.0;Nosource and drain junctions, respec-NJD = NJStivelyXTIS, XTIDJunction current temperature expo-XTIS = 3.0;Nonents for source and drain junctions,XTID = XTISrespectivelyTPBTemperature coefficient of PB0.0 V/KNoTPBSWTemperature coefficient of PBSW0.0 V/KNoTPBSWGTemperature coefficient of PBSWG0.0 V/KNoTCJTemperature coefficient of CJ0.0 K−1NoTCJSWTemperature coefficient of CJSW0.0 K−1NoTCJSWGTemperature coefficient of CJSWG0.0 K−1NoA.14 dW and dL ParametersWLCoefficient of length dependence for0.0 mWLNNowidth offsetWLNPower of length dependence of width1.0NooffsetWWCoefficient of width dependence for0.0 mWWNNowidth offsetWWNPower of width dependence of width1.0NooffsetWWLCoefficient of length and width cross0.0Noterm dependence for width offsetmWWN+WLNLLCoefficient of length dependence for0.0 mLLNNolength offsetLLNPower of length dependence for1.0Nolength offsetLWCoefficient of width dependence for0.0 mLWNNolength offsetLWNPower of width dependence for length1.0NooffsetLWLCoefficient of length and width cross0.0Noterm dependence for length offsetmLWN+LLNLLCCoefficient of length dependence forLLNoCV channel length offsetLWCCoefficient of width dependence forLWNoCV channel length offsetLWLCCoefficient of length and width cross-LWLNoterm dependence for CV channellength offsetWLCCoefficient of length dependence forWLNoCV channel width offsetWWCCoefficient of width dependence forWWNoCV channel width offsetWWLCCoefficient of length and width cross-WWLNoterm dependence for CV channelwidth offsetNOTES:Note-1:If γ1 is not given, it is calculated byγ1=2qɛsiNDEPCoxeIf γ2 is not given, it is calculated byγ2=2qɛsiNSUBCoxeNote-2:If NDEP is not given and γ1 is given, NDEP is calculated fromNDEP=γ12Coxe22qɛsiIf both γ1 and NDEP are not given, NDEP defaults to 1.7e17 cm−3and γ1 is calculated from NDEP.Note-3:If VBX is not given, it is calculated byqNDEP·XT22ɛsi=Φs-VBXNote-4:If VTH0 is not given, it is calculated byVTH0=VFB+Φs+K1Φs-Vbswhere VFB = −1.0. If VTH0 is given, VFB defaults toVFB=VTH0-Φs-K1Φs-VbsNote-5:If K1 and K2 are not given, they are calculated byK1=γ2-2K2Φs-VBMK2=(γ1-γ2)(Φs-VBX-Φs)2Φs(Φs-VBM-Φs)+VBMNote-6:If CGSO is not given, it is calculated byIf(DLC is given and > 0.0)CGSO = DLC · Coxe − CGSLif (CGSO < 0.0), CGSO = 0.0ElseCGSO = 0.6 · XJ · CoxeIf CGDO is not given, it is calculated byIf(DLC is given and > 0.0)CGDO = DLC · Coxe − CGDLif(CGDO < 0.0), CGDO = 0.0ElseCGDO = 0.6 · XJ · CoxeIf CGBO is not given, it is calculated byCGBO = 2 · DWC · CoxeNote-7:If CF is not given, it is calculated byCF=2·EPSROX·ɛ0π·log(1+4.0e-7TOXE)Note-8:For dioMod = 0, if XJBVS < 0.0, it is reset to 1.0.For dioMod = 2, if XJBVS <= 0.0, it is reset to 1.0.For dioMod = 0, if XJBVD < 0.0, it is reset to 1.0.For dioMod = 2, if XJBVD <= 0.0, it is reset to 1.0.


Poly Silicon Gate Depletion
Vpoly=0.5XpolyEpoly=qNGATE·Xpoly22ɛsi(1.2.1)EPSROX·Eox=ɛsiEpoly=2qɛsiNGATE·Vpoly(1.2.2)Vgs-VFB-Φs=Vpoly+Vox(1.2.3)a(Vgs-VFB-Φs-Vpoly)2-Vpoly=0(1.2.4)
Vgs−VFB−Φs=VpolyVox  (1.2.3)

a(Vgs−VFB−Φs−Vpoly)2Vpoly=0  (1.2.4)

where
a=EPSROX22qɛsiNGATE·TOXE2(1.2.5)Vgse=VFB+Φs+qɛsiNGATE·TOXE2EPSROX2(1.2.6)(1+2EPSROX2(Vgs-VFB-Φs)qɛsiNGATE·TOXE2-1)

Effective Channel Length and Width
Leff=Ldrawn+XL-2dL(1.3.1)Weff=WdrawnNF+XW-2dW(1.3.2a)Weff=WdrawnNF+XW-2dW(1.3.2b)dW=dW+DWG·Vgsteff+DWB(Φs-Vbseff-Φs)(1.3.3)dW=WINT+WLLWLN+WWWWWN+WWLLWLNWWWNdL=LINT+LLLLLN+LWWLWN+LWLLLLNWLWN(1.3.4)Lactive=Ldrawn+XL-2dL(1.3.5)Wactive=WdrawnNF+XW-2dW(1.3.6)dL=DLC+LLCLLLN+LWCWLWN+LWLCLLLNWLWN(1.3.7)dW=DWC+WLCLWLN+WWCWWWN+WWLCLWLNWWWN(1.3.8)Weffcj=WdrawnNF-(1.3.9)2·(DWJ+WLCLWLN+WWCWWWN+WWLCLWLNWWWN)

Long Channel Model with Uniform Doping
Vth=VFB+Φs+γΦs-Vbs(2.1.1)=VTH0+γ(Φs-Vbs-Φs)γ=2qɛsiNsubstrateCoxe(2.1.2)

Long Channel Model with Non-Uniform Doping
Vth=Vth,NDEP+qD0Coxe+K1NDEP(φs-Vbs-qD1ɛsi-φs-Vbs)(2.2.1)
    • where K1NDEP is the body-bias coefficient for Nsubstrate=NDEP,

      Vth,NDEP=VTH0+K1NDEP({square root}{square root over (φs−Vbs)}−{square root}{square root over (φs)})  (2.2.2)

      with a definition of
      ψs=0.4+kBTqln(NDEPni)(2.2.3)D0=D00+D01=0Xdep0(N(x)-NDEP)x+Xdep0Xdep(N(x)-NDEP)x(2.2.4)D1=D10+D11=0Xdep0(N(x)-NDEP)xx+xdep0Xdep(N(x)-NDEP)xx(2.2.5)Vth=VTH0+K1(Φs-Vbs-Φs)-K2·Vbs(2.2.6)
      Vth=VTH0+K1({square root}{square root over (Φs−Vbs)}−{square root}{square root over (Φs)})−KVbs  (2.2.6)


      where K2=qC01/Coxe, and the surface potential is defined as
      Φs=0.4+kBTqln(NDEPni)+PHIN(2.2.7)

      where

      PHIN=−qD10si
      K1=γ2−2K2{square root}{square root over (Φs−VBM)}  (2.2.8) PHIN=-qD10/ɛsiK1=γ2-2K2Φs-VBM(2.2.8)K2=(γ1-γ2)(Φs-VBX-Φs)2Φs(Φs-VBM-Φs)+VBM(2.2.9)γ1=2qɛsiNDEPCoxe(2.2.10)γ2=2qɛsiNSUBCoxe(2.2.11)qNDEP·XT22ɛsi=Φs-VBX(2.2.12)

      Non-Uniform Lateral Doping
      Vth=VTH0+K1(Φs-Vbs-Φs)·1+LPEBLeff-K2·Vbs+K1(1+LPE0Leff-1)Φs(2.3.1)ΔVth(DITS)=-nvt·ln((1--Vds/vt)·LeffLeff+DVTP0·(1+-DVTP1·Vds))(2.3.2)ΔVth(DITS)=-nvt·ln(LeffLeff+DVTP0·(1+-DVTP1·Vds))(2.3.3)

      Short-Channel and DIBL Effect

      ΔVth(SCE,DIBL)=−θth(Leff)·[2(Vbi−Φs)+Vds]  (2.4.1) ΔVth(SCE,DIBL)=-θth(Leff)·[2(Vbi-Φs)+Vds](2.4.1)Vbi=kBTqln(NDEP·NSDni2)(2.4.2)θth(Leff)=0.5cosh(Lefflt)-1(2.4.3)lt=ɛsi·TOXE·XdepEPSROX·η(2.4.4)Xdep=2ɛsi(Φs-Vbs)qNDEP(2.4.5)θth(Leff)=exp(-Leff2lt)+2exp(-Lefflt)(2.4.6)θth(SCE)=0.5·DVT0cosh(DVT1·Lefflt)-1(2.4.7)ΔVth(SCE)=-θth(SCE)·(Vbi-Φs)(2.4.8)lt=ɛsi·TOXE·XdepEPSROX·(1+DVT2·Vbs)(2.4.9)θth(DIBL)=0.5cosh(DSUB·Lefflt0)-1(2.4.10)ΔVth(DIBL)=-θth(DIBL)·(ETA0+ETAB·Vbs)·Vds(2.4.11)lt0=ɛsi·TOXE·Xdep0EPSROX(2.4.12)Xdep0=2ɛsiΦsqNDEP(2.4.13)

      Narrow Width Effect
      πqNDEP·Xdep,max22CaxeWeff=3πTOXEWeffΦs(2.5.1)ΔVth(Narrow_width1)=(K3+K3B·Vbs)TOXEWeff+W0Φs(2.5.2)ΔVth(Narrow_width2)=-0.5·DVT0Wcosh(DVT1W·LeffWeffltw)-1·(Vbi-Φs)(2.5.3)ltw=ɛsi·TOXE·XdepEPSROX·(1+DVT2W·Vbs)(2.5.4)Vth=VTH0+(K1ox·Φs-Vbseff-K1·Φs)1+LPEBLeff-K2oxVbseff+K1ox(1+LPE0Leff-1)Φs+(K3+K3B·Vbseff)TOXEWeff+W0Φs-0.5·[DVT0Wcosh(DVT1WLeffWeffltw)-1+DVT0cosh(DVT1Lefflt)-1](Vbi-Φs)-0.5cosh(DSUBLefflt0)-1(ETA0+ETAB·Vbseff)·Vds(2.5.5)K1ox=K1·TOXETOXM(2.5.6)andK2ox=K2·TOXETOXM(2.5.7)Vbseff=Vbc+0.5·[(Vbs-Vbc-δ1)+(Vbs-Vbc-δ1)2-4δ1·Vbc](2.5.8)Vbc=0.9(Φs-K124K22)(2.5.9)

      Channel Charge Model
      Qchsubs0=qNDEPɛsi2Φsvt·exp(Vgse-Vth-Voffnvt)(3.1.1)

      where
      Voff=VOFF+VOFFLLeff(3.1.1a)Qchs0=Coxe·(Vgse-Vth)(3.1.2)Qch0=Coxeff·Vgsteff(3.1.3)Coxeff=Coxe·CcenCaxe+CcenwithCcen=ɛxiXDC(3.1.4)XDC=1.9×10-9cm1+(Vgsteff+4(VTH0-VFB-Φs)2TOXP)0.7(3.1.5)Vgsteff=nvtln{1+exp[m*(Vgse-Vth)nvt]}m*+nCoxe·2ΦsqNDEPɛsiexp[-(1-m*)(Vgse-Vth)-Voffnvt](3.1.6a)

      where
      m*=0.5+arctan(MINV)π(3.1.6b)Qchs(y)=Caxeff·(Vgse-Vth-AbulkVF(y))(3.1.7)Qchs(y)=Qchr0+ΔQchs(y)(3.1.8)Qchsubs(y)=Qchsubs0·exp(-AbulkVF(y)nvi)(3.1.9)Qchsubs(y)=Qchsubs0(1-AbulkVF(y)nvi)(3.1.10)Qchsubs(y)=Qchsubs0+ΔQchsubs(y)(3.1.11)ΔQchsubs(y)=-Qchsubs0·AbulkVF(y)nvi(3.1.12)ΔQch(y)=ΔQchs(y)·ΔQchsubs(y)ΔQchs(y)+ΔQchsubs(y)(3.1.13)ΔQch(y)=-VF(y)VbQch0(3.1.14)Vb=Vgtseff2νtAbulk(3.1.15)Qch(y)=Caxeff·Vgsteff·(1-VF(y)Vb)(3.1.16)

      Subthreshold Swing
      Ids=I0[1-exp(-Vdsvt)]·exp(Vgs-Vth-Voffnvt)(3.2.1)

      where
      I0=μWLqɛsiNDEP2Φsvt2(3.2.2)n=1+NFACTOR·CdepCoxe+Cdsc_Term+CITCoxeCdsc_Term=(CDSC+CDSCD·Vds+CDSCB·Vbseff)·0.5cosh(DVT1Lefflt)-1(3.2.3)

      Voltage Across Oxide
      Voxacc=Vfbzb-VFBeff(4.2.1a)Voxdepinv=KloxΦs+Vgsteff(4.2.1b)Vfbzb=Vth|zeroVbsandvds-Φs-K1Φsand(4.2.2)VFBeff=Vfbzb-0.5[(Vfbzb-Vgb-0.02)+(Vfbzb-Vgb-0.02)2+0.08Vfbzb](4.2.3)

      Gate to Substrate Current
      Igbacc=WeffLeff·A·ToxRatio·Vgb·Vaux·exp[-B·TOXE(AIGBACC-BIGBACC·Voxacc)·(1+CIGBACC·Voxacc)]ToxRatio=(TOXREFTOXE)NTOX·1TOXE2Vaux=NIGBACC·vt·log(1+exp(-Vgb-VfbzbNIGBACC·vt))(4.3.1)Igbinv=WeffLeff·A·ToxRatio·Vgb·Vaux·exp[-B·TOXE(AIGBINV-BIGBINV·Voxdepinv)·(1+CIGBINV·Voxdepinv)]Vaux=NIGBINV·vt·log(1+exp(Voxdepinv-EIGBINVEIGBINV·vt))(4.3.2)

      Gate to Channel Current
      Igc=WeffLeff·A·ToxRatio·Vgse·Vaux·exp[-B·TOXE(AIGC-BIGC·Voxdepinv)·(1+CIGC·Voxdepinv)]Vaux=NIGC·vt·log(1+exp(Vgse-VTH0NIGC·vt))(4.3.3)Igs=WeffDLCIG·A·ToxRatioEdge·Vgs·Vgs·exp[-B·TOXE·POXEDGE·(AIGSD-BIGSD·Vgs)·(1+CIGSD·Vgs)]and(4.3.4)Igd=WeffDLCIG·A·ToxRatioEdge·Vgd·Vgd·exp[-B·TOXE·POXEDGE·(AIGSD-BIGSD·Vgd)·(1+CIGSD·Vgd)]ToxRatioEdge=(TOXREFTOXE·POXEDGE)NTOX·1(TOXE·POXEDGE)2Vgs=(Vgs-Vfbsd)2+1.0e-4Vgd=(Vgd-Vfbsd)2+1.0e-4Vfbsd=kBTqlog(NGATENSD)(4.3.5)

      Partition

      Igc=Igcs+Igcd Igc=Igcs+IgcdIgcs=Igc·PIGCD·Vds+exp(-PIGCD·Vds)-1+1.0e-4PIGCD2·Vds2+2.0e-4(4.3.6)Igcd=Igc·1-(PIGCD·Vds+1)·exp(-PIGCD·Vds)+1.0e-4PIGCD2·Vds2+2.0e-4(4.3.7)

      Drain Current Model


Bulk Charge Effect
Abulk={1+F_doping·[A0·LeffLeff+2XJ·Xdep·(1-AGS·Vgstef(LeffLeff+2XJ·Xdep)2)+B0Weff+B1]·}11+KETA·Vbseff(5.1.1)F_doping=1+LPEB/LeffK1ox2Φs-Vbseff+K2ox-K3BTOXEWeff+W0Φs(5.1.2)


Unified Mobility Model
Eeff=QB+(Qn/2)ɛsi(5.2.1)μeff=μ01+(Eeff/Eo)v(5.2.2)EeffVgs+Vih6TOXE(5.2.3)

    • mobMod=0
      μeff=U01+(UA+UCVbseff)(Vgsteff+2VihTOXE)+UB(Vgsteff+2VihTOXE)2(5.2.4)
    • mobMod=1
      μeff=U01+[UA(Vgsteff+2VihTOXE)+UB(Vgsteff+2VihTOXE)2](1+UC·Vbseff)(5.2.5)
    • mobMod=2
      μeff=U01+(UA+UC·Vbseff)Vgsteff+C0·(VTHO-VFB-ΦsTOXEEU(5.2.6)

      Asymmetric and Bias Dependent Source/Drain Resistance Model
    • rdsMod=0
      Rds(V)={RDSWMIN+RDSW·[PRWB·(Φs-Vbseff-Φs)+11+PRWG·Vgseff]}(1e6·Weffcj)WR(5.3.1)
    • rdsMod=1
      Rd(V)={RDWMIN+RDW·[-PRWB·Vbd+11+PRWG·Vgd-Vfbsd]}[(1e6·Weffcj)WR·NF](5.3.2)Rs(V)={RSWMIN+RSW·[-PRWB·Vbs+11+PRWG·(Vgs-Vfbsd)]}[(1e6·Weffcj)WR·NF](5.3.3.)

      Drain Current for Triode Region
    • rdsMod=1
      Ids(y)=WQch(y)μne(y)VF(y)y(5.4.1)μne(y)=μeff1+EyEsat(5.4.2)Ids(y)=WQch0(1-VF(y)Vb)μeff1+EyEsatVF(y)y(5.4.3)Ids0=WμeffQch0Vds(1-Vds2Vb)L(1+VdsEsatL).(5.4.4)
    • rdsMod=0
      Ids=Idso1+RdsIdsoVds(5.4.5)

      Velocity Saturation
      v=μeffE1+E/EsatE<Esat=VSATEEsat(5.5.1)Esat=2VSATμeff(5.5.2)

      Saturation Voltage Vdsat


Intrinsic
Vdsat=EsatL(Vgsteff+2Vt)AbulkEsatL+Vgsteff+2vt.(5.6.1)


Extrinsic
Vdsat=-b-b2-4ac2a(5.6.2a)a=Abulk2WeffVSATCoxeRds+Abulk(1λ-1)(5.6.2b)b=-[(Vgsteff+2vt)(2λ-1)+AbulkEsatLeff+3Abulk(Vgsteff+2vt)WeffVSATCoxeRds](5.6.2c)c=(Vgsteff+2vt)EsatLeff+2(Vgsteff+2vt)2WeffVSATCoxeRds(5.6.2d)λ=A1Vgsteff+A2(5.6.2e)
c=(Vgsteff+2ν1)EsatLeff+2(Vgsteff+2ν1)2WeffVSATCoxeRds  (5.6.2d)

λ=A1Vgsteff+A2  (5.6.2e)

Vdseff
Vdseff=Vdsat-12[(Vdsat-Vds-δ)+(Vdsat-Vds-δ2)+4δ·Vdsat](5.6.3)

Saturation-Region Output Conductance Model
Ids(Vgs,Vds)=Idsat(Vgs,Vdsat)+VdsatVdsIds(Vgs,Vds)Vd·Vd(5.7.1)=Idsat(Vgs,Vdsat)·[1+VdsatVds1VA·Vd]VA=Idsat·[Ids(Vgs,Vds)Vd]-1(5.7.2)

Channel Length Modulation
VACLM=Idsat·[Ids(Vgs,Vds)L·LVd]-1(5.7.3)VACLM=Cclm·(Vds-Vdsat)(5.7.4)Cclm=1PCLM·F·(1+PVAGVgsteffEsatLeff)(1+Rds·IdsoVdseff)(Leff+VdsatEsat)·1litl(5.7.5)F=11+FPROUT·LeffVgsteff+2vt(5.7.6)litl=ɛsiTOXE·XJEPSROX(5.7.7)

Drain Induced Barrier Lower (DIBL)
VADIBL=Idsat·[Ids(Vgs,Vds)Vth·VthVd]-1(5.7.8)VADIBL=Vgsteff+2vtθrout(1+PDIBLCB·Vbseff)(1-AbulkVdsatAbulkVdsat+Vgsteff+2vt)·(1+PVAGVgsteffEsatLeff)(5.7.9)θrout=PDIBLC12cosh(DROUT·Lefflt0)-2+PDIBLC2(5.7.10)

Substrate Current Induced Body Effect (SCBE)
Isub=AiBiIds(Vds-Vdsat)exp(-Bi·litlVds-Vdsat)(5.7.11)Ids=Ids-w/o-Isub+Isub(5.7.12)=Ids-w/o-Isub·[1+Vds-VdsatBiAiexp(Bi·litlVds-Vdsat)]VASCBE=BiAiexp(Bi·litlVds-Vdsat)(5.7.13)1VASCBE=PSCBE2Leffexp(-PSCBE1·litlVds-Vdsat).(5.7.14)

Drain Induced Threshold Shift (DITS)
VADITS=1PDITS·F·[1+(1+PDITSL·Leff)exp(PDITSD·Vds)](5.7.15)

Single Equation Channel Current Model
Ids=Ids0·NF1+RdsIds0Vdseff[1+1Cclmln(VAVAsat)]·(1+Vds-VdseffVADIBL)·(1+Vds-VdseffVADITS)·(1+Vds-VdseffVASCBE)(5.8.1)

where NF is the number of device fingers, and

VA is written as  (5.8.2)
VA=VAsat+VACLM  (5.8.3) VAiswrittenas(5.8.2)VA=VAsat+VACLM(5.8.3)VAsat=EsatLeff+Vdsat+2RdsvsatCoxeWeffVgsteff·1-AbulkVdsat2(Vgsteff+2vt)RdsvsatCoxeWeffAbulk-1+2λ(5.8.4)

Body Current Model


Iii Model
Iu=ALPHA0+ALPHA1·LeffLeff(Vds-Vdseff)exp(BETA0Vds-Vdseff)·IdsNoSCBE(6.1.1)IdsNoSCBE=Ids0·NF1+RdsIds0Vdseff[1+1Cclmln(VAVAsat)]·(1+Vds-VdseffVADIBL)·(1+Vds-VdseffVADITS)(6.1.2)


Igidl Model
IGIDL=AGIDL·WeffCl·Nf·Vds-Vgse-EGIDL3·Toxe·exp(-3·Toxe·BGIDLVds-Vgse-EGIDL)·Vdb3CGIDL+Vdb3(6.2.1)

Intrinsic Capacitance Modeling


Basic Formulation
{Qg=-(Qsub+Qinv+Qacc)Qb=Qacc+QsubQinv=Qs+Qd(7.2.1)Qg=-(Qinv+Qacc+Qsub0+δQsub)(7.2.2)Vth(y)=Vth(0)+(Abuilt-1)Vy(7.2.3){Qc=Wactive0Lactiveqcy=-WactiveCoxe0Lactive(Vgt-AbulkVy)yQg=Wactive0Lactiveqgy=WactiveCoxe0Lactive(Vgt+Vth-VFB-Φs-Vy)yQb=Wactive0Lactiveqby=-WactiveCoxe0Lactive(Vth-VFB-Φs+(Abulk-1)Vy)y(7.2.4)

    • where Vgt=Vgse−Vth and
      dy=dVyEyIds=WactiveμeffCoxeLactive(Vgt-Abulk2Vds)Vds=WactiveμeffCoxe(Vgt-AbulkVy)Ey(7.2.5)Cij=QiVj(7.2.6)

      where i and j denote the transistor terminals, Cij satisfies
      iCij=jCij=0

      Short Channel Model
      Vdsat,IV<Vdsat,CV<Vdsat,IV|Lactive->=Vgsteff,CVAbulk(7.2.7)Vdsat,CV=Vgsteff,CVAbulk·[1+(CLCLactive)CLE](7.2.8)Vgsteff,CV=NOFF·nvt·ln[1+exp(Vgse-Vth-VOFFCVNOFF·nvt)](7.2.9)Abulk={1+F_doping·[A0·LeffLeff+2XJ·Xdep·+B0Weff+B1]·}11+KETA·VbseffwhereF_doping=1+LPEB/LeffK1ox2Φs-Vbseff+K3BTOXEWeff+W0ΦsK2ox-(7.2.10)

      Single Equation Formulation
    • depletion to inversion region
      Q(Vgst)=Q(Vgsteff,CV)(7.2.11)C(Vgst)=C(Vgsteff,CV)Vgsteff,CVVg,d,s,b(7.2.12)

      Accumulation to Depletion Region
      VFBeff=Vfbzb-0.5[(Vfbzb-Vgb-0.02)+(Vfbzb-Vgb-0.02)2+0.08Vfbzb](7.2.13)
      Vfbzb=Vth|zeroVbsandVds−Φs−K1{square root}{square root over (Φs)}  (7.2.14)


      Linear to Saturation Region
      Vcoeff=Vdsat,CV-0.5{V4+V42+4δ4Vdsat,CV}whereV4=Vdsat,CV-Vds-δ4;δ4=0.02V(7.2.15)

      Charge Petitioning
      {Qs=Wactive0Lactiveqc(I-yLactive)yQd=Wactive0LactiveqcyLactivey(7.2.16)

      Charge—Thickness Capacitance Model
      Coxeff=Coxe·CcenCoxe+Ccen(7.3.1)
    • where

      Ccensi/XDC

      Accumulation and Depletion
      XDC=13Ldebyeexp[ACDE·(NDEP2×1016)-0.25·Vgse-Vbseff-VFBeffTOXE](7.3.2)
    • where Ldebye is Debye length, and XDC is in the unit of cm and (Vgse−Vbseff−VFBeff)/TOXE is in units of MV/Cm. For numerical statbility, (7.3.2) is replaced by (7.3.3)
      XDC=Xmax-12(X0+X02+4δxXmax)(7.3.3)

      where

      X0=Xmax−XDC−δx

      and Xmax=Ldebye/3; δx=10−3TOXE.


      Inversion Charge
      XDC=1.9×10-9cm1+(Vgsteff+4(VTH0-VFB-Φs)2TOXP)0.7(7.3.5)

      Body Charge Thickness in Inversion
      φδ=Φs-2ΦB=vtln(VgsteffCV·(VgsteffCV+2K1ox2ΦBMOIN·K1ox2vt)(7.3.5)
      qinv=−Coseff·(Vgseff,CV−φδ)  (7.3.6)


      Intrinsic Capacitance Model Equations


Accumulation Region

Qδ=WactiveLactiveCoxe(Vgs−Vbs−VFBCV)
Qsub=−Qs
Qinv=0


Subthreshold Region
Qsub0=-WactiveLactiveCoxe·K1ox22(-1+1+4(Vgs-VFBCV-Vbs)K1ox2)Qg=-Qsub0Qinv=0


Strong Inversion Region
Vdsat,cv=Vgs-VthAbulkAbulk=Abulk(1+(CLCLeff)CLE)Vth=VFBCV+Φs+K1oxΦs-Vbseff
Vth=VFBCV+φs+Klox{square root}{square root over (Φs−Vbseff)}


Linear Region
Qg=CoxeWactiveLactive(Vgs-VFBCV-Φs-Vds2+AbulkVds212(Vgs-Vth-AbulkVds2))Qb=CoxeWactiveLactive(VFBCV-Vth-Φs-(1-Abulk)Vds2-(1-Abulk)AbulkVds212(Vgs-Vth-AbulkVds2))


50/50 Partitioning:
Qinv=-CoxeWactiveLactive{Vgs-Vth-Φs-AbulkVds2+Abulk′2Vds212(Vgs-Vth-AbulkVds2))Qs=Qd=0.5Qinv
Qs=Qd=0.5Qinv


40/60 Partitioning:
Qd=-CoxeWactiveLactive(Vgs-Vth2-AbulkVds2+AbulkVds[(Vgs-Vth)26-AbulkVds(Vgs-Vth)8+(AbulkVds)240]12(Vgs-Vth-AbulkVds2)2)Qs=-(Qg+Qb+Qd)
Qs=−(Qs+Qb+Qd)


0/100 Partitioning:
Qd=-CoxeWactiveLactive(Vgs-Vth2+AbulkVds4-(AbulkVds)224)Qs=-(Qg+Qb+Qd)
Qs=−(Qg+Qb+Qd)


Saturation Region
Qg=CoxeWactiveLactive(Vgs-VFBCV-Φs-Vdsat3)Qb=-CoxeWactiveLactive(VFBCV+Φs-Vth+(1-Abulk)Vdsat3)


50/50 Partitioning:
Qs=Qd=-13CaxeWactiveLactive(Vgs-Vth)


40/60 Partitioning:
Qd=-415CaxeWactiveLactive(Vgs-Vth)
Qs=−(Qg+Qb+Qd)


0/100 Partitioning:

Qd=0
Qs=−(Qg+Qb)

capMod=1

Qg=−(Qinv+Qacc+Qsub0+δQsub)
Qb=−(Qacc+Qsub0+δQsub)
Qinv=Qs+Qd
Qacc=−WactiveLactiveCoxe·(VFBeff−Vfbzb) Qg=-(Qinv+Qacc+Qsub0+δQsub)Qb=-(Qacc+Qsub0+δQsub)Qinv=Qs+QdQacc=-WactiveLactiveCoxe·(VFBeff-Vfbzb)Qsub0=-WactiveLactiveCoxe·K1ox22·[-1+1+4(Vgse-VFBeff-Vgsteff-Vbseff)K1ox2]Vdsat,cv=VgsteffcvAbulk,Qinv=-WactiveLactiveCoxe·[Vgsteff,cv-12AbulkVcveff+Abulk′2Vcveff212·(Vgsteff,cv-AbulkVcveff/2)]δQsub=WactiveLactiveCoxe·[1-Abulk2Vcveff-(1-Abulk)·AbulkVcveff212·(Vgsteff,cv-AbulkVcveff/2)]


50/50 Charge Partitioning:
QS=QD=-WactiveLactiveCoxe2[Vgsteff,cv-12AbulkVcveff+Abulk′2Vcveff212·(Vgsteff-AbulkVcveff/2)]


40/60 Charge Partitioning:
QS=-WactiveLactiveCoxe2(Vgsteff,cv-AbulkVcveff/2)2[Vgsteff,cv3-43Vgsteff,cv2AbulkVcveff+23Vgsteff,cv(AbulkVcveff)2-215(AbulkVcveff)3]QD=-WactiveLactiveCoxe2(Vgsteff,cv-AbulkVcveff/2)2[Vgsteff,cv3-53Vgsteff,cv2AbulkVcveff+Vgsteff,cv(AbulkVcveff)2-15(AbulkVcveff)3]


0/100 Charge Partitioning:
QS=-WactiveLactiveCoxe2·[Vgsteff,cv3+12AbulkVcveff-Abulk′2Vcveff212·(Vgsteff,cv-AbulkVcveff/2)]QD=-WactiveLactiveCoxe2·[Vgsteff,cv3-32AbulkVcveff+Abulk′2Vcveff24·(Vgsteff,cv-AbulkVcveff/2)]

capMod=2
Qace=WactiveLactiveCoxeff·VgbaccVgbacc=12·[V0+V02+0.08Vfbzb]V0=Vfbzb+Vbseff-Vgs-0.02Vcveff=Vdsat-12·(V1+V12+0.08Vdsat)V1=Vdsat-Vds-0.02Vdsat=Vgsteff,cv-φδAbulkφδ=Φs-2ΦB=vtln(VgsteffCV·VgsteffCV+2K1ox2ΦBMOIN·K1ox2vt)Qsub0=-WactiveLactiveCaxeff·K1ox22·[-1+1+4(Vgse-VFBeff-Vbseffs-Vgsteff,cv)K1ox2]Qinv=-WactiveLactiveCoxeff·[Vgsteff.cv-φδ-12AbulkVcveff+Abulk′2Vcveff212·(Vgsteff,cv-φδ-AbulkVcveff/2)]δQsub=WactiveLactiveCaxeff·[1-Abulk2Vcveff-(1-Abulk)·AbulkVcveff212·(Vgsteff,cv-φδ-AbulkVcveff/2)]


50/50 Partitioning:
QS=QD=-WactiveLactiveCaxeff2[Vgsteff,cv-φδ-12AbulkVcveff+Abulk′2Vcveff212·(Vgsteff,cv-φδ-AbulkVcveff/2)]


40/60 Partitioning:
QS=-WactiveLactiveCoxeff2(Vgsteff,cv-φδ-AbulkVcveff2)2[(Vgsteff,cv-φδ)3-43(Vgsteff,cv-φδ)2AbulkVcveff+23(Vgsteff,cv-φδ)(AbulkVcveff)2-215(AbulkVcveff)3]QD=-WactiveLactiveCoxeff2(Vgsteff,cv-φδ-AbulkVcveff2)2[(Vgsteff,cv-φδ)3-53(Vgsteff,cv-φδ)2AbulkVcveff+(Vgsteff,cv-φδ)(AbulkVcveff)2-15(AbulkVcveff)3]


0/100 Partitioning:
QS=-WactiveLactiveCoxeff2·[Vgsteff,cv-φδ+12AbulkVcveff-Abulk2Vcveff212·(Vgsteff,cv-φδ-AbulkVcveff2)]QD=-WactiveLactiveCoxeff2·[Vgsteff,cv-φδ-32AbulkVcveff+Abulk2Vcveff24·(Vgsteff,cv-φδ-AbulkVdveff2)]

Fringe Capacitance Model
CF=2·EPSROX·ɛ0π·log(1+4.0e-7TOXE)(7.5.1)

Bias-Dependent Overlap Capacitance Model


(i) Source Side
Qoverlap,sWactive=CGSO·Vgs+CGSL(Vgs-Vgs,overlap-(7.5.2)CKAPPAS2(-1+1-4Vgs,overlapCKAPPAS))Vgs,overlap=12(Vgs+δ1-(Vgs+δ1)2+4δ1),δ1=0.02V(7.5.3)


(ii) Drain Side
Qoverlap,dWactive=CGDO·Vgd+CGDL(Vgd-Vgd,overlap-(7.5.4)CKAPPAD2(-1+1-4Vgd,overlapCKAPPAD))Vgd,overlap=12(Vgd+δ1-(Vgd+δ1)2+4δ1),δ1=0.02V(7.5.5)


(iii) Gate Overlap Charge

Qoverlap,g=−(Qoverlap,d+Qoverlap,s+(CGBO·LactiveVgb)  (7.5.6)

Bias-Independent Overlap Capacitance Model


The gate-to-source overlap charge is expressed by

Qoverlap,s=Wactive·CGSO·Vgs


The gate-to-drain overlap charge is calculated by

Qoverlap,d=Wactive·CGDO·Vgd


The gate-to-substrate overlap charge is computed by

Qoverlap,b=Lactive·CGBO·Vgb

Charge-Deficit Non-Quasi Static Model


The Transient Model
Qdef(t)=Vdef×Cfact(8.1.1)iD,G,S(t)=ID,G,S(DC)+Qd,g,s(t)t(8.1.2)Qdef(t)=Qcheq(t)-Qch(t)(8.1.3)Qdef(t)t=Qcheq(t)t-Qdef(t)τ(8.1.4a)Qd,g,s(t)t=D,G,SxpartQdef(t)τ(8.1.4b)1Rii=XRCRG1·(IdsVdseff+XRCRG2·WeffμeffCoxeffkBTqLeff)(8.1.5)

The AC Model
ΔQch(t)=ΔQcheq(t)1+jωτ(8.1.6)Gm=Gm01+ω2τ2+j(-Gm0·ωτ1+ω2τ2)(8.1.7)Cdg=Cdg01+ω2τ2+j(-Cdg0·ωτ1+ω2τ2)(8.1.8)

Gate Electrode Electrode and Intrinsic-Input Resistance Model
Rgeltd=RSHG·(XGW+Weffcj3·NGCON)NGCON·(Ldrawn-XGL)·NF(8.1.9)

Charge-Deficit Non-Quasi Static Model


The Transient Model
Qdef(t)=Vdef×Cfact(8.1.1)iD,G,S(t)=ID,G,S(DC)+Qd,g,s(t)t(8.1.2)Qdef(t)=Qcheq(t)-Qch(t)(8.1.3)Qdef(t)t=Qcheq(t)t-Qdef(t)τ(8.1.4a)Qd,g,s(t)t=D,G,SxpartQdef(t)τ(8.1.4b)1Rii=XRCRG1·(IdsVdseff+XRCRG2·WeffμeffCoxeffkBTqLeff)(8.1.5)

The AC Model
ΔQch(t)=ΔQcheq(t)1+jωτ(8.1.6)Gm=Gm01+ω2τ2+j(-Gm0·ωτ1+ω2τ2)(8.1.7)Cdg=Cdg01+ω2τ2+j(-Cdg0·ωτ1+ω2τ2)(8.1.8)

Gate Electrode Electrode and Intrinsic-Input Resistance Model
Rgeltd=RSHG·(XGW+Weffci3·NGCON)NGCON·(Ldrawn-XGL)·NF(8.1.9)Sid(f)=KF·IdsAFCoxeLeff2fEF(9.1.1)Sid,lev(f)=kBTq2μeffIdsCoxeLeff2Abulkfef·1010(NOIAlog(N0+NaN1+Na)+NOIB(N0-N1)+NOIC2(N02-N12))+kBTIds2ΔLclmWeff·Leff2fef·1010·NOLA+NOIBNi+NOIGNi2(Ni+Na)2(9.1.2)N0=Coxe·Vgsteff/q(9.1.3)Nl=Coxe·Vgsteff·(1-AbulkVdseffVgsteff+2Vi)/q(9.1.4)Na=kBT·(Coxe+Cd+CIT)/q2(9.1.5)ΔLclm=Litl·log(Vils-VdseffLitl+EMEset)Eset=2VSATμeff(9.1.6)Sid,subVt(f)=NOIA·kBT·Ids2WeffLefffEFNa2·1010(9.1.7)Sid(f)=Sid,lav(f)×Sid,subvt(f)Sid,subvt(f)+Sid,lav(f)(9.1.8)

Channel Thermal Noise
id2_=4kBTΔfRds(V)+Leff2μeffQinv·NTNOI(9.2.1)Qinv=WactiveLactiveCoxeff·NF·(9.2.2)[Vgsteff-AbulkVdseff2+Abulk2Vdseff212·(Vgsteff-AbulkVdseff2)]vd2_=4kBT·θtnoi2·VdseffΔfIds(9.2.3)id2_=4kBTVdseffΔfIds[Gds+βtnoi·(Gm+Gmbs)]2-(9.2.4)vd2_·(Gm+Gds+Gmbs)2θtnoi=0.37·[1+TNOIB·Leff·(VgsteffEsatLeff)2](9.2.5)βtnoi=0.577·[1+TNOIA·Leff·(VgsteffEsatLeff)2](9.2.6)

Junction Diode IV Model


Source/Body Junction Diode

    • dioMod=0
      Ibs=Isbs[exp(qVbsNJS·kBTNOM)-1]·fbreakdown+Vbs·Gmin(10.1.1)Isbs=AseffJss(T)+PseffJssws(T)+Weffcj·NF·Jsswgs(T)(10.1.2)fbreakdown=1+XJBVS·exp(-q·(BVS+Vbs)NJS·kBTNOM).(10.1.3)
    • dioMod=1
      Ibs=Isbs[exp(qVbsNJS·kBTNOM)-1]+Vbs·Gmin(10.1.4)Ibs=Isbs[exp(qVbsNJS·kBTNOM)-1]·fbreakdown+Vbs·Gmin(10.1.5)


Drain/Body Junction Diode

    • dioMod=0
      Ibd=Isbd[exp(qVbdNJD·kBTNOM)-1]·fbreakdown+(10.1.6)Vbd·GminIsbd=AdeffJsd(T)+PdeffJsswd(T)+Weffcj·NF·Jsswgd(T)(10.1.7)fbreakdown=1+XJBVD·exp(-q·(BVD+Vbd)NJD·kBTNOM)(10.1.8)
    • dioMod=1
      Ibd=Isbd[exp(qVbdNJD·kBTNOM)-1]+Vbd·Gmin(10.1.9)Ibd=Isbd[exp(qVbdNJD·kBTNOM)-1]·fbreakdown+(10.1.10)Vbd·Gmin

      Junction Diode CV Model


Source/Body Junction Diode

Cbs=AseffCjbs+PseffCjbasw+Weffcj·NF·Cjbsswg  (10.2.1)


If Vbs<0, use equn. 10.2.2, otherwise use equn. 10.2.3
Cjbs=CJS(T)·(1-VbsPBS(T))-MJS(10.2.2)Cjbs=CJS(T)·(1+MJS·VbsPBS(T))(10.2.3)


If Vbs<0, use equn. 10.2.4, otherwise use equn. 10.2.5
Cjbssw=CJSWS(T)·(1-VbsPBSWS(T))-MJSWS(10.2.4)Cjbssw=CJSWS(T)·(1+MJSWS·VbsPBSWS(T))(10.2.5)


If Vbs<0, use equn. 10.2.6, otherwise use equn. 10.2.7
Cjbsswg=CJSWGS(T)·(1-VbsPBSWGS(T))-MJSWGS(10.2.6)Cjbsswg=CJSWGS(T)·(1-VbsPBSWGS(T))-MJSWGS(10.2.7)

Drain/Body Junction Diode

Cbd=AdeffCjbd+PdeffCjbdsw+Weffcj·NF·Cjbdswg  (10.2.8)


If Vbd<0, use equn. 10.2.9, otherwise use equn. 10.2.10
Cjbd=CJD(T)·(1-VbdPBD(T))-MJD(10.2.9)Cjbd=CJD(T)·(1+MJD·VbdPBD(T))(10.2.10)


If Vbd<0, use equn. 10.2.11, otherwise use equn. 10.2.12
Cjbdsw=CJSWD(T)·(1-VbdPBSWD(T))-MJSWD(10.2.11)Cjbdsw=CJSWD(T)·(1+MJSWD·VbdPBSWD(T))(10.2.12)


If Vbd<0, use equn. 10.2.13, otherwise use equn. 10.2.14
Cjbdswg=CJSWGD(T)·(1-VbdPBSWGD(T))-MJSWGD(10.2.13)Cjbdswg=CJSWGD(T)·(1+MJSWGD·VbdPBSWGD(T))(10.2.14)

Layout Dependent Parasitic Models


Gate Electrode Resistance
Rgeltd=RSHG·(XGW+Weffcj3·NGCON)NGCON·(Ldrawn-XGL)·NF(11.2.1)

Temperature Dependence Model

          • Temperature Dependence of Threshold Voltage
            Vsh(T)=Vth(TNOM)+(KT1+KT1LLeff+KT2·Vbseff)·(TTNOM-1)(12.1.1)


Temperature Dependence of Mobility

U0(T)=U0(TNOM)·(T/TNOM)UTE  (12.2.1)
UA(T)=UA(TNOM)+UA1(T/TNOM−1)  (12.2.2)
UB(T)=UB(TNOM)+UB1·(T/TNOM−1)  (12.2.3)
UC(T)=UC(TNOM)+UC1·(T/TNOM−1)  (12.2.4)


Temperature Dependency of Saturation Velocity

VSAT(T)=VSAT(TNOM)−AT·(T/TNOM−1)  (12.3.1)


Temperature Dependency of LDD Resistance

    • rdsMod=0

      RDSW(T)=RDSW(TNOM)+PRT·(T/TNOM−1)  (12.4.1)
      RDSWMIN(T)=RDSWMIN(TNOM)+PRT·(T/TNOM−1)  (12.4.2)
    • rdsMod=1

      RDW(T)=RDW(TNOM)+PRT·(T/TNOM−1)  (12.4.3)
      RDWMIN(T)=RDWMIN(TNOM)+PRT·(T/TNOM−1)  (12.4.4)
      RSW(T)=RSW(TNOM)+PRT·(T/TNOM−1)  (12.4.5)
      RSWMIN(T)=RSWMIN(TNOM)+PRT·(T/TNOM−1)  (12.4.6)

      Temperature Dependence of Junction Diode IV

      Isbs=AseffJss(T)+PseffJssws(T)+Weffcj·NF·Jsswgs(T)  (12.5.1) Isbs=AseffJss(T)+PseffJssws(T)+Weffcj·NF·Jsswgs(T)(12.5.1)Jss(T)=JSS(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTIS·ln(TTNOM)NJS)(12.5.2)Jssws(T)=JSSWS(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTIS·ln(TTNOM)NJS)(12.5.3)Jsswgs(T)=JSSWGS(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTIS·ln(TTNOM)NJS)(12.5.4)

      drain side diode

      Isbd=AdeffJsd(T)+PdeffJsswd(T)+Weffcj·NF·Jsswgd(T)  (12.5.5) Isbd=AdeffJsd(T)+PdeffJsswd(T)+Weffcj·NF·Jsswgd(T)(12.5.5)Jsd(T)=JSD(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTID·ln(TTNOM)NJD)(12.5.6)Jsswd(T)=JSSWD(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTID·ln(TTNOM)NJD)(12.5.7)Jsswgd(T)=JSSWGD(TNOM)·exp(Eg(TNOM)vt(TNOM)-Eg(T)vt(T)+XTID·ln(TTNOM)NJD)(12.5.8)

      Temperature Dependence of Junction Diode CV
    • source side diode

      CJS(T)=CJS(TNOM)·[1+TCJ·(T−TNOM)]  (12.6.1)
      CJSWS(T)=CJSWS(TNOM)+TCJSW·(T−TNOM)  (12.6.2)
      CJSWGS(T)=CJSWGS(TNOM)·[1+TCJSWG·(T−TNOM)]  (12.6.3)
      PBS(T)=PBS(TNOM)−TPB·(T−TNOM)  (12.6.4)
      PBSWS(T)=PBSWS(TNOM)−TPBSW·(T−TNOM)  (12.6.5)
      PBSWGS(T)=PBSWGS(TNOM)−TPBSWG·(T−TNOM)  (12.6.6)

      drain side diode

      CJD(T)=CJD(TNOM)·[1+TCJ·(T−TNOM)]  (12.6.7)
      CJSWD(T)=CJSWD(TNOM)+TCJSW·(T−TNOM)  (12.6.8)
      CJSWGD(T)=CJSWGD(TNOM)·[1+TCJSWG·(T−TNOM)]  (12.6.9)
      PBD(T)=PBD(TNOM)−TPB·(T−TNOM)  (12.6.10)
      PBSWD(T)=PBSWD(TNOM)−TPBSW·(T−TNOM)  (12.6.11)
      PBSWGD(T)=PBSWGD(TNOM)−TPBSWG·(T−TNOM)  (12.6.12)

      Temperature Dependences of Eg and ni


      Drain Saturation Current Parameters
      Eg(TNOM)=1.16-7.02×10-4TNOM2TNOM+1108(12.7.1)Eg(T)=1.16-7.02×10-4T2T+1108(12.7.2)ni=1.45e10·TNOM300.15·TNOM300.15·exp[21.5565981-qEg(TNOM)2·kBT](12.7.3)Abulk={1-VT,LongVBS,eff×[A0·LeffLeff+2XJ·Xdep×(1-AGS·VGST,eff(LeffLeff+2XJ·Xdep)2)+B0Weff+B1]}×11+KETA·VBS,effwhereVT,LongVBS,eff=1+LPEBLeff×K122Φf-VBS,effTOXETOXM+K2TOXETOXM-K3×TOXEWeff+W02Φf14.1

Claims
  • 1. A method for extracting semiconductor device model parameters, comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices; extracting Vth related parameters based on the terminal current data; and extracting Igb related parameters based on the terminal current data and the extracted Vth related parameters.
  • 2. The method of claim 1, wherein the terminal current data comprises one or more Ig v. Vbs curves, and wherein extracting Igb related parameters comprises: extracting Aigbacc, Bigbacc, and Cigbacc using non-linear square fit and the one or more Ig v. Vbs curves; and extracting Nigbacc using said extracted Aigbacc, Bigbacc, and Cigbacc and linear interpolation using maximum slope position in the one or more Ig vs. Vbs curves.
  • 3. The method of claim 1, wherein the terminal current data comprises one or more Ib v. Vgs curves, and wherein extracting Igb related parameters comprises: extracting Aigbinv, Biginv, and Ciginv using non-linear square fit and the one or more Ib v. Vgs curves; and extracting NIgbinv and Eigbinv using the extracted Aigbinv, Bigbinv, and Cigbinv and mathematical optimization.
  • 4. A method for extracting semiconductor device model parameters, comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices; extracting Vth related parameters; and extracting Igidl related parameters based on the terminal current data and the Vth related parameters.
  • 5. The method of claim 3, wherein the terminal current data comprises Ib v. Vgs curves, and wherein extracting Igidl related parameters further comprises: extracting CGIDL based on the Ib vs Vgs curves for varying Vds; extracting AIGDL and BIGDL using non-linear square fit; and optimizing said AIGDL and said BIGDL to extract EGIDL.
  • 6. A method for extracting semiconductor device model parameters comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices; extracting Vth related parameters; and extracting Igd and Igs related parameters based on the terminal current data and the extracted Vth related parameters.
  • 7. The method of claim 5, wherein the terminal current data comprises Id v. Vgs and Is v. Vgs curves measured with Vds=0 and Vbs=0 on one or more devices having a maximum Ldrawn*Wdrawn among the set of test devices, and wherein extracting Igc related parameters further comprises: extracting AIGSD, BIGSD, and CIGSD using non-linear square fit method and the Id v. Vgs and Is v. Vgs curves.
  • 8. The method of claim 6, wherein extracting Igd and Igs related parameters further comprises: setting POXEDGE, TOXREF, and NTOX to their default values and setting DLCIG equal to 0.7 *Xj before extracting AIGSD, BIGSD, and CIGSD; and extracting DLCIG after extracting AIGSD, BIGSD, and CIGSD.
  • 9. The method of claim 5, further comprising extracting Igc related parameters by: obtaining Ig v. Vgs curves for devices having a maximum Ldrawn*Wdrawn among the set of test devices; removing Igs and Igd effects from the Ig v Vgs curves using the extracted Igd and Igs related parameters; extracting AIGC, BIGC, and CIGC using non-linear square fit and the Ig v. Vgs curves; and extracting NIGC at Vgs=Vth using linear interpolation. and dividing Igc into its two components, Igcs and Igcd.
  • 10. A method for extracting semiconductor device model parameters comprising: loading measurement data; extracting Vth related parameters; using the extracted Vth related parameters to extract Leff, Rd and Rs related parameters; using the extracted Vth related parameters to extract mobility and Weff related parameters; using the extracted Vth, Leff, mobility, and Weff related parameters to extract Vth geometry related parameters; using the extracted Vth, Leff, Rd Rs, mobility, and Weff related parameters to extract sub-threshold region related parameters; using the extracted Vth related parameters to extract drain induced barrier lower related parameters; using the extracted Vth, Leff, Rd, Rs, mobility, Weff, sub-threshold region, and drain induced barrier lower related parameters to extract Idsat related parameters; and extracting additional DC related parameters.
  • 11. The method of claim 9, wherein the Leff, Rd and Rs related parameters, the Vth geometry related parameters, the subthreshold region related parameters, and the drain induced barrier lower related parameters are extracted using linear region Id v. Vgs curves constructed based on the measurement data.
  • 12. The method of claim 9, wherein the Idsat related parameters are extracted using saturation region Id v. Vds curves constructed based on the measurement data.
  • 13. The method of claim 9, wherein extracting additional DC parameters further comprises: extracting Iii related parameters; and extracting junction related parameters.
  • 14. The method of claim 12, wherein the Iii related parameters are extracted using linear region Id v. Vgs curves constructed based on the measurement data and the junction related parameters are extracted using Cbs V. Vbs curves and Cbd v. Vbs curves constructed based on the measurement data.
  • 15. A method of extracting Igidl related parameters for modeling a MOSFET device, comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices, the terminal current data including Ib vs Vgs curves measured on the set of test devices; extracting CGIDL using the Ib vs Vgs curves; extracting AIGDL and BIGDL using non-linear square fit; and optimizing said AIGDL and said BIGDl to extract EGIDL.
  • 16. A method for extracting semiconductor device model parameters comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices; extracting Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters from the terminal current data; modifying the terminal current data using the Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters; and extracting additional DC parameters using the modified terminal current data.
  • 17. The method of claim 15, wherein extracting additional DC parameters further comprises: extracting Leff, Rd and Rs related parameters; extracting mobility and Weff related parameters; using the extracted Leff, mobility and Weff related parameters to extract Vth geometry parameters; using the extracted Leff, Rd and Rs, mobility and Weff related parameters to extract sub-threshold region related parameters; extracting DIBL related parameters; and using the extracted Leff, Rd and Rs, mobility and Weff Vth geometry, sub-threshold region and DIBL related parameters to extract Idsat related parameters
  • 18. The method of claim 16, wherein extracting additional DC parameters further comprising: extracting Iii related parameters; and extracting junction related parameters.
  • 19. A computer readable medium comprising computer executable program instructions that when executed cause a digital processing system to perform a method for extracting semiconductor device model parameters, the method comprising: obtaining terminal current data corresponding to various bias conditions in a set of test devices; extracting Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters from the terminal current data; modifying the terminal current data using the extracted Idiode related parameters and Ibjt related parameter extracting Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters; and extracting additional DC parameters from the modified terminal current data.
  • 20. A system for extracting semiconductor device model parameters, comprising: a central processing unit (CPU); a port or I/O device communicating with the central processing unit to provide terminal current data to the CPU corresponding to various bias conditions in a set of test devices; a memory communicating with the CPU and storing therein program instructions executable by the CPU to extract Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters from said terminal current data, to modify said terminal current data based on the extracted Igb related parameters, Igidl related parameters, Igd and Igs related parameters, and Igc related parameters, and to extract DC parameters based on said modified terminal current data.
  • 21. The system according to claim 19, wherein said memory also stores program instructions executable by the CPU to: extract Vth related parameters; use the extracted Vth related parameters to extract Leff, Rd and Rs related parameters; use the extracted Vth related parameters to extract mobility and Weff related parameters; use the extracted Vth, Leff, Rd, Rs, mobility and Weff related parameters to extract sub-threshold region related parameters; use the extracted Vth related parameters to extract drain induced barrier lower related parameters; and use the extracted Vth, Leff, Rd, Rs, mobility, Weff, sub-threshold region, and drain induced barrier lower related parameters to extract Idsat related parameters.
Provisional Applications (1)
Number Date Country
60407251 Aug 2002 US