This application claims priority to German Patent Application 10 2005 038 939.2, which was filed Aug. 17, 2005 and is incorporated herein by reference.
The present invention relates to semiconductor memory components, and in one example to charge trapping semiconductor components.
German Patent Application Serial No. 101 10 150 A1 and corresponding U.S. Pat. No. 6,686,242, each of which is incorporated herein by reference, describe a method for fabricating metallic bit lines for memory cell arrays, in which doped wells are fabricated at a main side of a semiconductor substrate and a storage layer sequence made of dielectric materials suitable for charge trapping is applied over the whole area. A gate region layer made of polysilicon that is provided for the gate electrodes is applied over the whole area and patterned in strip-type fashion along the bit lines to be fabricated. Buried bit lines are fabricated between the strips by implantation of dopant into the semiconductor material of the substrate. Metallic bit lines are fabricated directly on the doped regions by deposition of a suitable metal layer. The gate region layer is uncovered at the top side, with the result that it can be contact-connected to a first word line layer provided for the word lines, the word line layer likewise being polysilicon. This is followed by at least one metallic layer, for example a layer made of WSi, or a layer sequence made of tungsten nitride and tungsten. The layers provided for the word lines are then patterned according to the word lines to form word line stacks. In this case, the strip-type portions of the gate region layer are also separated into individual gate electrodes made of polysilicon.
However, further miniaturization of the memory components necessitates reducing the cross sections of the interconnects. As a result, the electrical resistance of the interconnects increases, but the resistance is intended to be as low as possible in order as far as possible to avoid a voltage drop along the line and to enable a sufficiently short switching time. On the other hand, the number of layers provided for the word lines should not be too high; the thickness of the layers must be kept as small as possible in order to keep the aspect ratio between the height of the word line stacks and the width thereof within appropriate limits. A multilayer word line layer including a polysilicon layer is, therefore, suitable only to a limited extent for further minimization of the memory components.
In one aspect, the present invention provides a fabrication method for a semiconductor memory component that makes it possible to reduce the electrical resistance of the word lines and at the same to obtain a smallest possible height of the word line stacks.
This aspect is achieved by means of the fabrication method wherein a storage layer sequence is formed over a semiconductor body. Gate electrodes are formed adjacent the storage layer sequence, the gate electrodes including strip-type structures made of electrically conductive material. Source/drain regions are formed by an implantation of dopant into the semiconductor body between the gate electrodes. A dielectric filling is formed between the gate electrode layer and word lines are formed from at least one metal layer that makes electrical contact with the gate electrodes. A dielectric material is provided adjacent free sidewalls that encompass an upper region of the gate electrodes, the dielectric material forming word line spacers. A further dielectric filling is formed into regions between mutually adjacent word lines and between mutually adjacent gate electrodes.
In the case of the semiconductor memory component, bit lines and word lines running transversely with respect thereto are arranged at a main side of a semiconductor substrate. The word lines connect the gate electrodes made of electrically conductive material, preferably made of conductively doped polysilicon, of the individual memory cells to one another in rows. The memory cells each have source/drain regions on both sides of the gate electrodes. At every location the word lines have an ohmic resistivity that is lower than the ohmic resistivity of highly doped silicon or highly doped germanium. The value of the ohmic resistivity of highly doped polysilicon of the order of magnitude of around 1000 μΩcm is typical of these comparative resistivities.
The word lines are preferably formed completely from metal having less than 5 percent of nonmetallic atoms or impurities. A material of this type is defined as pure metal in the context of this invention. Accordingly, the material of the word lines only has at most a proportion of impurities with a magnitude such that the electrical bulk resistance of the word lines remains sufficiently low and lies below the values of highly doped silicon or highly doped germanium. A resistivity of less than 15 μΩcm, in particular, can be achieved in this way. The word lines are preferably pure tungsten or pure molybdenum if the method provides further steps at a high temperature of 1000° C. or more, which the word lines must withstand. The metals can be applied not only by CVD (chemical vapor deposition) but also by sputtering. Preferred refinements provide for surrounding the word lines with material that has properties of a barrier in order to prevent the outdiffusion of metal atoms from the word lines into the surrounding material. Nitride layers, in particular, are suitable for this purpose.
In the case of the fabrication method, a metal layer that is practically pure in the above sense, or a layer sequence made of pure metals, and is provided for the word lines may firstly be applied over the whole area on the top side and on parallel strips of a gate electrode layer. The metal forms a low-value contact resistance with respect to the electrically conductive material of the gate electrodes; if appropriate, a thin adhesion layer may additionally be arranged between the gate electrode layer and the word lines. The word line stacks are then etched at least into a certain depth into the strip-type portions of the gate electrode layer and subsequently provided with electrically insulating spacers at the sides, which spacers bring about, in particular, an encapsulation of the word lines that protects the material of the word lines in optionally required subsequent steps performed at high temperature. Such a material having a good barrier effect against outdiffusion of the metal atoms from the word line is preferably chosen for this purpose. A nitride of the semiconductor material, in particular silicon nitride, is especially suitable for this purpose. The word line stacks are then also completely patterned, if appropriate, so that the gate electrodes of the individual memory cells are separated from one another.
Instead of this, a hard mask may firstly be applied and patterned in the form of the word line stacks to be fabricated. A dielectric material with respect to which the material of the hard mask can be etched selectively is introduced between the portions of the hard mask that are patterned in strip-type fashion. When the hard mask has been removed, the openings fabricated in this way can be filled with the material of the word lines. By this means, too, word lines are formed that are composed completely of a material having a low ohmic resistance, preferably of pure metal.
Examples of the semiconductor memory component and associated fabrication methods are described in more detail below with reference to the accompanying figures.
The following list of reference symbols can be used in conjunction with the figures:
The openings 30 between the gate electrodes 34 extend at least down to the upper boundary layer 18 of the storage layer sequence 20. An implantation region 32 may in each case be fabricated between the channel regions 6, the basic doping of the doped well 12 being increased in the implantation region by means of an implantation of dopant in order to obtain harder pn junctions with respect to the buried bit lines that are to be implanted later, so that the difference between the n-type conductivity and the p-type conductivity is greater there. However, the implantation regions 32 provided for the hard pn junctions may also be omitted.
The buried bit lines 38, which also comprise the source/drain regions of the individual memory cells, are formed by means of an implantation of dopant. The openings 30, possibly between the spacers 36, are filled with a dielectric filling 42. However, the spacers 36 may, if present, also be removed first before the introduction of the dielectric filling 42. The hard mask 24 is removed prior to the application of the word line layer provided for the word lines. In this case, the dielectric filling 42 may be insipiently etched and, in particular, be removed to an extent such that the top side of the intermediate product obtained is essentially planar.
An exemplary embodiment of the semiconductor memory component with word lines formed completely from pure metal can also be fabricated by an alternative fabrication method, which is described below with reference to the further figures.
The differences between the exemplary embodiments described can be inferred from the comparison of
In each embodiment, the entire word line is formed only from layers having a low ohmic resistivity. Provision may also be made, and it is particularly preferred, for only a single homogeneous metal layer to be applied as word line. Both preferred fabrication methods illustrated result in the fabrication of semiconductor memory components whose word lines comprise pure metal with a sufficiently low percentage of impurities. Suitable lateral electrical insulations are provided in each case. The buried bit lines may, as necessary, be additionally provided with metallizations such as are described in German Patent Application 101 10 150 A1 cited in the introduction.
The invention makes it possible to fabricate the specified component structure with smaller period spacings (pitch) than has been possible heretofore. One advantage of this invention is, in particular, that the word lines can be formed with self-aligned contacts on the gate electrodes. The embodiment with a further hard mask layer 25 has the advantage, in particular, that all the high temperature steps, in particular the annealing of implants, can be carried out before the low-resistance material for the word lines is deposited and patterned. This primarily has the advantage that a material that only has to be able to withstand 450° C. can be chosen for the word line.
Number | Date | Country | Kind |
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10 2005 038 939.2 | Aug 2005 | DE | national |