Patent Application
20120058597
This invention relates to thin-film field-effect transistors and a fabrication method thereof.
Semiconducting thin-film transistors (TFTs) comprise a substrate, a semiconducting layer, a dielectric layer, and conducting materials for the source, drain and gate electrodes. Depending on the gate potential (VG) and the drain potential (VD), the channel current (i.e. the current flowing from the source electrode to the drain electrode, often referred to as ID) can be modulated.
Over the last ten years, TFTs based on amorphous inorganic semiconductors have become the key technology for numerous applications. The most notable example comes from the information display industry where amorphous (a-Si) transistors, in particular, are found at the heart of everyday products including electrophoretic displays (i.e. E-paper), liquid crystal displays (LCDs), liquid crystal on silicon (LCoS) for micro-display and projection TV technology, to name a few.
Generally, amorphous semiconductors are preferred over polycrystalline films as the active layers from the view point of processing temperature and uniformity of device characteristics, i.e. small parameter spread. Despite the significant advantages, however, use of a-Si or state-of-the-art organic materials in the next generation displays is limited mainly due to their low carrier mobility (0.01-1 cm2/Vs). For example, with the use of amorphous semiconductors in current driven display technologies such as active-matrix (AM) displays based on organic light-emitting diodes (OLEDs), small mobilities mean that the transistors must be large enough in order to drive the necessary current (1-10 μA/pixel). In reality, however, driving TFTs cannot exceed certain dimensions because the bigger their size the smaller the available area for the emitting pixel. This is the so-called aperture ratio and is defined as the fraction of the total pixel area available for light emission. In the case of a-Si TFTs or high-performance organic TFTs (OTFTs) and a pixel size of 300-500 μm, aperture ratios of 40-50% have been demonstrated.
One possible route towards increasing the aperture ratio is the use of high mobility polycrystalline semiconductors such as polycrystalline-Si (p-Si). The downside of this approach is that device processing requires a large thermal budget with typical temperatures in excess of 500° C. This not only imposes a severe restriction on the choice of substrate materials but also hampers the overall suitability of the technology for prospective low cost fabrication. Another major contributor to the limited aperture ratio is the extensive wiring needed. This because every pixel in an AM display requires additional circuitry which typically includes a switching transistor and a storage capacitor integrated with appropriate power/data lines to allow selective pixel addressing. As a result the area associated with the driving electronics becomes comparable to the area of the light-emitting, pixel, hence severely reducing the aperture ratio.
One alternative approach that could potentially address all the issues outlined above is the use of conductive and semiconductive transparent metal oxides as the electrode and active channel materials, respectively. Metal oxides have been known for many years but only recently have been explored in active electronic devices such as field-effect transistors. A very important property associated with this class of materials is that the charge transport can be independent of the crystallinity of the solid. This feature is completely different from what is usually encountered in covalent semiconductors such as Si. As a result, amorphous films of metal oxides exhibit the same carrier mobilities as crystalline films. Therefore one could envision high performance applications where the high mobility semiconductor is an amorphous oxide.
In recent years, oxide semiconductors have been the focus of intense research because of their potential in numerous technological applications including photocatalysis, solar cells, light-emitting diodes, and very recently, TFTs. In the past, a variety of techniques have been used for the deposition of oxide films, including radio frequency magnetron sputtering, pulsed laser deposition, metal organic chemical vapour deposition, dip coating, spin coating, and spray pyrolysis. With the latter three techniques the films are deposited from solution in ambient air. The advantages of solution-processing over sputtering, laser or vapour deposition techniques are known from organic electronics with the most important being the easy deposition and patterning of the semiconductor materials on large area substrates employing relatively simple techniques. The latter could potentially lead to a significant reduction in processing cost and equipment expenditure. However, in most cases, control over the morphology of the solution-processed semiconductor films is limited and can negatively affect device performance. As result there is a desire to simplify the fabrication process for TFTs, particularly those using oxide semiconductors.
According to a first aspect of the present invention there is provided a method as defined in claim 1 of the appended claims. Thus there is provided a method of forming a thin-film field-effect transistor comprising: forming a dielectric layer adjacent a gate; forming a source region and a drain region; and forming a semiconductor layer on the dielectric layer; wherein the semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising: oxides; oxide-based materials; mixed oxides; metallic type oxides; group I-IV, II-VI, III-VI, IV-VI, V-VI and VIII-VI binary chalcogenides; and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides.
The order in which the various processes appear in the preceding sentence should not be interpreted as implying any particular sequence of steps in the formation of the transistor.
Accordingly, the invention enables the fabrication of oxide-based TFTs in which the semiconductor layer(s) is/are deposited by spray pyrolysis.
Deposition of the source and/or drain regions, and/or the gate, can also be performed by spray pyrolysis, using appropriate conductive materials such as conductive oxides made using doped metal oxides (e.g. indium doped tin oxide, aluminium doped zinc oxide, to name but two).
The invention enables simple fabrication of TFTs, by exploiting the ability to deposit metal oxide (and other) semiconductors by spray pyrolysis. Spray pyrolysis is an attractive processing route for TFTs since it is scalable and hence provides a potentially low-cost process suitable for the deposition of dense films. Moreover, there are virtually no restrictions on the substrate material and dimensions. By changing the composition of the spray solution during the spraying process it can be used to make layered films of different physical characteristics, i.e. optical, electrical, mechanical etc. We believe such a fabrication process will be well-suited to the manufacture of display devices such as active-matrix displays, as well as large area integrated transparent electronics, and other devices such as light sensors, gas sensors or bio-sensors.
The use of spray pyrolysis for the fabrication of semiconductors has been surprisingly limited in the prior art. The growth of several types of oxide semiconductor films using spray pyrolysis has been reported in “Versatility of chemical spray pyrolysis technique” by P. S. Patil [Materials Chemistry and Physics 59, 185 (1999)]. However, to the best of our knowledge, to date there have been no explicit disclosures of any oxide-based TFTs fabricated by spray pyrolysis. The closest prior art known to us is WO 2006/003584 (Field-Effect Transistors), which mentions spray pyrolysis, but does not disclose oxide-based TFTs. In WO 2006/003584, the candidate materials are limited to compounds containing cadmium (Cd), zinc (Zn), lead (Pb), tin (Sn), bismuth (Bi), antimony (Sb), indium (In), copper (Cu), mercury (Hg), sulphur (S), selenium (Se) and tellurium (Te).
Also of relevance is our own International (PCT) patent application WO 2008/129238 (which was unpublished as at the priority date of the present application) relating to titanium dioxide (TiO2) TFTs formed in a variety of ways, including spray pyrolysis.
Thus, according to a second aspect of the present invention there is provided a method of forming a thin-film field-effect transistor comprising: forming a dielectric layer adjacent a gate; forming a source region and a drain region; and forming a semiconductor layer on the dielectric layer; wherein the semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising: oxides other than titanium dioxide; oxide-based materials; mixed oxides; metallic type oxides; group I-IV, II-VI, IV-VI, V-VI and VIII-VI binary chalcogenides; and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides.
In relation to both the first and second aspects of the invention, preferable, optional, features are defined in the dependent claims.
Thus, preferably the semiconductor layer is deposited using a precursor solution. The precursor solution may be doped in order to incorporate dopant atoms in the semiconductor material once formed, which in turn may give rise to hole and/or electron transport and/or to higher charge carrier mobility in the semiconductor layer and/or induce/enhance additional physical properties. The dopant atoms may be selected from a group comprising: aluminium, indium, gallium, molybdenum, boron, nitrogen, lithium. Other dopants are also possible.
The spray pyrolysis may be performed at any suitable temperature according to the semiconductor material being deposited and the substrate used. The temperature may be in the range of 100° C. to 600° C., preferably in the range of 100° C. to 400° C., and more preferably in the range of 200° C. to 400° C.
The semiconductor layer may be sprayed in a raster fashion, although other deposition techniques are also possible.
The semiconductor layer may be deposited in a pulsed manner. By providing a time delay between successive sprays, this enables the solution vapours to adsorb to the substrate and convert to the semiconductor material.
Alternatively the semiconductor layer may be deposited in a continuous manner.
The method may further comprise heat treating the semiconductor layer to remove residual un-reacted precursor material(s).
In certain embodiments to be described below, the semiconductor layer is formed of zinc oxide. However, many alternative materials are possible.
Further, in certain embodiments, the source and drain regions may each be formed of titanium and gold layers, the titanium acting as an adhesion layer for the gold.
The gate may be conductive—for example, formed of a metal, or a conductive polymer, or conductive doped silicon.
To enable the fabrication of flexible devices or arrays, the gate and/or substrate and/or source and drain regions may formed of flexible materials.
The dielectric layer may be formed of an inorganic insulator, such as a metal oxide. Alternatively, the dielectric layer may be formed of an organic/polymer material, such as a perfluoropolymer, polystyrene, poly(methyl methacrylate), a crosslinkable monomer or polymer, a ferroelectric polymer, or a derivative or co-polymer of any of the above.
Some embodiments are based on top-gate transistor architectures. To form such a transistor, preferably the semiconductor layer is deposited before the dielectric layer, and the gate is formed after the dielectric layer. Preferably, the fabrication method further comprises treating the surface of the semiconductor layer with plasma (particularly preferably using oxygen plasma) prior to the deposition of the dielectric layer, as we have found that this can improve the performance of the transistor.
The method may be part of the fabrication process of a display device, an integrated (e.g. large area) electronic circuit, a memory device, or a sensor such as a UV light sensor, a gas sensor or a bio-sensor.
Embodiments of the invention will now be described, by way of example only, and with reference to the drawings in which:
In the figures, like elements are indicated by like reference numerals throughout.
The present embodiments represent the best ways known to the applicants of putting the invention into practice. However, they are not the only ways in which this can be achieved.
By way of introduction, as illustrated in
The embodiments of the invention seek to address both the issue of simple processing, and the control over film morphology, of the oxide semiconductor.
The spray pyrolysis technique may be used for the deposition of simple oxide films, mixed oxide films, metallic type oxides, group I-IV, II-VI, IV-VI, V-VI and VIII-VI binary chalcogenides, and group II-VI-VI and V-II-VI ternary chalcogenides. Films of such metal oxide and metallic spinel oxide materials prepared by SP have matching properties for a wide range of technological applications. Surprisingly, however, use of SP for the fabrication of TFTs is very limited. To provide the proof of concept we have demonstrated functional TFTs based on ZnO films deposited by SP. The experimental setup of the spray pyrolysis technique used here is shown in
For the TFT fabrication we employed prefabricated device structures similar to the one shown in
Step (1): The substrate 22 may be rigid or flexible depending on the application. In the present embodiments highly conductive Si++ is employed as the substrate 22, which also acts as the gate electrode 20, but this may be replaced by other materials.
Step (2): If the substrate 22 is not conducting then a conductive gate 20 has to be deposited. This can be a conductive polymer, metal, or any type of solid conductive substance (e.g. silicon, metal oxides, transparent metal oxides, etc). In the present embodiments the gate 20 is made using conductive doped silicon. However, flexible gates and substrates could also be used, made of metal foil or plastic, which would enable fabrication of flexible devices or arrays.
Step (3): The dielectric 18 is then deposited on the top of the gate 20. This is the standard process for a bottom-contact bottom-gate FET. In the present embodiments the dielectric is standard thermally-grown SiO2. However this layer can be any inorganic material having good insulating properties, or similarly-performing organic materials (small molecules, oligomers and polymers).
Step (4): The source electrode 14 (“S”) and the drain electrode 16 (“D”) are then deposited on top of the dielectric 18. In the present embodiment the source and drain electrodes 14, 16 are each made of titanium and gold layers, the titanium and gold layers having thicknesses of 10 nm and 100 nm respectively, which are vacuum deposited and patterned using standard photolithographic techniques. Here the titanium acts as an adhesion layer for the gold, since the latter will not stick to the SiO2 by itself. The role of the thin titanium layer is therefore not functional in terms of the electronic functionality of the device. However, other contact metals may alternatively be employed, as those skilled in the art will appreciate.
Step (5): Finally, the semiconductor layer 12 is deposited on the top of the prefabricated structure by spray pyrolysis.
In the present embodiments, deposition of the ZnO semiconductor layer was performed using a 0.2 M methanolic precursor solution of zinc acetate di-hydrate (
The film was grown in the following manner: The substrate was placed on the hot plate until the temperature was stabilised, then the solution was sprayed with the airbrush positioned vertically above the substrate in a raster fashion (
If required, once deposited, the semiconductor layer may be heat treated to remove any residual un-reacted precursor material(s) or unwanted atmospheric molecules/atoms (e.g. oxygen, water etc.).
The source and/or drain regions, and/or the gate, can also be deposited by spray pyrolysis, using appropriate conductive materials such as conductive oxides made using doped metal oxides (e.g. indium doped tin oxide, aluminium doped zinc oxide, to name but two).
As already described above, with the SP technique a precursor solution is pulverised by means of an inert carrier gas so that it arrives at the surface of the targeted substrate in the form of very fine droplets. Upon arrival the material droplets react chemically and convert to the desired chemical compound in the form of a film layer. The chemical reactants are selected such that the products other than the desired compound are volatile at the specific temperature so they do not stay on the surface of the substrate.
Other materials that could possibly be used as oxide semiconductors deposited by spray pyrolysis include:
We have proven the concept of SP deposition of oxide semiconductors to work with ZnO. Our most important findings are as follows:
Bottom-Gate Bottom-Contact ZnO Transistors
All our ZnO-based devices were found to exhibit electron transport with maximum mobilities in the range 0.1-20 cm2/Vs. The best mobilities were obtained for devices where ZnO was deposited at higher temperatures, i.e. >300° C. However, device fabrication at lower substrate temperatures (TS) i.e. 100<TS<250° C. is also believed to be possible. Thus, we anticipate the SP deposition method to be compatible with processing on plastic substrates (which may be flexible). The same also applies for the SD electrodes.
Bottom-Gate Top-Contact ZnO Transistors
ZnO TFTs based on bottom-gate top-contact architectures have also been realised. The specific bottom-gate top-contact transistor structure employed is shown in
In the device of
Doped Metal Oxide Films Deposited by Spray Pyrolysis
Another important feature associated with the SP technique is the ability to dope the deposited films by means of physical blending of the precursor materials prior to layer deposition. As an example we demonstrate doping of ZnO with aluminium (Al) to produce aluminium zinc oxide (AZO). This work is motivated by the fact that in the literature AZO has been found to exhibit higher charge mobility, and hence its potential for technological applications could be very significant. It should be emphasised that doping is not restricted to Al, and numerous other dopants (known from the literature and hence known to the person skilled in the art) could be employed. Example materials include indium (In), gallium (Ga), molybdenum (Mo), boron (B), nitrogen (N), lithium (Li) and several others. For SP such materials could be introduced in the form of precursor compounds. For instance, one could use the precursor acetamide (
Material Preparation and Deposition of AZO Films by SP
The AZO based TFT structure employed is the same as shown in
Specifically, the films were grown in the following manner. After placing the substrate on top of the hot plate, the solution was sprayed vertically above it in a raster fashion for a time duration of 1-50 seconds using an air brush. A time delay of 1-60 seconds was given before the second spray (in a similar manner) to enable the solution vapours to adsorb to the substrate. As those skilled in the art will appreciate, the deposition and delay times may be varied, and the process may be repeated between 1 and 50 (or more) times, depending on the desired properties of the film such as thickness and surface roughness etc.
Aluminium source and drain contacts (25 nm) were thermally evaporated using shadow masks. The resulting channel length and width were 60 μm and 1-1.5 mm, respectively. The output operating characteristics (drain current [ID] versus drain voltage [VD] at different gate voltages [VG]) of a TFT based on an AZO film are displayed in
Electron mobilities as high as 5 cm2/Vs were obtained from TFTs based on AZO (Al doping of 3%) deposited at 400° C. Although this value is smaller than that obtained from pristine ZnO based TFTs (
Alternative Device Architectures
In principle many alternative transistor architectures could be employed, other than the bottom-gate bottom-contact architecture of
Top-Gate ZnO Transistors
ZnO TFTs based on top-gate architectures have also been realised. The specific top-gate transistor structures employed are shown in
In the devices of
This is the first demonstration of a top-gate ZnO TFT fabricated by SP. Such a top-gate structure can be used in memory applications, particularly when combined with ferroelectric polymers such as PVDF derivatives or co-polymers.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0811962.0 | Jun 2008 | GB | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/GB09/01635 | 6/30/2009 | WO | 00 | 1/26/2011 |
