Patent Grant
7171975
This invention relates generally to the field of design, development and manufacturing of miniaturized chemical and biochemical analysis devices and systems using microelectromechanical systems (MEMS) technology, and more particularly to process sequences for fabricating MEMS and microfluidic devices and systems having fluid transport systems with any or all of the following attributes: (1) ultra-shallow depths; (2) well-controlled variations in channel depth; and (3) structures in the channels of sub-micrometer size.
The creation of channels in a substrate at a microminiaturized scale has many potential applications. When suitably enclosed so as to confine the motion of a fluid to the channel, these structures may be used to provide a well-defined flow path for liquids or gases. Microchannels serve a wide variety of purposes, ranging from mere routing of fluid flow from a source to a destination or partitioning of a source volume into multiple streams; to mixing of two or more fluids for purposes of dilution, multi-phase extraction, or reaction; to chemico-physical interaction of the channeled fluid with physical structures created in the channel, e.g., for chromatographic separation; to analysis of fluid components by means of optical probing and other detection techniques.
Academic and commercial efforts to develop and manufacture fluidic channel devices and systems have utilized a variety of materials. The choice of materials has been dictated by performance requirements of the finished devices, by available processing equipment, and by individually established experience and familiarity with certain materials. A large body of published research details work on silicon, quartz, glass and plastic substrates.
Much early work was done with glass substrates or slides, generally for reasons of familiarity and compatibility with extant detection systems, or of ability to electrically insulate voltages ranging up to 10 kV in electrokinetically-driven separations.
Quartz substrates have also been used for fabrication of microchannel-based devices and systems, despite difficulties in processing due to the material's hardness and relative inertness.
Due to economically attractive materials costs, a variety of plastics have been considered and evaluated as substrate materials for microchannels. Although incompatibility with fluidic constituents can limit choice of specific materials due to possible contamination of transported fluids, the relatively inexpensive cost of plastics vis-a-vis glass or silicon substrates has driven continued work for certain applications.
Silicon has been regarded as a potentially valuable substrate for a wide variety of microelectromechanical applications for several decades. The relatively recent growth of interest in silicon as a substrate for microfluidic devices and systems is, in part, attributable to the emergence of process equipment that is suitable for fabricating structures with better-defined architectures and high aspect ratios.
Shallow channels may be formed from any of these materials. Shallow channels typically may be fabricated having dimensions from 1 to 100 μm in width, 1 to 100 μm in depth, and 10 μm to 10 mm in length. These dimensions correspond to a cross-sectional area of 1 to 104 μm2 and total contained fluid quantities of 101 to 108 μm3, or 10 fL to 100 nL.
These dimensions offer the advantages of reduced fluid volume over macro systems. Very small quantities of fluids are needed to fill microchannels and, conversely, very small quantities of effluent fluid are produced. This constitutes a principal attraction of these structures.
Shallow channels also offer performance advantages: undesired dead volume originating from separate component interconnection can be significantly reduced or eliminated; operation time can be greatly lessened due to shortened fluid flow path lengths; more effective separations can be done due to increased surface-to-volume ratios; and greatly reduced quantities of solvents and reagents are required (with concomitant reduction of effluent volumes), as discussed previously.
Fabrication methods and equipment developed for the creation of standard semiconductor industry products like microprocessors, memory, and logic, and later used for the manufacturing of microelectromechanical systems (MEMS), are particularly well-suited for use in the creation of microfluidic channels in silicon. The art of creating intricate, multi-layer patterns in silicon and compatible materials through deposition, lithographic, and etching processes is extremely well developed and reproducible in those industries.
Dry etching of silicon, whether primarily physical in nature (ion-milling) or primarily chemical (plasma etching), is a highly evolved part of the overall MEMS fabrication process. Reactive-ion etching (RIE) is a method of etching that is a combination of physical and chemical mechanisms, and is the most commonly practiced embodiment of dry etching. RIE, through judicious selection and optimization of reactant gases, pressure, temperature, and power sources, can attain both a high degree of anisotropy as well as good selectivity (differentiation among unlike materials). A particular class of silicon etch processes has been considered specifically for high-aspect-ratio etching of silicon in MEMS applications.
Confinement of fluids to channels is an indispensable requirement for controlled operation of microfluidic devices and systems. Although three of the required four sides in a channel of rectangular cross-section may be formed as a natural consequence of the etching processes, the remaining side must be provided through additional process steps. There are a variety of methods by which a lid substrate may be attached to a channel substrate, including anodic bonding, fusion bonding, frit bonding, and attachment through the use of “glue” layers, generally organic in nature. Anodic bonding, when suitable for a given device and application, provides a strong, hermetic bond between a silicon substrate and a glass lid substrate.
Simple microfluidic systems may be enhanced by defining additional functionality in the fluidic device. The functionality defined may include electrospray ionization (ESI), liquid chromatography (LC), and integrated LC/ESI devices and systems. The additional functionality may be as simple as electrical contacts for purposes of effecting electrokinetic flow and separation in the channels. On the other hand, the incremental functionality may take the form of additional microstructures, such as nozzles for purposes of electrospray to transport fluids off-chip. Creation of the desired functionality can be commonly achieved by integration of appropriate additional patterns in design and layout as well as additional process operations. This offers a significant advantage over a system built by macroscopic assembly of individual components.
Other researchers have similarly considered microfluidic systems in which the basic functionality of microfluidic channels was enhanced through the creation of intra-channel structures.
Although device design for microfluidic applications entails consideration of often-challenging constraints that go beyond the basic creation of the microfluidic channels themselves, the fabrication of channels with dimensions of a micron or more as discussed above is generally straightforward.
Many applications have been identified and more are anticipated for channels that have been etched into a substrate such as silicon, glass, quartz, or fused silica with depth of channels typically ranging from 10 to 100 μm in depth. Such channels can be fabricated using known techniques. New applications are emerging, however, for channels that are 1/10– 1/1000 of those depths, i.e., depths ranging from approximately 10 to 1000 nm (“ultra-shallow channels”). Applications for ultra-shallow channels often require more precise tolerances than standard devices, thus increasing the fabrication challenge.
The typical etch processes described above are not capable of producing devices to such specification. RIE, for example, etches at rates that make sub-micron control difficult in any dimension. Also, whereas lateral dimensions are more easily varied (at least for critical dimensions greater than 1 μm) through layout in CAD, vertical differentiation of features (e.g., controllably varied channel depths) can be very difficult to achieve in currently-practiced processing schemes, and cannot be controlled at all reliably with sub-micron precision.
Fabrication of ultra-shallow channels is difficult to achieve with sufficient control for reproducibility in manufacturing. Standard etch processes and equipment are generally designed to maximize etch rate while maintaining at least a minimal level of other performance parameters like selectivity to masking materials. In the case of ultra-shallow channels, however, low etch rates are needed so as to afford an acceptable degree of precision. That is, in the absence of a detectable and definitive endpoint, etch depth is determined by etch time, given an established etch rate. For example, with a typical RIE etch rate of several micrometers per minute, a 50 nm channel would nominally require an etch time of only 1–2 seconds. Since there are transient plasma conditions after ignition that last several seconds during which etch rates and uniformities are not characteristic of the stabilized etch process, reproducibility of an etch of a few seconds duration is unachievable, and etch durations of less than two seconds produce inherently unreliable results.
There is a need for devices having ultra-shallow channels. Ultra-shallow channel devices meet some of the following requirements: minimizing fluid volume; maximizing interaction with channel surfaces (high surface-to-volume ratio); controlling the flow of a transported fluid in the laminar or molecular flow regime; acting as a filter for particles of greater dimension than the channel depth; and increasing the signal-to-noise (S/N) ratio for optical probing techniques by limiting the required depth of field in optical detection systems and other factors. Current state of the art processes cannot produce devices incorporating ultra-shallow channels reliably or repeatably.
The present invention addresses the aforementioned drawbacks by providing a method for producing devices having ultra-shallow channels.
We herein disclose a method whereby ultra-shallow channels may be fabricated with required precision and reproducibility. Any given etch process, to be effective, preferentially etches one material at a relatively fast rate, and is less effective in etching a second material that is simultaneously presented for etching. In such an example, the etch process is said to be selective for the first material, and selective to the second. The degree of selectivity is expressed as the ratio of the etch rate of the intended material to the etch rate of the unintended material. Standard fabrication processes utilize etch methods selective for the substrate sought to be etched in order to increase the efficiency of the process, controlling the etch of the substrate with a relatively non-reactive masking material patterned on the wafer. We achieve the required control necessary to create ultra-shallow channels in the substrate by reversing this process altogether, using an etch that is selective for the mask and to the substrate. This permits much more fine control of the rate of etch of the substrate. The disclosed method has been shown to have a precision of 5 nm or better, and can be used to reproducibly fabricate channels as shallow as 10 nm or less.
This method is compatible with either resist-masked etching or etching without resist mask. In one embodiment of the invention, silicon oxide is patterned as a mask over a silicon substrate, and an etch method selective for silicon oxide is employed on the patterned silicon wafer. The silicon oxide will be consumed at a much faster rate than the silicon according to well-established selectivity ratios. In this manner, by regulating the thickness of the silicon oxide mask, the exposed silicon can be etched with great precision.
In another alternative embodiment, a process designed to etch silicon preferentially to silicon oxide may be used to etch ultra-shallow channels in silicon oxide. Masking in this case would be done using lithographically patterned photoresist, for example.
In yet another embodiment, the method is used to etch structures other than fluidic channels to ultra-shallow depths. Any pattern that can be defined by lithographic means can be transferred to the desired depth using the disclosed method. For example, damascene (inlaid) structures may be fabricated using the disclosed method. Potential applications for this embodiment include, but are not limited to, the following: (1) Creation of metal or metal-like wires for conduction of electrical and/or thermal signals on the device, while preserving a planar top surface of the substrate so as not to impede bonding to another substrate. (2) Creation of an island of heterogeneously doped silicon/polysilicon (as compared to surrounding substrate material), with the additional refinement possible of electrically isolating the so-created island from the surrounding substrate by means of a thermally grown or deposited insulating material like silicon oxide between the substrate and the island. The island could serve as an etch stop for a dopant-dependent etch, for example. (3) Creation of structures that can subsequently, through additional process steps, be released from the surrounding substrate, thereby having suspended structures that are free to move except at designed anchor points. (4) Creation of features that can subsequently, through an embossing process, be transferred in relief to a removable material like a thermally-deformable plastic.
Fluidic channels or other features that have been fabricated by the disclosed method can be passivated if desired by subsequent thermal growth of silicon oxide or by conformal deposition of silicon oxide or silicon nitride. The ultra-shallow fluidic channels or structures so formed—whether passivated or unpassivated—are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
A method is also disclosed whereby stepped fluidic channels may be fabricated. Stepped fluidic channels are channels having two or more different discrete depths. Each channel segment corresponds to a separate masking and etching sequence. Any or all of the channel segments may be etched to ultra-shallow depths using the method previously disclosed. Any or all of the stepped channel segments may be ultra-shallow in depth. We also disclose means by which relatively deep channel segments may be produced contiguous to ultra-shallow segments. By thus combining normal etching with ultra-shallow etching, extreme variations in channel depth can be produced—e.g., 100 μm in combination with 10 nm segments, a 104 depth ratio. Such a structure could function as a kind of pressure relief, or overpressure, valve.
As in the case of channels and/or structures of ultra-shallow depth, the surfaces of stepped channels may be passivated by thermal growth of silicon oxide or by the deposition of a passivating film like silicon oxide or silicon nitride. The ultra-shallow fluidic channels or structures so formed are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
In a third aspect of the present invention, structures such as posts, weirs, flow steering/mixing barriers, etc., can be patterned within defined channel(s), and are formed at the same time as the channel walls when the channel is etched. Formation of such structures is entirely compatible with the former two aspects of the present invention. The structures may be formed in ultra-shallow channels, as well as any or all levels of a multi-stepped channel.
The tops of the structures can be made to be co-planar with the field region (the preferred embodiment) so as to facilitate and ensure sealing to a bonded surface and to prevent formation of a fluidic “sneak path”. Alternatively, the structures can be fabricated such that their tops can be at the level of the shallower channel in a stepped channel. This is accomplished by appropriate segregation of the structure patterns between masks corresponding to the separate channel segments.
As in the case of channels and/or structures of ultra-shallow depth(s), the surfaces of structures formed in the channels may be passivated by thermal growth of silicon oxide or by the deposition of a passivating film like silicon oxide or silicon nitride. The ultra-shallow fluidic channels or structures so formed are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
A microfluidic channel system is also disclosed, comprising a channel substrate (silicon, in one embodiment), to which is bonded a second substrate so as to provide a containing surface for the fluid. The second substrate can be passive, in the sense that it merely bounds the fluidic channel(s) in the channel substrate. Ingress and egress to/from the fluidic channel would functionally be a part of the channel substrate in this case. The second substrate may also provide access for optical probing techniques if suitably transmissive to the wavelengths of the probing electromagnetic light source. Alternatively, the second substrate can be active, in the sense that it provides access to the fluidic channels in the channel substrate in addition to its primary function of bounding the fluid channel(s).
In another embodiment, the fluidic channels can be continuous to the edge of the finished and diced device so as to provide means of fluidic ingress and/or egress to/from the fluidic channels.
Briefly stated, a method for etching an ultra-shallow channel includes using an etch process selective for one material on a different material that is selective to that same process in order to achieve a very precise channel depth in the different material. Channels as shallow as 10 nm can be fabricated in silicon with precision of 5 nm or better using the method. Stepped channels can be fabricated where each segment is a different depth, with the segments being between 10 nm and 1000 nm in depth. The method is applied to create a fluidic channel, which includes a channel substrate to which is bonded a lid substrate to confine fluids to the fluidic channels so fabricated.
According to an embodiment of the invention, a method for etching an ultra-shallow channel includes the steps of providing a substrate of a first material; forming a layer of a second material on at least part of said first material; selectively removing a portion of said second material such that said second material is completely removed in at least one area to expose at least one area of said first material and is at least partially persistent in areas adjacent to said at least one exposed area of said first material so as to provide direct etchant communication with said first material within said at least one exposed area and to prevent etchant communication with said first material in areas where said second material has not been completely removed, and such that said act of removing said portion of said second material does not significantly remove any of said first material; providing an etch process that is selective for said second material and selective to said first material, wherein said etch process preferentially etches said second material at a rate that is significantly greater than that at which said etch process would etch said first material; and applying said etch process to etch said first material to a desired depth of said ultra-shallow channel.
According to an embodiment of the invention, a method for etching an ultra-shallow channel includes the steps of providing a substrate of a first material; forming a masking layer of a second material on at least part of said first material; coating said masking layer with a photoresist layer; defining a pattern in said photoresist layer; transferring said pattern into said masking layer using a dry etching process selective for said second material at a first etch rate until said first material is exposed; and etching said exposed first material using said dry etching process at a rate less than said first etch rate until a desired depth of said ultra-shallow channel is achieved in said first material.
According to an embodiment of the invention, a method for etching an ultra-shallow channel includes the steps of providing a substrate of a first material; forming a masking layer of a known depth of a second material on at least part of said first material; determining a first etch rate of a dry etching process in said first material where said dry etching process is selective for said second material; determining a second etch rate of said dry etching process in said second material; coating said masking layer with a photoresist layer; defining a pattern in said photoresist layer; transferring said pattern into said masking layer using said dry etching process; and continuing etching said first material using said dry etching process until a desired depth of said channel is achieved in said first material, where a total time for etching said first and second materials is determined by dividing said desired depth in said first material by said first etch rate to obtain a first time, dividing said known depth of said masking layer by said second etch rate to obtain a second time, and adding said first and second times together to obtain said total time.
According to an embodiment of the invention, a method for etching an ultra-shallow channel includes the steps of providing a substrate of a first material; coating said first material with a photoresist layer; defining a pattern in said photoresist layer; transferring said pattern into said first material using a dry etching process selective for a material other than said first material until a desired depth of said channel is achieved in said first material.
According to an embodiment of the invention, a method for etching an ultra-shallow channel in a workpiece includes the steps of providing a substrate of a first material; forming a layer of a second material on at least part of said first material; coating said layer with a photoresist; defining a pattern in said photoresist; and transferring said pattern into said layer using a dry etching process selective for said first material until a desired depth of said channel is achieved in said second material.
According to an embodiment of the invention, a method for creating a structure that is attached to a substrate only at designated anchor points, thus permitting free movement of said structure except at said anchor points, includes the steps of providing a workpiece initially consisting of a substrate of a first material; forming a layer of a second material on at least part of said first material; coating said layer with a photoresist; defining a pattern for said anchor points in said photoresist; transferring said pattern into said layer using a dry etching process selective for said first material until a depth of said pattern in said second material extends to said substrate; depositing said first material in said pattern, thereby filling said pattern; smoothing said first material until a top side of said first material is coplanar with a top side of said second material; depositing said first material on said workpiece followed by patterning said first material; and etching, using a wet etch, to remove said second material, thereby leaving said patterned first material and said substrate connected only by non-patterned regions of said workpiece.
According to an embodiment of the invention, a method for etching a channel includes the steps of providing a substrate of a first material; forming a masking layer of a second material on at least part of said first material; coating said masking layer with a first photoresist layer; defining a first pattern for a first segment of said channel in said first photoresist layer; transferring said first pattern into said masking layer using a dry etching process selective for said second material at a first etch rate until said first material is exposed; etching, at a second etch rate, said exposed first material using said dry etching process until a desired depth of said first segment of said channel is achieved in said first material; removing said first photoresist layer from said masking layer; coating said masking layer and said first segment with a second photoresist layer; defining a second pattern for a second segment of said channel in said second photoresist layer; transferring said second pattern into said masking layer using said dry etching process selective for said second material until said first material is exposed; etching said exposed first material using said dry etching process until a desired depth of said second segment of said channel is achieved in said first material, wherein said first and second segments have different depths; and removing said second photoresist layer from said masking layer and said first segment.
According to an embodiment of the invention, a method for etching a channel in a workpiece includes the steps of providing a substrate of a first material as an initial form of said workpiece; forming a masking layer of a second material on at least part of said first material; coating said workpiece with a first photoresist layer; defining a first pattern for a first segment of said channel in said first photoresist layer; transferring said first pattern into said masking layer using a dry etching process selective for said second material until said first material is exposed; removing said first photoresist layer from said workpiece; coating a second photoresist layer on said workpiece; defining a second pattern for a second segment of said channel on said second photoresist layer, wherein said second pattern includes said first pattern as a subset; dry etching, after the step of defining said second pattern, said first pattern into said first material for a first period of time; transferring said second pattern into said masking layer using dry etching; and dry etching simultaneously, using said dry etching process and after the step of transferring said second pattern, said first and second patterns for a second period of time, such that the planar dimensions of said first pattern and said second pattern are reproduced in said substrate.
According to an embodiment of the invention, a method for etching a channel in a workpiece includes the steps of providing a substrate of a first material as an initial form of said workpiece; forming a masking layer of a second material on said workpiece; coating a first photoresist layer on said masking layer; defining a first pattern for first and second segments of said channel on said first photoresist layer; transferring said first pattern into said masking layer to a depth of an interface between said first material and said second material using dry etching; removing said first photoresist layer from said workpiece; coating a second photoresist layer on said workpiece; defining a second pattern on said workpiece, wherein said second pattern corresponds to said first segment of said channel; dry etching, after the step of defining said second pattern, said second pattern into said first material for a first period of time; removing said second photoresist layer from said workpiece; dry etching simultaneously, using said dry etching process and after the step of dry etching said second pattern, said first and second segments for a second period of time, such that the planar dimensions of said first segment and said second segment are reproduced in said substrate.
According to an embodiment of the invention, a method for making a plurality of posts in an ultra-shallow channel in a workpiece includes the steps of providing a substrate of a first material; forming a layer of a second material on at least part of said first material; coating said layer with a photoresist; defining a pattern for said plurality of posts in said photoresist such that said plurality of posts are masked from etching; and transferring said pattern into said layer using a dry etching process selective for said first material until a desired depth of said channel is achieved in said second material.
According to an embodiment of the invention, a method for etching a channel includes the steps of providing a substrate of a first material; forming a masking layer of a second material on at least part of said first material; coating said masking layer with a first photoresist layer; defining a first pattern for a first segment and a second segment of said channel in said first photoresist layer; transferring said first pattern into said masking layer using a dry etching process selective for said second material at a first etch rate until said first material is exposed; etching, at a second etch rate, said exposed first material using said dry etching process until a desired depth of said first and second segments of said channel is achieved in said first material; removing said first photoresist layer from said masking layer; coating said masking layer and said first and second segments with a second photoresist layer; defining a second pattern for a third segment of said channel in said second photoresist layer; transferring said second pattern into said masking layer using said dry etching process selective for said second material until said first material is exposed; etching said exposed first material using said dry etching process until a desired depth of said third segment of said channel is achieved in said first material, wherein said third segment is a different depth from said desired depth of said first and second segments; and removing said second photoresist layer from said masking layer and said first and second segments.
According to an embodiment of the invention, an integrated fluidic channel system includes a fluidic channel silicon substrate having a first surface and a second surface; said channel substrate defining a channel origination portion, a channel terminus portion, and a shallow or ultra-shallow channel extending between said channel origination portion and said channel terminus portion on at least said first surface, wherein said shallow or ultra-shallow channel includes at least a first segment that is between 10–1000 nm in depth; at least one of said channel origination portion, said channel terminus portion, and said channel being formed at least in part by reactive-ion etching; and a lid substrate having a first surface and a second surface, wherein said second surface of said lid substrate is attached to said first surface of said channel substrate to enclose said channel origination portion, said channel terminus portion, and said channel.
Additional features and advantages of the invention will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the invention as described herein, including the detailed description which follows, the claims, as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the invention, and together with the description serve to explain the principles and operation of the invention.
Reference will now be made in detail to the present exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
The first principal aspect of the present invention addresses the formation of shallow and ultra-shallow fluid transport channels. “Shallow” as used herein means depths ranging from 1 μm to 10 μm. “Ultra-shallow” as used herein means depths below a micron ranging from 10 nm to 1000 nm (1 μm). “Standard” as used herein means depths ranging from 10 μm–100 μm, while “deep” means depths greater than 100 μm. One micron is chosen as the dividing line between shallow and ultra-shallow because conventional methods of fabrication do not work reliably below one micron.
Methods of fabrication are disclosed whereby sub-micrometer channel depths can be reproducibly created using standard semiconductor processing equipment. Channel depths as little as 10 nm are readily achieved using the disclosed methods.
A second principal aspect of the invention addresses the formation of stepped fluid transport channels—i.e., channels of purposefully varying depth along well-defined segments of the channel. Methods of fabrication are disclosed whereby channel depths ranging from 10 nm to hundreds of micrometers may be produced, with sharp, well-defined transition between contiguous channel segments.
In addition to the two principal aspects of the present invention, an alternative embodiment is disclosed wherein microstructures may be created within the ultra-shallow channels, whether they are of a single uniform depth or comprising more than one segment with discretely varying channel depths. The aforementioned microstructures may be used to effect a variety of purposes, including mixing and chromatographic separation.
Lastly, an alternative embodiment is disclosed wherein ultra-shallow channels with or without stepped depths and with or without microstructures in the channel(s) are combined with a second substrate so as to comprise a microfluidic channel system. The system provides for the preservation of the performance advantages obtained by the creation of the aforementioned channels, ensuring that designed volumes and cross-sectional profiles are retained in a practical, working microfluidic channel device and/or system, preventing dead volume creation and out-of-channel fluidic leakage.
Ultra-shallow Fluidic Channels—Methods of Fabrication
The formation of fluidic channels having depths less than 1–2 μm presents serious issues of process control and reproducibility. In commonly available reactive-ion etch (RIE) tools and processes, silicon etch rate ranges from 1–7 μm per minute. Indeed, tool and process designs would generally have the goal of maximizing silicon etch rate while preserving at least certain levels of selectivity to masking materials like silicon oxide or photoresist. Further, the nature of the Bosch etch is cyclical—i.e., a short series of 2–5 second steps (a “loop”) is repeated for a user-chosen number of iterations, with each loop lasting about 12 seconds. This implies a best-case etch depth resolution of 0.2 μm, or 200 nm, with depths of 0.2, 0.4, 0.6 μm, . . . thus being available, but nothing between (or below 0.2 μm).
For precise control of cross-sectional dimensions, fluid volume and volumetric flow rates, it is generally necessary to have a fabrication process that would achieve etch-depth tolerances of less than ±5% and, for critical applications, less than ±1%. The etch depth resolution delivered by the standard etch process is therefore far too coarse to achieve targeted etch depths below 1–2 μm with precision.
Whereas established silicon etch tools and processes are developed to generally maximize silicon etch rate, they are simultaneously designed to minimize etch rates of common masking materials like silicon oxide or photoresist. Equivalently, the silicon etch rate is maximized while maintaining good selectivity to silicon oxide and photoresist, where selectivity is the ratio of silicon etch rate to mask etch rate. Common selectivity values range from 80:1–160:1 for oxide, 40:1–80:1 for photoresist. Conversely, equipment and etch processes that are designed to etch silicon oxide will have selectivity to silicon—that is, the etch rate of silicon oxide is high relative to that of silicon.
It will be appreciated that the present invention can be employed in the context of a semiconductor processing system for fabricating MEMS devices. Such a processing system might include, for example, a dry etcher configured to apply a dry etchant to at least one substrate (using a process such as reactive ion etching (RIE)) and a process controller coupled to the etcher. The process controller can be programmed to select a dry etchant having a predetermined etch rate relative to any particular substrate. While no one particular etchant is specifically preferred, it should be noted that the dry etchant can be a gas, such as CHF3. The process controller also can direct the etcher to apply the selected etchant to at least a portion of the substrate for a predetermined period of etching time, so that the dry etcher etches in the substrate to a predetermined submicron etch depth for a predetermined period of etching time.
The etch depth, etching rate, and etching time, singly or in combination, may be adjusted to form desired submicron microstructures in the substrate. For example, the etch rate associated with advantageous operation of such a semiconductor processing system might have a lower boundary of approximately 1.5 nm per second. Further, the predetermined period might have a lower boundary of approximately three seconds.
The present invention discloses the use of an etch process that is designed and optimized for etching silicon oxide (in preference to etching silicon) to etch silicon, so as to dramatically lower the silicon etch rate for purposes of precision in etching extremely shallow channels. This method has been demonstrated to achieve targeted etch depths with precision (deviation from target) of less than 5 nm.
The mechanism for silicon to silicon oxide selectivity is understood in terms of a fluorine-to-carbon ratio (F/C). As the F/C ratio is lowered through choice of etch gases, the tendency to etch silicon is reduced. Also as hydrogen is introduced to the primary fluorine-supplying etch gas, F atoms are scavenged, thereby lowering the F/C ratio, and contributing to the deposition of non-volatile etch residue on the silicon surface, inhibiting silicon etching. In areas of silicon oxide, oxygen is supplied from the oxide to scavenge carbon, increasing the F/C ratio locally and helping to maintain oxide etch rate. With etching of silicon depressed (through the addition of hydrogen) and the etching oxide sustained by oxygen (supplied from the oxide itself), selectivity of silicon to oxide is achieved.
The hydrogen needed to increase silicon:oxide selectivity can be supplied explicitly in the form of hydrogen gas (H2) in combination with a primary etchant gas like CF4, typically in volumetric concentrations of hydrogen ranging up to 40%. Alternatively, the hydrogen may be supplied by the primary etchant gas itself, as in the case of CHF3.
In the oxide etch process used to fabricate shallow-ultra-shallow channels as disclosed in the present invention, a single etch gas, CHF3, was used at a flow rate of 30 sccm and a pressure of 5 mT. Helium backside cooling at 3000 mT was used to maintain stable etch temperatures at the wafer surface and to thereby help conserve masking photoresist. Dual electrodes were used to generate the etch plasma, with the source electrode at 650 W and 15° C., and the substrate electrode at 85 W and 30° C.
The foregoing etch process parameters resulted in an oxide etch rate of 200 nm/min and a silicon etch rate of 95 nm/min. By comparison, the silicon etch rate in the standard Bosch silicon etch process is roughly 2000 nm/min or more, over twenty times faster. With a silicon etch rate of roughly 1.5 nm/sec in the oxide etch process, etch depth precision of 5 nm or better corresponds to a little over 3 seconds of etch time, which is easily achieved under machine program control.
With respect to machine program control, the present invention can be executed, and perhaps even enhanced, using the advantages associated with computer control of manufacturing processes. In the context of the present invention, well-known computer readable media, such as random access memory (RAM), read only memory (ROM, EROM E2ROM, etc.), CD/ROM, diskettes, optical media, magnetic media, electromagnetic media, wireline transmission media, wireless transmission media, fiber optic transmission media, or the like, can be used to store computer-executable instructions. The computer-executable instructions could then be executed by a computer associated with a MEMS fabrication system. Bearing in mind the processes described herein, the computer-executable instructions might include a method for making a microstructure, including selecting a dry etchant having a predetermined etch rate relative to a substrate, and directing an etcher to apply the selected etchant to at least a portion of the substrate for a predetermined period of etching time. The etchant is selected or formulated to etch in the substrate to a predetermined submicron etch depth during the predetermined period of etching time to thereby form submicron microstructures in the substrate.
Re-design of process tools can undoubtedly accomplish, at least to a degree, the significant reduction in silicon etch rate that is needed for precise control of ultra-shallow channel depths. This redesign would entail expenditure of significant non-recurring engineering funds.
Similarly, the existing etch process in extant etch equipment may be modified so as to effect, at least in part, a reduction in silicon etch rate, although this will likely come at the cost of increased maintenance due to excessively polymerizing etch chemistry, and/or reduction of process uniformity. The salient advantage of the present invention is its use of existing processes in existing etch equipment.
In an alternative embodiment, as shown in
Time=(target depth into silicon substrate 120)/(silicon etch rate in oxide etch)+(oxide film 105 thickness)/(oxide etch rate in oxide etch)
In an alternative embodiment (
The preferred embodiment is preferable to the latter alternative embodiment for several reasons. First, more precise patterning of small features is obtained on an oxide film as opposed to a bare silicon substrate, as discussed previously. Secondly, the amount of silicon etching is ultimately limited by the amount of available masking material—silicon oxide, photoresist, or both. The preferred embodiment would permit more extensive etching of silicon if needed because the oxide mask would persist through some additional etching after the photoresist mask was consumed.
After formation of the shallow fluid channel 125 as described in
Fluidic channels or other features that have been fabricated in silicon by the disclosed method can be passivated if desired for purposes of electrical or chemical isolation by subsequent thermal growth of silicon oxide or by conformal deposition of silicon oxide or silicon nitride. These processes will preserve the depth of the channel relative to the surrounding field region.
The ultra-shallow fluidic channels or structures so formed—whether passivated or unpassivated—are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
Stepped Fluidic Channels—Methods of Fabrication
Fluidic channels having two or more segments with intentionally different depths may be desired for a variety of purposes. Mixing of two or more fluids may be aided by disruption of an otherwise smooth, continuous flow path. Filtering of relatively large particles or precipitates may be effectively accomplished by constricting the fluid flow path in a vertical (or horizontal) dimension. Resolution of depth or volume-dependent analysis techniques directed at fluid in a channel can be improved in terms of signal-to-noise ratio by reducing the depth of the fluid in a detection/analysis region of the channel.
For the foregoing application and others, then, a channel with cross-sectional profiles like those shown in
The present invention discloses process methods whereby stepped ultra-shallow channels can be fabricated. These stepped channels can be combinations of two or more different ultra-shallow depths or, alternatively, combinations of one or more conventional channel depths with one or more ultra-shallow depths.
The process sequence for fabrication of a stepped fluidic channel comprising two ultra-shallow segments is shown in
Extension of the process method to fabrication of a fluidic channel with more than two discrete depths will be obvious to skilled practitioners of the art, each separate etch depth requiring its own lithographic patterning and etch.
Mask-to-mask (mis)alignment will inevitably lead to small regions of overlap between adjacent channel segments. In normal processing, this would mean that the region of overlap would be etched to a depth representative of the summation of the two adjacent segments, to first order. This may be acceptable for many applications, and may, in fact, be desirable for mixing purposes, the trough thereby created causing disordered flow (mixing).
The use of the latent masking process methodology, as described below, will prevent the creation of the etch trough because that methodology is inherently a self-aligned patterning scheme. That is, there is no overlap of adjacent patterns because one pattern (the one corresponding to the deeper channel segment) is a proper subset of the entire channel pattern. The problematic overlap only arises when adjacent segments are separately and distinctly patterned.
As in the case of the first principal aspect of the present invention—formation of a ultra-shallow fluidic channel having a single, uniform depth—the depths of the shallow-ultra-shallow segments of a stepped channel are limited only by persistence of masking material (photoresist). Typically, photoresist:oxide selectivities are on the order of 1:1, placing a practical limit of roughly the smallest feature size on etch depth (since coated photoresist thickness is generally held to less than or approximately equal to the smallest feature's dimension).
For channels other than those of ultra-shallow depth, the formation of stepped channels may be problematic due to difficulties inherent in coating/spinning photoresist over etched features having greater than approximately one-micrometer height or depth. Topographical discontinuities can cause coating defects, compromising attempts to perform subsequent patterning steps with fidelity to the intended design. There are several methods by which this obstacle may be overcome.
U.S. patent application Ser. No. 09/334,408 (Moon et al.) describes improved process methods for fabricating MEMS and microfluidic devices. In that application, methods denoted as SMILE (for simultaneous multi-level etching) and latent masking are disclosed as means for surmounting common constraints that inhibit or prevent multi-level patterning of a surface due to interference of etched topography with subsequent photoresist spinning. The inventions disclosed in the Ser. No. 09/334,408 application provide enhanced design flexibility and improved manufacturability for MEMS and microfluidic devices. Reference is made to U.S. patent application Ser. No. 09/334,408, which is incorporated herein by reference as though fully set forth in its entirety, for a more detailed explanation of the SMILE process.
The SMILE process methodology was developed specifically for the purpose of overcoming patterning difficulties due to topographical discontinuities. In the present context of microfluidic channels,
Latent masking is conceptually similar to the SMILE methodology, essentially reversing the order of pattern etching from the previous (SMILE) example. In this case, an initial patterning of both channel segments would be done and etched into the underlying silicon oxide layer, stopping at the oxide/silicon interface. A second patterning is then done, coating photoresist and patterning it so as to create openings corresponding to a first channel segment. The first segment is etched into silicon to a certain depth, after which the photoresist is removed. The remaining oxide mask is then used to mask a second etch which is stopped when targeted etch depths are achieved. As in the case of SMILE processing, the first segment would be the segment with the greater depth target. The amount of the initial etch would be offset from the final etch depth target by the amount of the second targeted depth.
In an alternative embodiment of the present invention, etch depth may be varied continuously, rather than discretely, by taking advantage of the etch lag effect. This effect, arising from steadily increasing difficulty in getting reactive species into and etch by-products out of high-aspect-ratio features, is manifested as a monotonically decreasing etch depth as the lateral dimension of the etch pattern is decreased. If the device's required functionality, then, is compatible with flexibility in layout design, the depth of the fluid channel can be increased (decreased) by increasing (decreasing) the width of the channel as seen in plan and cross-sectional views in
As in the case of channels and/or structures of ultra-shallow depth, the surfaces of stepped channels may be passivated by thermal growth of silicon oxide or by the deposition of a passivating film like silicon oxide or silicon nitride. These processes will preserve the depth of the channel relative to the surrounding field region provided that any remaining masking oxide is removed prior to the growth or deposition.
The stepped ultra-shallow fluidic channels or structures so formed—whether passivated or unpassivated—are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
Structures in Fluidic Channels—Methods of Fabrication
Both of the principal aspects of the present invention—ultra-shallow channels and stepped channels—may be used in alternative embodiments wherein the fluid channels so fabricated may be populated by structures of various kinds, including, but not limited to, posts, weirs, and sub-channel.
The creation of desired structures in the fluid channels can be accomplished simultaneously with formation of the channels themselves. The lithographic mask—or, in the case of stepped channels, the several masks—would define patterns corresponding to the desired structure in addition to defining the extents of the channels themselves.
Referring to
Referring to
In the case of stepped channels, intra-channel features can be created, the tops of which are, by design, not co-planar with the surrounding field region.
As in the instances of channels and/or structures of ultra-shallow depth(s), the surfaces of structures formed in the channels may be passivated by thermal growth of silicon oxide or by the deposition of a passivating film like silicon oxide or silicon nitride. These processes will preserve the depth of the channel relative to the surrounding field region.
The ultra-shallow fluidic channels or structures so formed—whether passivated or unpassivated—are compatible with a variety of bonding methods for purposes of providing a necessary containing surface for the channels.
Microfluidic Channel System
We also disclose a fluidic channel system, comprising a ultra-shallow and/or stepped fluidic channel substrate to which a second fluid-confining substrate is attached. The purpose of the second substrate is to provide the otherwise missing surface to form an enclosed channel.
The principal requirements of the attachment method are (1) preservation of designed volume (i.e., minimization, preferably elimination, of offset between channel substrate and lid substrate); (2) hermetic containment of fluid (i.e., no lateral leakage out of the channel); (3) ability to withstand up to several hundred psi fluid pressure without delamination/detachment; (4) prevention of the intrusion of any bonding media into the channels or the channels' ingress and egress openings.
Anodic bonding is the preferred embodiment of the system. Other attachment methods may be used in alternative embodiments, including, but not limited to, fusion bonding methodologies, frit bonding, and adhesion bonding, generally with less complete satisfaction of the aforementioned system requirements.
The anodic bonding process is practiced in the preferred embodiment as a means of attaching the lid substrate 905 to the channel substrate 910 to form a fluid channel system 900. A critical requirement for successful anodic bonding is that both substrates must be essentially particle- and contamination-free on the bonding surface. Standard cleaning methodologies will generally suffice to ensure a proper degree of cleanliness. As shown in
Fluidic channel systems are thus formed in which fluid flow is confined to defined channels. Through the formation of ultra-shallow channels, extremely small volumes of fluid may be directed from source to destination. The system so described is fully compatible with channels of a single depth, stepped channels, and with unstepped or stepped channels containing intra-channel structures.
According to the present invention, a microfluidic channel system which includes at least one MEMS device is contemplated. The MEMS device might include a first substrate that has at least one microstructure formed in the first substrate. The at least one microstructure includes at least one channel structure of submicron channel depth, such as in the range of between about 20 nm and about 1,000 nm.
As described herein, the microstructure typically includes a cover substrate bonded (by, for example, anodic, fusion, frit, or adhesion bonding) to the first substrate, the cover substrate being configured to enclose the at least one channel structure and hermetically seal the MEMS device. The MEMS device also might include a fluid ingress port disposed in either the first substrate or the cover substrate (or both) in fluidic communication with the at least one channel structure, and a fluid egress port disposed in either the first substrate or the cover substrate (or both) in fluidic communication with the fluid ingress port via the at least one channel structure.
Microfluidic channel systems according to the invention can have many varieties, depending on, for example, the functionality one skilled in the art wishes to impart to the systems. Thus, for example, the MEMS device could include multiple substrates, multiple channel structures, or a single channel structure with one or more sub-channels. Further, and in accordance with the present invention, preferentially shaped structures, such as posts or weirs, could be disposed in any given channel. Each MEMS device used in the microfluidic channel system could also include other microstructures, such as fluid reservoirs, or fluid reservoirs connected by channels.
Microfluidic channel systems, and other systems according to the present invention, are well-suited for use in the context of systems for carrying out industrial processes, such as electrospray ionization (ESI) and liquid chromatography (LC), and the like.
A system for performing such processes might include, by way of example, one or more MEMS devices (as described herein), one or more application specific integrated circuits (ASICS), and a computer. The ASIC(s) could be configured, for example, to monitor and/or control the MEMS devices in accordance with instructions stored on and/or executed by the computer.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
This application claims priority under 35 U.S.C. §119(e) based on U.S. Provisional Application Ser. No. 60/356,493 filed Feb. 12, 2002 and entitled FABRICATION OF SHALLOW AND ULTRA-SHALLOW CHANNELS FOR MICROFLUIDIC DEVICES AND SYSTEMS, incorporated herein by reference in its entirety.
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| Number | Date | Country | |
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| 20030178075 A1 | Sep 2003 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60356493 | Feb 2002 | US |
