Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells

Abstract

A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

Description

BACKGROUND

Chip-Scale Atomic Clocks (CSACs) include vapor cells that contain vapors of an alkali metal such as rubidium (Rb). The vapor cells also typically contain a buffer gas, such as an argon-nitrogen buffer gas blend. The standard technique for fabricating the vapor cells involves anodically bonding two glass wafers on opposing sides of a silicon wafer having a plurality of cell structures that define cavities. The alkali metal vapor and buffer gas are trapped in the cavities of the cell structures between the two glass wafers.

The anodic bond joint starts at the locations between the wafers that are initially in contact and spreads out as the electrostatic potential brings the surfaces together. This lag of the bond front from one area to the next can lead to pressure differences in the vapor cells. Additionally, the presence of a low boiling temperature material like Rb requires the bonding to take place at as low a temperature as possible, otherwise the vapor generated can foul the bond surface. Thus, a high voltage needs to be applied as the wafers are heating, to allow the bond to form as soon as possible. This can result in vapor cells sealing at different times, and thus at different temperatures, which can result in pressure differences in the vapor cells, even on cells that are fabricated side-by-side on the same wafer.

Further, total thickness variations in the two glass wafers cause some of the vapor cells to become hermetically sealed before other vapor cells on the same set of wafers. This problem is further exacerbated in that the temperature is gradually ramped in the bonder equipment, driving some of the trapped gas out of vapor cells that bond late. In addition, there are no easy escape paths for buffer gas that gets trapped in regions that bond late, which can lead to pressure differences in the vapor cells.

SUMMARY

A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings. Understanding that the drawings depict only typical embodiments and are not therefore to be considered limiting in scope, the invention will be described with additional specificity and detail through the use of the accompanying drawings, in which:

FIG. 1 is a cross-sectional schematic depiction of a physics package for a chip-scale atomic clock that includes a vapor cell according to one embodiment;

FIG. 2 is a schematic diagram of one embodiment of a vapor cell die for a chip-scale atomic clock that has been formed on a wafer layer; and

FIG. 3 is partial plan view of a wafer with a plurality of vapor cell dies and vent channels according to one embodiment.

DETAILED DESCRIPTION

In the following detailed description, embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be utilized without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense.

Fabrication techniques are provided for enhancing gas pressure uniformity in anodically bonded vapor cells used in Chip-Scale Atomic Clocks (CSACs). In general, the vapor cells are fabricated with a pair of optically clear glass wafers that are anodically bonded to opposing sides of a substrate such as a silicon wafer having a plurality of cell structures. The vapor cells are fabricated prior to assembly within a physics package for the CSAC.

In one approach for enhancing gas pressure uniformity during vapor cell fabrication, a design feature is incorporated into a wafer surface that creates interconnected vent channels that provide a path from each vapor cell die in the wafer to the perimeter of the wafer. The vent channels allow gas near the interior of the wafer to be in substantially continuous pressure-equilibrium with gas outside of the wafer during anodic bonding. In another approach for enhancing gas pressure uniformity, the anodic bonding process is modified to continually ramp pressure upward as temperature is ramped upward.

The foregoing approaches can be combined such that utilizing the vent channels in the silicon wafer surface along with pressure ramping allows vapor cells that are sealed later in the process, and thus at higher temperature, to also have a higher gas pressure. When cooled to room temperature, the vapor cells sealed at a higher temperature will drop in pressure more than those sealed at a lower temperature. With a higher gas pressure, the later sealing vapor cells can be compensated so the final pressure of all vapor cells is about the same at room temperature.

Further details of the present fabrication techniques are described hereafter with reference to the drawings.

FIG. 1 illustrates a CSAC 100 according to one embodiment, which can employ a vapor cell fabricated according to the present approach. The CSAC 100 includes a physics package 102, which houses various mechanical and electronic components of CSAC 100. These components can be fabricated as wafer-level micro-electro-mechanical systems (MEMS) devices prior to assembly in physics package 102. In general, the CSAC components in package 102 include a laser die 110 such as a vertical-cavity surface-emitting laser (VCSEL), a quarter wave plate (QWP) 120 in optical communication with laser die 110, a vapor cell 130 in optical communication with QWP 120, and an optical detector 140 in optical communication with vapor cell 130.

A laser beam 104 emitted from laser die 100 is directed to pass through QWP 120 and vapor cell 130 to optical detector 140. As shown in FIG. 1, QWP 120, vapor cell 130, and optical detector 140 can be mounted within package 102 at various tilt angles with respect to the optical path of laser beam 104. Tilting these components reduces reflective coupling back into the VCSEL, enhancing CSAC stability.

The vapor cell 130 includes a pair of optically clear glass wafers 132 and 134 that are anodically bonded to opposing sides of a substrate such as a silicon wafer 136. Exemplary glass wafers include Pyrex glass or similar glasses. At least one chamber 138 defined within vapor cell 130 provides an optical path 139 between laser die 110 and optical detector 140 for laser beam 104.

In one approach for fabricating vapor cell 130 prior to assembly within package 102, glass wafer 132 is initially anodically bonded to a base side of substrate 136, after which rubidium or other alkali metal (either in liquid or solid form) is deposited into chamber 138. The glass wafer 134 is then anodically bonded to the opposing side of silicon wafer 136 to form vapor cell 130. Such bonding typically is accomplished at temperatures from about 250° C. to about 400° C. The bonding process is performed with the wafers 132, 134, 136 either under high vacuum or backfilled with a buffer gas, such as an argon-nitrogen gas mixture. When the buffer gas is used, the manufacturing equipment containing the components for vapor cell 130 is evacuated, after which the buffer gas is backfilled into chamber 138. Thus, when the bonding is completed to seal vapor cell 130, the alkali metal and optional buffer gas are trapped within chamber 138.

During the anodic bonding process, the glass wafers, which contain mobile ions such as sodium, are brought into contact with the silicon wafer, with an electrical contact to both the glass and silicon wafers. Both the glass and silicon wafers are heated to at least about 200° C., and a glass wafer electrode is made negative, by at least about 200 V, with respect to the silicon wafer. This causes the sodium in the glass to move toward the negative electrode, and allows for more voltage to be dropped across the gaps between the glass and silicon, causing more intimate contact. At the same time, oxygen ions are released from the glass and flow toward the silicon, helping to form a bridge between the silicon in the glass and the silicon in the silicon wafer, which forms a very strong bond. The anodic bonding process can be operated with a wide variety of background gases and pressures, from well above atmospheric to high vacuum. Higher gas pressures improve heat transfer, and speed up the process. In the case of Rb vapor cells, it is desirable to form a bond at as low a temperature as possible, in the presence of a buffer gas.

FIG. 2 illustrates one embodiment of a vapor cell die 200 for a CSAC that has been formed on a wafer layer. The vapor cell die 200 includes a silicon substrate 205 in which a first chamber 210, a second chamber 220, and at least one connecting pathway 215 have been formed. The chambers 210, 220, and pathway 215 are sealed within vapor cell die 200 between glass wafers (such as glass wafers 132, 134) using anodic bonding as described above.

For the embodiment shown in FIG. 2, chamber 210 comprises part of the optical path for the CSAC and needs to be kept free of contaminants and precipitates. The rubidium or other alkali metal (shown generally at 235) is deposited as a liquid or solid into chamber 220. The connecting pathway 215 establishes a “tortuous path” (illustrated generally at 230) for the alkali metal vapor molecules to travel from second chamber 220 to first chamber 210. Because of the dynamics of gas molecules, the alkali metal vapor molecules do not flow smoothly through pathway 215, but rather bounce off of the walls of pathway 215 and frequently stick to the walls. In one embodiment, second chamber 220 is isolated from pathway 215 except for a shallow trench 245 to further slow migration of alkali metal vapor from the second chamber 220.

Further details related to fabricating a suitable vapor cell for use in the CSAC are described in copending U.S. application Ser. No. 12/873,441, filed Sep. 1, 2010, and entitled APPARATUS AND METHODS FOR ALKALI VAPOR CELLS, the disclosure of which is incorporated herein by reference.

As discussed previously, the anodic bond joint starts at the locations between the wafers that are initially in contact and spreads out as the electrostatic potential brings the surfaces together. This lag of the bond front from one area to the next can lead to pressure differences if there is no path for gas to move out from between the wafers as the bond fronts move together. This can result in poor buffer gas uniformity in the fabricated vapor cells.

Furthermore, using a low melting temperature material like Rb requires the bonding to take place at as low a temperature as possible, otherwise the vapor generated can foul the bond surface. Thus, a high voltage needs to be applied as the wafers are heating, to allow the bond to form as soon as possible. This can result in vapor cells sealing at different times, and thus at different temperatures, which can also produce pressure differences in the fabricated vapor cells.

The problem of poor buffer gas uniformity in fabricated vapor cells can be solved using the techniques discussed hereafter.

In one approach, vent channels are formed in a surface of the silicon wafer in order to provide pathways for gas to escape to a perimeter of the wafer during anodic bonding. This approach is illustrated in FIG. 3, which shows a wafer 300 for fabricating vapor cells used in a CSAC. The wafer 300 includes a plurality of vapor cell dies 302 and interconnected vent channels 304 that surround vapor cell dies 302. The vapor cell dies 302 and vent channels 304 are located in an interior surface region 306 of wafer 300. The vent channels 304 can be formed with the same processes used to form vapor cell dies 302.

The vent channels 304 provide at least one pathway for gas from each vapor cell die to travel outside of a perimeter 308 of wafer 300. The vent channels 304 allow gas toward the interior surface region 306 to be in substantially continuous pressure-equilibrium with gas outside of perimeter 308 during anodic bonding of glass wafers to opposing sides of wafer 300.

In another approach for enhancing gas pressure uniformity, the anodic bonding process is modified to continually ramp pressure upward as temperature (measured in degrees Kelvin, or degrees absolute) is ramped upward. In this approach, anodic bonding of a first wafer such as a silicon wafer is carried out by increasing a temperature of the first wafer at predetermined rate during anodic bonding of the first wafer to a second wafer such as a glass wafer. The silicon wafer has a plurality of dies each with at least one chamber. A gas pressure between the first and second wafers is also increased at a predetermined rate while the temperature is increasing during anodic bonding.

For example, in one implementation, as the temperature is increased from about 150° C. (423° K) to about 350° C. (623° K) during anodic bonding, the pressure is increased from about 296 torr to about 436 torr.

The foregoing approaches can be combined such that utilizing the vent channels in the wafer surface along with pressure ramping allows vapor cells that are sealed later in the process, and thus at higher temperature, to also have a higher gas pressure. When cooled to room temperature, the vapor cells sealed at a higher temperature will drop in pressure more than those sealed at a lower temperature. With a higher gas pressure, the later sealing vapor cells can be compensated so the final pressure of all vapor cells is about the same at room temperature. By keeping the ratio of the pressure to the temperature constant, the ideal gas law ensures than n (the molar density of the gas in the cells) will remain constant across the wafer.

The present invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is therefore indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

1. A method of fabricating vapor cells, comprising: forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter;forming a plurality of interconnected vent channels in the first wafer, the vent channels providing at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer;anodically bonding a second wafer to one side of the first wafer; andanodically bonding a third wafer to an opposing side of the first wafer, wherein the vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

2. The method of claim 1, wherein the first wafer comprises a silicon wafer.

3. The method of claim 2, wherein the second and third wafers comprise glass wafers.

4. The method of claim 1, wherein each of the vapor cells are configured for a chip-scale atomic clock.

5. The method of claim 1, wherein during the anodic bonding, a temperature of the first wafer is ramped upward at a predetermined rate.

6. The method of claim 5, wherein a gas pressure is ramped upward at a predetermined rate while the temperature is ramped upward.

7. The method of claim 5, wherein the temperature is ramped upward from about 150° C. (423° K) to about 350° C. (623° K) during the anodic bonding.

8. The method of claim 6, wherein the gas pressure is ramped upward from about 296 torr to about 436 torr during the anodic bonding.

9. The method of claim 5, wherein each of the vapor cell dies comprise a substrate having a first chamber, a second chamber, and at least one connecting pathway between the first and second chambers.

10. A wafer structure for fabricating vapor cells, comprising: a first wafer comprising a plurality of vapor cell dies, the first wafer having an interior surface region and a perimeter; anda plurality of interconnected vent channels in the first wafer, the vent channels providing at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer during anodic bonding of the first wafer;wherein the vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during anodic bonding of a second wafer to one side of the first wafer and a third wafer to an opposing side of the first wafer.

11. The wafer structure of claim 10, wherein the first wafer comprises a silicon wafer.

12. The wafer structure of claim 10, wherein the second and third wafers comprise glass wafers.

13. The wafer structure of claim 10, wherein each of the vapor cells dies is configured for a chip-scale atomic clock.

14. The wafer structure of claim 10, wherein each of the vapor cell dies comprise a substrate having a first chamber, a second chamber, and at least one connecting pathway between the first and second chambers.