The present disclosure relates to a fan test device.
Typically, a fan test device has a first connector to connect to a motherboard and a second connector to connect a fan. The first and second connectors look similar to each other which may cause confusion. The fan test device may be damaged when the connections are incorrect.
Many aspects of the present disclosure can be better understood with reference to the following drawing. The components in the drawing are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure.
The FIGURE is a circuit diagram of an embodiment of a fan test device of the present disclosure.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” The reference “a plurality of” means “at least two.”
The FIGURE shows an embodiment of a fan test device 10 of the present disclosure.
The fan test device 10 can comprise a first connector J1, a second connector J2, a first electronic switch Q1, a second electronic switch Q2, a control chip U1, a resistor R1, a resistor R2, a diode D1, a diode D2, an alarm module 20, a first power terminal V, a fuse FS1, and a fuse FS2.
As illustrated, a first terminal of the first electronic switch Q1 can be connected to a control pin RC5 of the control chip U1. A power pin 1 of the first connector J1 is connected to a second terminal of the first electronic switch Q1. A third terminal of the first electronic switch Q1 is connected to a cathode of the diode D1. An anode of the diode D1 is coupled to the power pin 1 of the first connector J1 through the fuse FS1. A signal pin 2 of the first connector J1 is coupled to a signal pin TACH1 of the control chip U1 through the resistor R1. A sensing pin 3 of the first connector J1 is connected to a sensing pin SENSE1 of the control chip U1. A ground pin 4 of the first connector J1 is grounded.
A first terminal of the second electronic switch Q2 is connected to a control pin RC4 of the control chip U1. A power pin 1 of the second connector J2 is connected to a second terminal of the second electronic switch Q2. A third terminal of the second electronic switch Q2 is connected to the first power terminal V. The third terminal of the second electronic switch Q2 is also connected to a cathode of the diode D2. An anode of the diode D2 is coupled to the power pin 1 of the connector J2 through the fuse FS2. A signal pin 2 of the second connector J2 is coupled to a signal pin TACH2 of the control chip through the resistor R2. A sensing pin 3 of the second connector J2 is connected to a sensing pin SENSE2 of the control chip U1. A ground pin 4 of the second connector J2 is grounded. The fuse FS1 and the fuse FS2 are used to prevent damage from excess current.
When the first connector J1 is connected to a motherboard and the second connector J2 is connected to a fan, the motherboard outputs a first signal to the sensing pin SENSE1 of the control chip U1 through the sensing pin 3 of the first connector J1. The control chip U1 outputs a low level signal, such as logic 0, to the first terminal of the first electronic switch Q1. The first electronic switch Q1 is turned off. A voltage from the motherboard is output to the first power terminal V through the power pin 1 of the first connector J1, the fuse FS1, the anode of the diode D1, and the cathode of the diode D1 in that order. The fan outputs a second signal to the sensing pin SENSE2 of the control chip U1 through the sensing pin 3 of the second connector J2. The control chip U2 outputs a high level signal, such as logic 1, to the first terminal of the second electronic switch Q2 through the control pin RC4. The second electronic switch Q2 is turned on. The voltage from the motherboard is input to the power pin 1 of the second connector J2 through the first power terminal V. Thus, the motherboard supplies power to the fan. The control chip U1 receives a third signal of a speed of the fan through the signal pin 2 of the second connector J2 and the signal pin TACH2. The control chip U1 outputs the third signal to the motherboard through the signal pin TACH1 and the signal pin 2 of the first connector J1 when the control chip U1 determines that the speed of the fan is abnormal.
When the first connector J1 is connected to the fan and the second connector J2 is connected to the motherboard, the motherboard outputs the first signal to the sensing pin SENSE1 of the control chip U1 through the sensing pin 3 of the second connector J2. The control chip U1 outputs a low level signal to the first terminal of the second electronic switch Q2. The second electronic switch Q2 is turned off. The motherboard outputs the voltage to the first power terminal V through the power pin 1 of the second connector J2, the fuse FS2, the anode of the diode D2, and the cathode of the diode D2 in that order. The fan outputs the second signal to the sensing pin SENSE1 of the control chip U1. The control chip U1 outputs a high level signal to the first terminal of the first electronic switch Q1. The first electronic switch Q1 is turned on. The motherboard supplies power to the fan. The control chip U1 receives the third signal through the signal pin 2 of the first connector J1 and the signal pin TACH1. The control chip U1 outputs the third signal to the motherboard through the signal pin TACH2 and the signal pin 2 of the second connector J2 when the control chip U1 determines that the speed of the fan is abnormal.
The alarm module 20 comprises a resistor R3 and a light emitting diode (LED) D3. An anode of the LED D3 is connected to a second power terminal P5V. The second power terminal P5V is used to input a high level signal. In the embodiment, the second power terminal P5V is connected to the first power terminal V. When the control chip U1 determines that the speed of the fan is abnormal, the control chip U1 outputs a low level signal through the alarm pin Alarm. When the control chip U1 determines that the speed of the fan is normal, the control chip U1 outputs a high level signal through the alarm pin Alarm.
In the embodiment, the first and second electronic switches Q1 and Q2 are both n-channel filed effect transistors (FETs).
The fan test device operates normally either when the first connector J1 is connected to the motherboard and the second connector J2 is connected to the fan or when the first connector J1 is connected to the fan and the second connector J2 is connected to the motherboard.
While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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2013101982188 | May 2013 | CN | national |