1. Technical Field
The disclosure generally relates to a testing system, and especially to a system for testing a fan in a computer.
2. Description of Related Art
With the development of the computer industry, operating frequencies of most components in computer systems have increased, and the heat generated by these components has increased as well. If the heat is not removed in a timely fashion, the computer system may overheat and the system could be damaged or destroyed. Usually, a fan is used for preventing the temperature in the computer system from becoming too high. Generally, the faster the fan rotates, the faster it can remove heat. These fans need to be tested before being used in computer systems. In general, testers need to test parameters of the fans such as rotational speed, rated voltage, and rated current. However, a typical testing method requires engineers to operate a special test apparatus and record the output voltages of the fan, which is inefficient and expensive.
Therefore there is a need for improvement in the art.
Many aspects of the embodiments can be better understood with references to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
In general, the word “module,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language, such as, for example, Java, C, or Assembly. One or more software instructions in the modules may be embedded in firmware, such as an EPROM. It will be appreciated that modules may comprise connected logic units, such as gates and flip-flops, and may comprise programmable units, such as programmable gate arrays or processors. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of computer-readable medium or other computer storage device.
Referring to
Referring to
The indication module 30 includes a LED D1, the alarm module 40 includes a buzzer LS1. A buzzer LS1 anode is electrically connected to the I/O terminal PB6. A LED D1 anode is electrically connected to the I/O terminal PB7. A buzzer LS1 cathode and a LED D1 cathode are grounded. The fan 300 includes a pulse control signal input terminal PC0, a rotational speed signal output terminal PC1, a power terminal PC2 and a ground terminal PC3. The I/O terminal PB0 is electrically connected to the pulse control signal input terminal PC0. The rotational speed signal output terminal PC1 is electrically connected to the I/O terminal PB1. A variable resistor R1 grounds the power terminal PC2. The power terminal PC2 is configured to receive a +12V DC voltage. The analog input terminal PA0 is electrically connected to a variable resistor R1 adjusting terminal. The ground terminal PC3 is electrically connected to the analog input terminal PA1. A first resistor R2 grounds the ground terminal PC3. A second resistor R3 grounds the ground terminal PC3 and a toggle switch S1 that are connected in series.
The switch module 20 includes a first push switch S2, a second push switch S3 and a third push switch S4. The first push switch S2 grounds the reset terminal RESET. The second push switch S3 grounds the I/O terminal PB4. The third push switch S4 grounds the I/O terminal PBS. When the first push switch S2 is pushed, the micro controller 10 is initialized. When the second push switch S3 is pushed, the micro controller 10 outputs sequential pulse control signals at the I/O terminal PB0; and when the third push switch S4 is pushed, the micro controller 10 outputs intervallic pulse control signals at the I/O terminal PB0. The crystal oscillator J1 grounds the oscillator signal input terminal X1 and the oscillator signal output terminal X2. The A frequency of the crystal oscillator J1 is 16 MHZ. The crystal oscillator J1 is configured to generate a 24 MHZ pulse control signals at the I/O terminal PB0.
Referring to
The conversion circuit 60 includes a voltage level conversion chip U2, and capacitors C5˜C9. In one embodiment, the voltage level conversion chip U2 is a MAX232 type chip for RS-232 standard interface circuit of computer. The voltage level conversion chip U2 includes charge terminals C1+, C1−, V+, V−, C2+, C2−, data transforming terminals T1 IN, T1 OUT, R1 IN, R1 OUT, a power terminal VCC, and a ground terminal GND. The charge terminal C1+ is electrically connected to the charge terminal C1− via the capacitor C5. The charge terminal C2+ is electrically connected to the charge port C2− via the capacitor C6. The charge terminal V+ is electrically connected to the +5V DC voltage via the capacitor C7. The charge terminal V− is grounded via the capacitor C9. The charge terminals C1+, C1−, V+, V−, C2+, C2− and capacitors C5, C6, C7, C9 form a charge pump circuit for generating a +12V voltage and a −12V voltage which are provided to the RS-232 standard interface circuit. The voltage level conversion chip U2 power port VCC is electrically connected to the +5V DC voltage. The voltage level conversion chip U2 power port VCC is grounded via the capacitor C8. The data transforming port T1 IN acts as a voltage level signal receiving terminal for receiving the rotational speed signals, rotational voltages and rotational currents from the I/O terminal PB3. The data transforming port T1 OUT acts as a voltage level signal transmitting terminal for transmitting the converted rotational speed signals, rotational voltage signals and rotational current signals to the control device 200. The data transforming port R1 IN acts as a voltage level signal receiving terminal for receiving the test complete signal from the control device 200. The data transforming port R1 OUT acts as a voltage level signal transmitting terminal for transmitting the converted test complete signal to the I/O terminal PB2.
During testing, the fan 300 is electrically connected to the testing system as shown in
The control device 200 stores a plurality of normal rotational voltages and rotational currents value under different rotational speeds. The control device 200 compares the rotational speeds, rotational voltages and rotational currents from the micro controller 10 with the plurality of normal rotational voltage and rotational current values, and outputs the test complete signal or an abnormal signal to the micro controller 10 according to the comparison result. The micro controller 10 outputs the indication signal to the indication module 30 when it receives the test completed signal. The indication module 30 emits light to indicate that the fan 300 is rotating under a normal rotational speed when it receives the indication signal. The micro controller 10 outputs the alarm signal when it receives the abnormal signal. The alarm module 40 makes a sound to indicate that the fan 300 is rotating under an abnormal rotational speed when it receives the alarm signal.
It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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201010503129.6 | Oct 2010 | CN | national |