Fast cycle slip detection and correction

Abstract

A method of detecting and correcting cycle slip in a data stream including sync symbol blocks and data symbol blocks prior to feedback carrier recovery is described. A phase ambiguity angle is computed upon detecting a last sync symbol of a sync symbol block in the data stream. A cycle slip corrector initiates cycle slip correction upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream. The corrected data stream is provided to a feedback carrier recovery circuit.

Description

TECHNICAL FIELD

The present principles relate to a method and apparatus for fast cycle slip detection and correction for improved communications in satellite systems.

BACKGROUND OF THE INVENTION

The phase detector of carrier recovery circuitry has different stable points. For Multiple Phase Shift Keying (MPSK), stable points are given on 2π/M separated constellation points, where M is the order of modulation. This is usually termed as “phase ambiguity of 2π/M”. Separate de-rotation logic must be used to correct phase ambiguity and de-rotate symbols back to the correct constellation for the forward error correction (FEC) logic that follows de-rotation. During the carrier tracking or acquisition phase, the phase estimate of the phase detector usually fluctuates around the aforementioned stable points. If the noise introduced into the carrier recovery loop passes a certain threshold, phase estimation may be pushed into neighborhood stable constellation points. This effect is called cyclic slip, which may cause errors in the FEC as the de-rotation logic needs to follow the new stable point. Signaling constellations typically have some degree of rotational symmetry, which provides the origin for a 2π/M phase ambiguity. A QAM (Quadrature Amplitude Modulation)/QPSK (Quadrature Phase Shift Keying) constellation has fourfold symmetry, and is equally likely to lock to one of its four rotations. 8 PSK (8 Phase Shift Keying) has 8-fold symmetry. Since carrier recovery loops are structured with little delay to track phase noise in a system, loop errors are often derived from slicer decisions, so that any 2π/M rotation is a viable lock point for the loop. When the correct phase is established, noise of a sufficient magnitude may push the loop from one lock point to another, since both lock points are local minima for the tracking loop.

Traditionally, de-rotation logic relies on known symbols (or training symbols) to remove the phase ambiguity. Given known (training) symbols, there is only one valid rotation for the constellation. Other systems examine the error rate—if all the loops are locked, but the error rate is high, it is probable that the rotation is wrong and another rotation is used. The system will step through different rotations until a suitable rotation is reached. However, this takes time and an FEC requires a significant amount of time to begin decoding valid data, which can include hundreds or thousands of symbols, or more. However, using this traditional method, a whole block of data may be corrupted, until a point where a block with known symbols arrives at the receiver and de-rotation logic is able to rotate the constellation points to the correct phase.

SUMMARY OF THE INVENTION

These and other drawbacks and disadvantages of the prior art are addressed by the present principles, which are directed to methods and apparatus for fast cycle slip detection and correction for improved communications in satellite systems.

According to an aspect of the present principles, there is provided a method and apparatus for fast cycle slip detection and correction for improved communications in satellite systems.

A method of detecting and correcting cycle slip and an apparatus that detects and corrects cycle slip in a data stream, including sync symbol blocks and data symbol blocks, prior to feedback carrier recovery is described. A phase ambiguity angle is computed upon detecting a last sync symbol of a sync symbol block in the data stream. A cycle slip corrector initiates cycle slip correction upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream. The corrected data stream is provided to a feedback carrier recovery circuit.

The data stream may further include pilot symbol blocks. Computation of a phase ambiguity angle may be performed in response to detecting a last pilot symbol of a received pilot symbol block in the data stream. The sync symbols may be represented by r[s+i]=exp(jφ)t[i]+w[i], i=0, . . . , N−1 where s represents the starting index of the sync symbols, N represents the number of sync symbols, t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i]. The phase ambiguity angle may be represented by

$\phi \in \left\{\frac{2\pi k}{M},k=0,1,\dots ,M-1\right\}.$

The phase ambiguity angle may also be represented by

$\hat{\phi }=\underset{\phi \in \left\{\frac{2\pi k}{M},k=0,1,\dots ,M-1\right\}}{\arg \min }\mathrm{angle}\left(\sum _{i=0}^{N-1}r\left[s+i\right)t^{*}\left[i\right]\right)-\phi ,$

where angle (•) represents the operation to compute the angle and (•)* represents the complex conjugate operation necessary to compute the angle. Cycle slip correction is performed by using the operation represented by r[s+i]exp{j({circumflex over (φ)}^(k-1)−{circumflex over (φ)}^(k))}.

The method and apparatus described above may also be implemented in a method for detecting and correcting cycle slip and an apparatus that detects and corrects cycle slip in a data stream prior to feedforward carrier recovery.

These and other aspects, features and advantages of the present principles will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a shows a diagram of a feed-back carrier recovery circuit for implementing cycle slip detection and correction;

FIG. 1 b shows a diagram of a feed-forward carrier recovery circuit for implementing cycle slip detection and correction implemented in ry;

FIG. 2 shows an exemplary DVB-S2 signal transmitted to the cycle slip detection and correction feed-back and feed-forward carrier recovery loops;

FIG. 3 shows a flow chart detailing the steps taken to perform cycle slip detection and correction according to present principles.

DETAILED DESCRIPTION OF THE INVENTION

Features and aspects of described implementations may be adapted for other implementations. Although implementations described herein may be described in a particular context, such descriptions should in no way be taken as limiting the features and concepts to such implementations or contexts.

The implementations described herein may be implemented in, for example, a method or process, an apparatus, or a software program. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation or features discussed may also be implemented in other forms (for example, an apparatus or program). An apparatus may be implemented in, for example, appropriate hardware, software, and firmware. The methods may be implemented in, for example, an apparatus such as, for example, a computer or other processing device. Additionally, the methods may be implemented by instructions being performed by a processing device or other apparatus, and such instructions may be stored on a computer readable medium such as, for example, a CD, or other computer readable storage device, or an integrated circuit. Further, a computer readable medium may store the data values produced by an implementation.

As should be evident to one of skill in the art, implementations may also produce a signal formatted to carry information that may be, for example, stored or transmitted. The information may include, for example, instructions for performing a method, or data produced by one of the described implementations. The signal may take a variety of forms, including for example, the signal may be analog, digital, and the signal may be baseband or modulating a carrier frequency suitable for transmission. Further, the signal may be recorded on computer readable medium.

Additionally, many implementations may be implemented in one or more of an encoder, a pre-processor to an encoder, a decoder, or a post-processor to a decoder. The implementations described or contemplated may be used in a variety of different applications and products. Some examples of applications or products include set-top boxes, cell phones, personal digital assistants (PDAs), televisions, personal recording devices (for example, PVRs, computers running recording software, VHS recording devices), camcorders, streaming of data over the Internet or other communication links, and video-on-demand.

Further, other implementations are contemplated by this disclosure. For example, additional implementations may be created by combining, deleting, modifying, or supplementing various features of the disclosed implementations.

An approach for detecting cyclic slip and removing its effect before a carrier recovery loop is reached is described herein. Detecting cyclic slip before the carrier recovery loop is advantageous for reducing the probability of data corruption introduced by cycle slips. Herein is described the detection of cycle slips and correction of its effects before a data stream reaches carrier recovery circuitry.

In FIG. 1a, a diagram of the cycle slip detection and correction in feed-back carrier recovery circuitry 101 is shown. The received signal after the first de-rotator 103 is denoted as r[n] (FIG. 2) and the corresponding received sync symbols of a DVB-S2 signal are denoted as

r[s+i],i=0, . . . , N−1  (1)

where s represents the starting index of the sync symbols and N represents the number of sync symbols. Thus the received sync symbols r[s+i] (FIG. 2) can be expressed as

r[s+i]=exp(jφ)t[i]+w[i],i=0, . . . , N−1  (2)

where the phase ambiguity angle for MPSK signals is represented by

$\begin{array}{cc}\phi \in \left\{\frac{2\pi k}{M},k=0,1,\dots ,M-1\right\}& \left(3\right)\end{array}$

t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i]. The phase ambiguity angle is estimated and represented by

$\begin{array}{cc}\hat{\phi }=\underset{\phi \in \left\{\frac{2\pi k}{M},k=0,\dots ,M-1\right\}}{\arg \min }\mathrm{angle}\left(\sum _{i=0}^{N-1}r\left[s+i\right]t^{*}\left[i\right]\right)-\phi & \left(4\right)\end{array}$

where angle (•) represents the operation to compute the angle and (•)* represents the complex conjugate operation necessary to compute the angle. The phase ambiguity angle represents a symbol in a possible stable rotation for a constellation.

Cycle slip detector/corrector 105 computes a phase ambiguity angle {circumflex over (φ)}^(k) when the sync symbols arrive and compares the current angle with a previous angle {circumflex over (φ)}^(l-1). If the two angles are different, cycle slip detector/corrector 105 provides an indication that a cycle slip has occurred. Cycle slip correction circuitry (not shown) is then activated in order to compensate for the adverse effects of the cycle slip. The mathematical operation for correcting cycle slip is represented by

r[s+i]exp{j({circumflex over (φ)}^(k-1)−{circumflex over (φ)}^(k))}  (5)

Slicer 113 receives a signal and slices the signal in order to optimize the signal for further processing. CTL (Computation Tree Logic) 111 performs logical operations on the signal to further prepare the signal for phasing by phasor 109. Phasor 109 calculates a sine wave representation of the signal. Phase shifter 107 shifts the sine wave to provide a time shifted delayed phase for use in cycle detection by cycle slip detector/corrector 105.

In FIG. 1b, a diagram of the cycle slip detection and correction in feed-forward carrier recovery circuitry 151 is shown. Calculations performed using cycle slip detector/corrector 155 are identical to calculations performed in cycle slip detector/corrector 105 of FIG. 1a. Slicer 163 slices the derotated signal and optimizes the signal for cycle slip detection. FF (feed forward) phase rotator 165 adjusts the phase of the incoming signal from cycle slip detector/corrector before sending the adjusted signal to phasor 159 that calculates a sine wave representation of the signal.

The embodiments shown in FIGS. 1a and 1b are advantageous because cycle slip detection and correction are both performed before a signal reaches a carrier recovery circuit or stage. This results in a more efficient and effective way of limiting cycle slips which may cause corruption and interruption of data flow through satellite systems.

FIG. 2 shows an exemplary DVB-S2 signal transmitted to the cycle slip detection and correction feed-back and feed-forward carrier recovery loops. SYNC symbols are shown as being inserted between data packets or symbols. In one embodiment of the present arrangement, cycle slip detection relies on known symbols or training symbols within a transmitted data stream for detecting phase ambiguity. For example, in DVB-S2, there are known sync symbols placed before data symbols or packets as shown in FIG. 2. Sync symbols are used to signify that data symbols or packets follow. DVB-S2 signals may also contain pilot symbols, not shown in FIG. 2, for cyclic slip detection. The exemplary data signal shown in FIG. 2 may be transmitted to the hardware implementations shown in FIGS. 1a and 1b.

A flow chart of an algorithm for cycle slip detection and correction as performed by cycle slip detector/corrector 105 and 155 is shown in FIG. 3. At step 301, Sync and data symbols are received after de-rotation. At step 303, the cycle slip detector/corrector detects if the k-th block of sync symbols (or last block of sync symbols in a sync block) has arrived. If the k-th block of sync symbols has not arrived, step 301 is repeated. If the k-th block of sync symbols has arrived, step 305 is performed, in which phase ambiguity angle {circumflex over (φ)}^(k) is computed using equation (4) shown above. At step 307, phase ambiguity angle {circumflex over (φ)}^(k) is compared with a previous phase ambiguity angle {circumflex over (φ)}^(l-1) that is stored by either the feedback or feedforward implementations shown in FIGS. 1a and 1b. If both angles match, then the process ends at step 311. If both angles do not match, step 309 is performed and cycle slip correction in a known manner is initiated.

The present description illustrates the present principles. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the present principles and are included within its spirit and scope.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the present principles and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

Moreover, all statements herein reciting principles, aspects, and embodiments of the present principles, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Thus, for example, it will be appreciated by those skilled in the art that the block diagrams presented herein represent conceptual views of illustrative circuitry embodying the present principles. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (“DSP”) hardware, read-only memory (“ROM”) for storing software, random access memory (“RAM”), and non-volatile storage.

Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

Claims

1. A method of detecting and correcting cycle slip in a data stream, including sync symbol blocks and data symbol blocks, prior to feedback carrier recovery, comprising computing a phase ambiguity angle upon detecting a last sync symbol of a sync symbol block in the data stream;initiating cycle slip correction, at a cycle slip corrector, upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream; andproviding the corrected data stream to a feedback carrier recovery circuit.

2. The method of claim 1, wherein the data stream further includes pilot symbol blocks.

3. The method of claim 2, wherein computing a phase ambiguity angle is performed in response to detecting a last pilot symbol of a received pilot symbol block in the data stream.

4. The method of claim 1, wherein the sync symbols are represented by r[s+i]=exp(jφ)t[i]+w[i],i=0, . . . , N−1 where s represents the starting index of the sync symbols, N represents the number of sync symbols, t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i].

5. The method of claim 1, wherein the phase ambiguity angle is represented by

6. The method of claim 1, wherein the phase ambiguity angle is represented by

7. The method of claim 1, cycle slip correction is performed by using the operation represented by r[s+i]exp{j({circumflex over (φ)}(k-1)−{circumflex over (φ)}(k))}.

8. An apparatus that detects and corrects cycle slip in a data stream, including sync symbol blocks and data symbol blocks, prior to feedback carrier recovery, comprising a cycle slip detector, that computes a phase ambiguity angle upon detecting a last sync symbol of a received sync symbol block;a cycle slip corrector, that initiates cycle slip correction upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream; andan output that provides the corrected data stream to a feedback carrier recovery circuit.

9. The apparatus of claim 8, wherein the data stream further includes pilot symbol blocks.

10. The apparatus of claim 9, wherein the phase ambiguity angle is computed in response to detecting a last pilot symbol of a received pilot symbol block.

11. The apparatus of claim 8, wherein the sync symbols are represented by r[s+i]=exp(jφ)t[i]+w[i],i=0, . . . , N−1 where s represents the starting index of the sync symbols, N represents the number of sync symbols, t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i].

12. The apparatus of claim 8, wherein the phase ambiguity angle is represented by

13. The apparatus of claim 8, wherein the phase ambiguity angle is represented by

14. The apparatus of claim 8, cycle slip correction is performed by using the operation represented by r[s+i]exp{j({circumflex over (φ)}(k-1)−{circumflex over (φ)}(k))}.

15. A method of detecting and correcting cycle slip in a data stream, including sync symbol blocks and data symbol blocks, prior to feedforward carrier recovery, comprising computing a phase ambiguity angle upon detecting a last sync symbol of a received sync symbol block;initiating cycle slip correction, at a cycle slip corrector, upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream; andproviding the corrected data stream to a feedforward carrier recovery circuit.

16. The method of claim 15, wherein the data stream further includes pilot symbol blocks.

17. The method of claim 16, wherein computing a phase ambiguity angle is performed in response to detecting a last pilot symbol of a received pilot symbol block.

18. The method of claim 15, wherein the sync symbols are represented by r[s+i]=exp(jφ)t[i]+w[i],i=0, . . . , N−1 where s represents the starting index of the sync symbols, N represents the number of sync symbols, t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i].

19. The method of claim 15, wherein the phase ambiguity angle is represented by

20. The method of claim 15, wherein the phase ambiguity angle is represented by

21. The method of claim 15, cycle slip correction is performed by using the operation represented by r[s+i]exp{j({circumflex over (φ)}(k-1)−{circumflex over (φ)}(k))}.

22. An apparatus that detects and corrects cycle slip in a data stream including sync symbol blocks and data symbol blocks prior to feedforward carrier recovery, comprising a cycle slip detector, that computes a phase ambiguity angle upon detecting a last sync symbol of a received sync symbol block;a cycle slip corrector, that initiates cycle slip correction upon determining the computed phase ambiguity angle is different from a previous computed phase ambiguity angle to generate a corrected data stream;an output that provides the corrected data stream to a feedforward carrier recovery circuit.

23. The apparatus of claim 22, wherein the data stream further includes pilot symbol blocks.

24. The apparatus of claim 23, wherein the phase ambiguity angle is computed in response to detecting a last pilot symbol of a received pilot symbol block.

25. The apparatus of claim 22, wherein the sync symbols are represented by r[s+i]=exp(jφ)t[i]+w[i],i=0, . . . , N−1 where s represents the starting index of the sync symbols, N represents the number of sync symbols, t[i] represents the known sync symbol and has a constant amplitude denoted by A, and noise embedded in the received signal is denoted by w[i].

26. The apparatus of claim 22, wherein the phase ambiguity angle is represented by

27. The apparatus of claim 22, wherein the phase ambiguity angle is represented by

28. The apparatus of claim 22, cycle slip correction is performed by using the operation represented by r[s+i]exp{j({circumflex over (φ)}(k-1)−{circumflex over (φ)}(k))}.