1. Field of the Invention
The present invention relates to latch and register circuits, and more particularly to a fast dynamic register.
2. Description of the Related Art
Dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. In many dynamic register circuits, the data had to be held while the clock was at a particular state, which was significantly disadvantageous for certain clock signals at or near 50% duty cycle. In a fast path of a digital circuit, buffers were often required to hold the data for the requisite amount of time. Buffers, however, consume valuable space and power. One method of reducing the hold time was to provide a pulsed clock generator. A pulse clock generator, however, also consumes valuable space and power.
There is a need for providing a fast dynamic register circuit with minimal setup and hold times without the overhead of buffers and/or pulsed clock circuits.
A fast dynamic register circuit according to one embodiment includes first and second precharge circuits, a full keeper circuit and an output circuit. The first precharge circuit precharges a first precharge node high while a clock node is low, maintains the first precharge node high after the clock node goes high when a data node is low, discharges the first precharge node low if the data node is high when the clock node goes high, and keeps the first precharge node discharged low while the clock node is high if the first precharge node was discharged low when the clock node went high. The second precharge circuit precharges a second precharge node high while the clock node is low, and discharges the second precharge node low if the first precharge node remains high after the clock node went high. The full keeper circuit keeps a state of the second precharge node immediately after either one of the first and second precharge nodes switches state while the clock node is high. The output circuit drives an output node to a state based on the second precharge node immediately after either one of the first and second precharge nodes switches state after the clock signal goes high and which otherwise maintains a state of the output node.
The fast dynamic register circuit may be implemented as a multiple input NOR logic gate in which multiple data nodes form the inputs. In this case, the first precharge circuit precharges the first precharge node high while the clock node is low, maintains the first precharge node high after the clock node goes high when each of the data nodes is low, discharges the first precharge node low if any of the data nodes are high when the clock node goes high, and keeps the first precharge node discharged low while the clock node is high if the first precharge node was discharged when the clock node went high.
The fast dynamic register circuit may be implemented as a multiple input NAND logic gate. In this case, multiple first precharge circuits are provided, each precharging a corresponding one of multiple first precharge nodes high while the clock node is low, each maintaining a corresponding one of the first precharge nodes high after the clock node goes high when a corresponding data node is low, each discharging a corresponding first precharge node low if a corresponding data nodes is high when the clock node goes high, and each keeping a corresponding first precharge node discharged low while the clock node is high if the corresponding first precharge node was discharged low when the clock node went high. Also, the second precharge circuit precharges the second precharge node high while the clock node is low and discharges the second precharge node low if at least one first precharge node remains high after the clock node goes high.
An integrated circuit, according to one embodiment includes combinatorial logic which provides a data signal and a fast dynamic register for registering the data.
A method of registering data according to one embodiment includes precharging a first precharge node high while a clock node is low, maintaining the first precharge node high after the clock node goes high when a data node is low, discharging the first precharge node low if the data node is high when the clock node goes high, keeping the first precharge node discharged low while the clock node is high if the first precharge node was discharged low when the clock node went high, precharging a second precharge node high while the clock node is low, discharging the second precharge node low if the first precharge node remains high after the clock node went high, keeping a state of the second precharge node immediately after either one of the first and second precharge nodes switches state while the clock node is high, and asserting an output node to a state based on the second precharge node immediately after either one of the first and second precharge nodes switches state after the clock signal goes high and otherwise maintaining a state of the output node.
The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:
The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The present inventor has observed that dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. In many dynamic register circuits, the data had to be held while the clock was at a particular state, which was significantly disadvantageous for certain clock signals at or near 50% duty cycle. In a fast path of a digital circuit, buffers were often required to hold the data for the requisite amount of time. Buffers, however, consume valuable space and power. One method of reducing the hold time was to provide a pulsed clock generator. A pulse clock generator, however, also consumes valuable space and power. The present inventor has therefore developed a fast dynamic register, as will be further described below with respect to
In operation of the fast dynamic register 100, PC1 and PC2 are pre-charged high to VDD while CLK is low. When CLK goes high, D is effectively sampled by the precharge circuit 102 which either maintains PC1 high or discharges PC1 low. If PC1 remains high, PC2 is discharged low by the precharge circuit 104. When PC2 is discharged low, QB goes high (or stays high). If PC1 is discharged low, then PC2 stays high and QB goes low (or stays low). Once either PC1 or PC2 discharges low while CLK is high, the output QB of the fast dynamic register 100 is determined and the D signal may change state without changing QB. The state of QB is determined by the state of PC2 relatively quickly after the rising edge of CLK. In this manner, the hold time of the register 100 is relatively short. When CLK goes back low, the PC1 and PC2 signals are once again pre-charged high and the state of QB is maintained by the precharge circuit 106.
In operation of the precharge circuit 102, when CLK is low P1 is turned on precharging node 103 pulling the PC1 signal high to VDD. The output of the inverter I1 is low so that N3 is off, and N2 is also off. When CLK goes high, P1 is turned off and N2 and N4 are turned on. If D is high when CLK goes high, then node 103 is discharged via N1 and N2 so that PC1 goes low. After PC1 goes low, any change of D is inconsequential and does not change the state of PC1. Also, the output of the inverter I1 of the clocked half-keeper circuit 202 goes high turning on N3. In this manner, node 103 is kept discharged via N3 and N4 to VSS so that PC1 is kept low while CLK is high. If instead D is low when CLK goes high, then N1 is off so that node 103 remains charged and PC1 remains high. PC1 is maintained at a high logic level while CLK is high. It is noted that if D goes from low to high while CLK is high, node 103 is discharged pulling PC1 low. As described further below, however, if PC1 remains high when CLK goes high, PC2 is discharged low relatively quickly. Once PC2 is discharged low, PC2 remains low even if PC1 is subsequently pulled low while CLK is high, so that the change of the input D signal is inconsequential. In this manner, the fast dynamic register 100 has a relatively minimal hold time in that the state remains registered once either PC1 or PC2 is pulled low.
In operation of the precharge circuit 104, when CLK is low, P2 is on which pre-charges node 105 to VDD thus pulling PC2 to a high logic level. The inverter I2 drives node 301 high so that node 301 is pre-charged high and CLKB is high. Although PC1 is pre-charged high as previously described, N5 is off since CLKB is also high. When CLK goes high, P2 is turned off and inverter I2 begins discharging node 301 low. If PC1 remains high after CLK goes high (such as when D is low), then N5 turns on as CLKB decreases so that PC2 is pulled low by the inverter I2. If instead PC1 is pulled low (such as when D is high) after CLK goes high, then N5 remains off so that PC2 remains high.
In operation of the output circuit 106, when CLK is low, N6 is off and PC2 is precharged high turning off P3 and turning N7 on thereby discharging node 403. If the inverter I3 asserts Q high (such as from a prior cycle), then P4 is off and N8 is on pulling PO low via N7 and N8 thereby keeping Q high. Q and PC2 are both high so that QB is low. Otherwise, if the inverter I3 asserts Q low, then N8 is off and P4 is on so that PO is pulled high via P4 and P5. In this case, QB is high. The devices P4, P5, N7 and N8 and the inverter I3 collectively operate as a full keeper circuit to maintain the state of PO and Q while CLK is low.
When CLK goes high, N6 is turned on and P5 is turned off. It is noted that when CLK initially goes high while PC2 is high and if PO was also high, N6 and N7 are both turned on to discharge node 401 to begin pulling PO low. If PC1 stays high (such as when D is low), then the inverter I2 discharges nodes 301 and 105 relatively quickly so that PC2 drops sufficiently fast before node 401 is discharged by a significant amount. As PC2 decreases, N7 begins turning off to reduce discharge current from node 401 while P3 begins turning on to add charging current to node 401. Thus, if PO is initially high, it momentarily “glitches” below VDD. When PC2 is sufficiently low, P3 is turned on and N7 is turned off so that PO is pulled back high. The devices N5, N6 and N7, and the inverter I2 are configured such that the voltage of node 401 does not drop significantly during this condition so that PO remains at a logic high level, so that the inverter I3 maintains Q low. If instead PO was initially low when CLK goes high and PC1 stays high, then this condition is inconsequential and PO is eventually pulled high by P3 when PC2 goes low. When PO is high, the inverter I3 pulls Q low. In either case, Q goes low turning P4 on. When CLK next goes back low, P5 turns on pulling PO high via P4 and P5 to maintain Q low. In either case, QB remains high.
If instead PC1 is pulled low (such as when D is high) after CLK goes high, then N5 remains off so that PC2 remains high. N6 is turned on and node 401 is discharged low to pull PO low via N6 and N7. Thus, if PO was high it goes low, and if PO was already low, then it does not change state in response to CLK going high. In this case the inverter I3 pulls Q high turning N8 on to pull PO low via N8 and N7 to maintain the high state of Q. Since PC2 and QB are both high, QB is low. When CLK next goes low, PC1 and PC2 are once again pre-charged high and the states of Q and QB are maintained.
In operation of the keeper circuit 108, when CLK is low, PC2 is pre-charged high as previously described and the inverter I4 drives PC2B low turning on P7 and turning off N9. Thus, PC2 is pulled high via P6 and P7. When CLK goes high, if PC2 stays high and is not otherwise driven low, the inverter I4 maintains PC2B to keep PC2 pulled high via P6 and P7. If PC2 is driven low by the inverter I2, then the inverter 14 switches to pull PC2B high turning on N9 and turning off P7. PC2 is pulled low via N9 and N10 while CLK is high. When CLK goes back high, PC2 is once again pre-charged high pulling PC2B low. In an alternative embodiment, the full keeper circuit 108 is configured as a clocked full keeper circuit using clock signals CLK and CLKB as understood by those of ordinary skill in the art.
CLK goes back low at about time t6. The inverter I2 pulls CLKB high and P2 pre-charges PC1 back high at subsequent time t7 and PC2 stays high. Since Q is high after time t6, N8 is turned on keeping PO low, so that the inverter I3 keeps Q high while CLK is low. At subsequent time t8, D goes low just before CLK goes back high at subsequent time t9. N1 is turned off so that PC1 remains high just after time t9. The inverter I2 pulls CLKB low at time t10 turning N5 on since PC1 remains high. The inverter I2 further pulls PC2 low at subsequent time t11 as N5 turns on. As PC2 goes low, it turns P3 on which pulls PO high at subsequent time t12. Also, the output circuit 106 pulls QB high at about time t12. The inverter I3 pulls Q low at subsequent time t13 in response to PO going high. Anytime after time t11 when PC2 is low, D may change state without affecting operation. As shown at 604, D toggles several times after time t11 with no effect on the signals PC2, PO, Q or QB. This is true even though PC1 goes low in response to D going high as shown at 606, where PC1 stays low until precharged once again when CLK next goes low at time t14. When CLK next goes low at subsequent time t14, PC1 and PC2 are once again pre-charged high and CLKB also goes high at subsequent time t15. Further toggling of D has no effect during the pre-charged state. Since Q and CLK are both low, PO is held high via P4 and P5, so that the inverter I3 keeps Q low while CLK is low.
CLK goes high once again at time t16 while D is low and while PC2 is still high. As CLK rises, N6 is turning on while P5 is turning off. There is a slight contention since while the pull up of P4 and P5 for PO is turning off, the pull down of N6 and N7 for PO starts turning on. In one embodiment, P4 and P5 are configured as weak keeper devices. Meanwhile, CLKB goes low at subsequent time t17 turning N5 on since PC1 remains high. As N5 turns on, PC2 discharges low at subsequent time t18. PC2 eventually turns N7 off removing the pull down of N6 and N7, and PC2 turns P3 on adding further pull up on PO. The devices are sized and configured to maintain PO high after time t17, although a slight “glitch” shown at 608 may appear on PO as previously described. The slight dip of PO shown at 608 has no effect since the inverter I3 does not change state, so that the states of PO, Q and QB remain unmodified.
A fast dynamic register according to embodiments of the present invention are particularly advantageous on integrated circuits such as shown in
A fast dynamic register circuit according the various embodiments as described herein includes first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high which causes the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations. Note, for example, that the NOR configuration of
Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. For example, the circuits described herein may be implemented in any suitable manner including logic devices or circuitry or the like. Any number of the functions described for the logic circuits may be implemented in software or firmware within an integrated device. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5075386 | Vanderbilt | Dec 1991 | A |
5880608 | Mehta et al. | Mar 1999 | A |
5889979 | Miller, Jr. et al. | Mar 1999 | A |
5926038 | Fouts et al. | Jul 1999 | A |
6060910 | Inui | May 2000 | A |
6172532 | Nishio et al. | Jan 2001 | B1 |
6191618 | Gayles et al. | Feb 2001 | B1 |
6265899 | Abdel-Hafeez et al. | Jul 2001 | B1 |
6420904 | Dutta et al. | Jul 2002 | B1 |
6429689 | Allen et al. | Aug 2002 | B1 |
6486706 | Ye et al. | Nov 2002 | B2 |
6496038 | Sprague et al. | Dec 2002 | B1 |
6560737 | Colon-Bonet et al. | May 2003 | B1 |
6628143 | Hsu et al. | Sep 2003 | B2 |
6650145 | Ngo et al. | Nov 2003 | B2 |
6956406 | Seningen et al. | Oct 2005 | B2 |
6960939 | Ngo | Nov 2005 | B2 |
7064584 | Bertram et al. | Jun 2006 | B2 |
7129754 | Ngo et al. | Oct 2006 | B2 |
7157930 | Hirata | Jan 2007 | B2 |
7161992 | Anders et al. | Jan 2007 | B2 |
7187209 | Bertram | Mar 2007 | B2 |
7187210 | Lundberg et al. | Mar 2007 | B2 |
7187211 | Lundberg et al. | Mar 2007 | B2 |
7193445 | Bertram | Mar 2007 | B2 |
7224190 | Haller et al. | May 2007 | B2 |
7317339 | Qureshi et al. | Jan 2008 | B1 |
7321243 | Qureshi et al. | Jan 2008 | B1 |
7332938 | Al-Assadi et al. | Feb 2008 | B2 |
7336105 | Chuang et al. | Feb 2008 | B2 |
7348806 | Lundberg et al. | Mar 2008 | B2 |
7382161 | Lundberg et al. | Jun 2008 | B2 |
7414436 | Klim et al. | Aug 2008 | B1 |
7417465 | Lundberg et al. | Aug 2008 | B2 |
7429880 | Rana et al. | Sep 2008 | B2 |
7492203 | Kim | Feb 2009 | B2 |
7501850 | Correale et al. | Mar 2009 | B1 |
7557616 | Klim et al. | Jul 2009 | B2 |
7663408 | Masleid et al. | Feb 2010 | B2 |
7710155 | Bhatia et al. | May 2010 | B2 |
20020158670 | Alvandpour | Oct 2002 | A1 |
20030042932 | Bales | Mar 2003 | A1 |
20030052714 | Alvandpour | Mar 2003 | A1 |
20030110404 | Seningen et al. | Jun 2003 | A1 |
20040034681 | Bertram | Feb 2004 | A1 |
20040051560 | Belluomini et al. | Mar 2004 | A1 |
20040056685 | Azam et al. | Mar 2004 | A1 |
20040113658 | Lundberg | Jun 2004 | A1 |
20040257115 | Bertram et al. | Dec 2004 | A1 |
20050046446 | Qureshi et al. | Mar 2005 | A1 |
20050110522 | Hoekstra | May 2005 | A1 |
20050127952 | Bertram | Jun 2005 | A1 |
20060033534 | Lundberg et al. | Feb 2006 | A1 |
20060038589 | Lundberg et al. | Feb 2006 | A1 |
20060038590 | Lundberg et al. | Feb 2006 | A1 |
20060158226 | Bertram | Jul 2006 | A1 |
20070290719 | Qureshi et al. | Dec 2007 | A1 |
20070290720 | Qureshi et al. | Dec 2007 | A1 |
20080036501 | Lundberg et al. | Feb 2008 | A1 |
20080036502 | Lundberg et al. | Feb 2008 | A1 |
20090108874 | Klim et al. | Apr 2009 | A1 |
20090108875 | Klim et al. | Apr 2009 | A1 |
Number | Date | Country | |
---|---|---|---|
20110058641 A1 | Mar 2011 | US |