FAST, LOW-POWER RECEIVE SIGNAL STRENGTH INDICATOR (RSSI) CIRCUIT AND METHOD THEREFOR

Abstract

A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.

Description

CROSS REFERENCE TO RELATED APPLICATION

Related subjected matter is found in U.S. patent application Ser. No. ______, filed ______, invented by the inventors hereof and assigned to the assignee hereof.

FIELD OF THE DISCLOSURE

This disclosure relates generally to radio communication, and more specifically to receive signal strength indicator (RSSI) circuits.

BACKGROUND

Receive signal strength indicator (RSSI) circuits measure the power in a radio frequency (RF) communication signal or an intermediate frequency (IF) signal derived from the RF signal. The output of the RSSI circuit can be used to adjust the gains of various amplifiers in the system to compensate for variations in signal strength. The measured receive signal strength is usually represented in logarithmic form because the wide dynamic variation of the received signal can be represented within a limited indication range.

Generally, RSSI circuits are implemented with a series of amplifier stages forming a limiting amplifier, and the RSSI can be measured from rectified outputs of the amplifier stages. A typical rectifier typically uses a PN junction diode driving a load including a current source in parallel with a capacitor. The currents from all the rectifiers are summed and driven into a load to form the RSSI measurement as a voltage. However, this rectifier-based RSSI circuit requires high steady-state current and takes an appreciable amount of time, such as on the order of a few microseconds, to resolve because of the RC time constant of the load.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which:

FIG. 1 illustrates in partial block diagram and partial schematic form a conventional receive signal strength indicator (RSSI) circuit known in the prior art,

FIG. 2 illustrates in partial block diagram and partial schematic form an integrated low noise amplifier (LNA) and receive signal strength indicator (RSSI) circuit according to various embodiments of the present application;

FIG. 3 illustrates in partial block diagram and partial schematic form a gain stage suitable for use as one of the gain stages in the low noise amplifier of FIG. 2;

FIG. 4 illustrates in schematic form an envelope detector circuit that can be used as an envelope detector circuit in the receive signal strength indicator circuit of FIG. 2;

FIG. 5 illustrates a timing diagram showing the settling time of the receive signal strength indicator circuit of FIG. 2;

FIG. 6 illustrates in block diagram for a linear point detection circuit suitable for use as the linear point detection circuit of FIG. 2;

FIG. 7 illustrates in block diagram form a comparator circuit that can be used as any one of the comparator circuits of FIG. 6; and

FIG. 8 illustrates a graph showing the relationship between the two input voltages and the output voltage of the comparator circuit of FIG. 7.

The use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION

FIG. 1 illustrates in partial block diagram and partial schematic form a receive signal strength indicator (RSSI) circuit 100 known in the prior art. RSSI circuit 100 includes generally a limiting amplifier 110, an output amplifier 130, a full wave current rectifier stage 140, and an output load 150.

Limiting amplifier 110 includes an offset subtractor 111, a series of amplifier stages 112-118, and a feedback filter 120. Offset subtractor 111 include first and second signal inputs for receiving positive and negative components of a differential intermediate frequency signal labelled “IFin”, first and second feedback inputs for receiving positive and negative components of a differential feedback signal, and first and second outputs for providing positive and negative components of a difference signal. Amplifier stages 112-118 are differential amplifiers connected serially between the output of offset subtractor 111 and the input of limiting amplifier 110. Amplifier 112 has positive and negative inputs connected to the first and second outputs of offset subtractor 111 for receiving the positive and negative components of the difference signal, and first and second outputs for providing positive and negative components of a differential output signal of amplifier stage 112. Each of amplifiers 113-117 are connected in the same manner. Amplifier 118 has positive and negative inputs connected to the first and second outputs of amplifier 117, and first and second outputs for providing positive and negative components of a differential output signal of amplifier stage 118. Feedback filter 120 includes resistors 121 and 122, and a capacitor 123. Resistor 121 has a first terminal connected to the second output of amplifier stage 118, and a second terminal connected to the second feedback terminal of offset subtractor 111. Resistor 122 has a first terminal connected to the first output of amplifier stage 118, and a second terminal connected to the first feedback terminal of offset subtractor 111. Capacitor 123 has a first terminal connected to the second terminal of resistor 121, and a second terminal connected to the second terminal of resistor 122.

Output amplifier 130 has first and second inputs connected to the first and second outputs of amplifier stage 118, and an output for providing a signal labelled “IF out”.

Full wave current rectifier stage 140 includes current rectifiers 141 through 148. Current rectifier 141 has first and second inputs for receiving the positive and negative components of the differential input signal IFin, and a current output. Each of current rectifiers 142-148 has first and second inputs connected to the first and second outputs of a corresponding one of amplifiers stages 112-118, and a current output connected together and to the output of current rectifier 141.

Output load 150 includes a resistor 151 and a capacitor 152. Resistor 151 has a first terminal connected to the outputs of each of current rectifiers 141-148, and a second terminal connected to ground. Capacitor 152 has a first terminal connected to the outputs of each of current rectifiers 142-148, and a second terminal connected to ground.

RSSI circuit 100 has several problems. First, it uses current sensing from the outputs of a series of current rectifiers, and the summed currents are driven into a load. These operations cause RSSI circuit 100 to consume a significant amount of power and to have a significant circuit size. Second, RSSI circuit 100 uses differential signaling with CMOS technology, subjecting the amplifiers to offsets from component mismatch, in which the offsets accumulate and are amplified through succeeding stages of the limiting amplifier. In order to compensate for the offsets, limiting amplifier 110 adds an offset subtractor, which increases circuit complexity and lengthens settling time. Third, the load itself can be large and may require, for example, an off-chip capacitor to convert the summed currents into a voltage.

FIG. 2 illustrates in partial block diagram and partial schematic form an integrated low noise amplifier (LNA) and receive signal strength indicator (RSSI) circuit 200 according to various embodiments of the present application. Integrated LNA and RSSI circuit 200 includes generally an LNA 210 and an overlapping RSSI circuit 220.

LNA 210 has an input for receiving a single-ended input intermediate frequency input signal labelled “IF_IN”, and an output for providing an amplified intermediate frequency output signal labelled “IF_OUT”. In alternate embodiments, LNA 210 is also suitable for operation as an LNA that receives a relatively low radio frequency (RF) signal, e.g., at a carrier frequency on the order of tens of mega-Hertz (MHz) or less, at an input of a RF receiver. LNA 210 is implemented as a set of serially-connected amplifier stages 211-215, and a single-ended input to single-ended output level shifter 216. Amplifier stage 211 is a single-ended input to single-ended output amplifier stage having an input for receiving IF_IN, and an output. Each of amplifier stages 212-215 is a single-ended input to single-ended output amplifier stage having an input connected to the output of a previous amplifier stage, and a single-ended output. Level shifter 216 has an input connected to the output of amplifier stage 215, and an output for providing signal IF_OUT.

RSSI circuit 220 shares amplifier stages 212-215 with LNA 210 and uses them as a limiting amplifier. RSSI circuit 220 also includes an envelope detector stage 230, a selection circuit 240, and an output stage 250. Envelope detector stage 230 includes envelope detector circuits 232-235 connected to the outputs of amplifier stages 212-215, respectively. Envelope detector 232 has an input connected to the output of amplifier stage 212, and an output for providing a signal labelled “rssi<0>”. Envelope detector 233 has an input connected to the output of amplifier 213, and an output for providing a signal labelled “rssi<1>”. Envelope detector 234 has an input connected to the output of amplifier 214, and an output for providing a signal labelled “rssi<2>”. Envelope detector 235 has an input connected to the output of amplifier 215, and an output for providing a signal labelled “rssi<n>”. As shown in FIG. 2, each envelope detector circuit includes a diode, a current source, and a capacitor. The diode has an anode connected to the output of the respective amplifier, and a cathode that provides the respective rssi component. The current source and capacitor are connected in parallel to each other and each has a first terminal connected to the anode of the corresponding diode, and a second terminal connected to ground.

Selection circuit 240 includes a linear point detection circuit 241 and a multiplexer 242 labelled “MUX”. Linear point detection circuit 241 has an input for receiving the rssi<n:0> voltages from the corresponding envelope detector circuits, and an output for providing a rssi selection signal labelled rssi_sel<n:0>. Multiplexer 242 has signal inputs for receiving the rssi<n:0> voltages from the corresponding envelope detector circuits, a control input connected to the output of linear point detection circuit 241, and an output for providing as a detected RSSI signal a receive signal strength indicator component of one of the envelope detector circuits having a desired linear range. Linear point detection circuit 241 provides one of the rssi_sel<n:0> signals in an active state, while keeping all remaining ones in an inactive state. Thus, linear point detection circuit 241 provides a one-hot output signal.

Output stage 250 includes an amplifier 251 and an analog-to-digital converter (ADC) 255. Amplifier 251 includes an operational amplifier 252 and resistors 253 and 254. Operational amplifier 252 has a non-inverting input connected to the output of multiplexer 242, an inverting input, and an output. Resistor 253 has a first terminal connected to the non-inverting input of operational amplifier 252, and a second terminal connected to ground, and has an associated resistance R₁. Resistor 254 has a first terminal connected to the non-inverting input of operational amplifier 252, and a second terminal connected to the output terminal of operational amplifier 252, and has an associated resistance R₂.

In operation, amplifier stages 212-215 function together as a limiting amplifier for RSSI circuit 220. The overall LNA gain is given by Equation 111:

G(LNA)=G1+G₂₁₂+G₂₁₃±G₂₁₄+ . . . G₂₁₅  [1]

However, as shown in FIG. 2, amplifier stage 211 has a gain labelled “G1”, whereas each of stages 212-215 has a gain labelled “G”.

The RSSI dynamic range is given by Equation [2]:

DR _(RSSI) =G ₂₁₂ +G ₂₁₃ +G ₂₁₄ + . . . G ₂₁₅  [2]

In some embodiments, the DR_(RSSI) may be chosen to align with the sensitivity of LNA 210, while G₁ is independently scaled for noise.

In some embodiments, the gains G of amplifier stages 212-215 are equal to each other, but are different from gain G1. By making the gains G of amplifier stages 212-215 the same, linearity is improved and detection error is reduced.

Since the gains of amplifier stage 211-215 are known, the inventors have discovered that selecting the output of only one of amplifier stages 212-215 having a desired linear range can be used to determine the RSSI of the IF_IN signal. For example, if the output of stage 214 demonstrates the desired linear range, then linear point detection circuit 241 can choose its input to multiplexer 242 as the detected RSSI signal. As will be explained further below, linear point detection circuit 241 detects the first amplifier in the amplifier chain in an order from amplifier stage 212 to amplifier stage 215 whose RSSI component exceeds the prior RSSI component by more than a threshold. In this way, the RSSI signal will be free of saturation at either the low end or the high end of the gain range and will be substantially linear in the middle.

Amplifier 251 applies a final gain equal to 1+(R2/R1) to its output that is connected to the input of ADC 255. The values for R1 and R2 can be determined by simulation or characterization, or can be made programmable and set using calibration during operation to place the analog signal at the ideal point at the input of ADC 255.

ADC 255 converts the analog signal to a digital signal representation of the receive signal strength. This receive signal strength can be adjusted in the digital domain based on the gain stage that produced the output having the desired linear range.

Contrary to conventional RSSI detection methods with voltage-current-voltage based conversion, such as RSSI circuit 100 of FIG. 1, RSSI circuit 220 uses a voltage-only based signal detection with ultra-low power consumption, as well as a novel method to determine the linear range of operation without multi cycle count calculations. The low-power envelope detection based method used by RSSI circuit 220 generates an analog output voltage representative of the RSSI of IF_IN on the order of a few microseconds, while providing a fast-settling output.

Integrated LNA and RSSI circuit 200 provides several advantages over known circuits. First, it has a small device footprint thanks to the simple architecture, thus saving silicon area and reducing cost. In particular, the limiting amplifier formed by amplifier stages 212-215 is shared between LNA 210 and RSSI circuit 220, avoiding the need to duplicate its circuitry.

Second, since there are no large RC loads on the output of the gain stages and the signal strength is measured in the voltage domain, it operates at high speed with very low power consumption. As will be explained further below, in some embodiments it further uses an envelope detector that has high input impedance and small capacitance due to small MOS transistors used as source followers.

Third, since LNA 210 uses single-ended gain stages with integral band-pass filters, it avoids the problem of offset voltage multiplication through a long amplifier chain and avoids the need for an offset cancellation loop and the extra settling time required by such a loop. Each amplifier stage is connected to a subsequent amplifier stage using blocking capacitors that block the DC component and prevent the need for DC offset cancellation.

FIG. 3 illustrates in partial block diagram and partial schematic form an amplifier stage 300 suitable for use as one of the amplifier stages in LNA 210 of FIG. 2. Amplifier stage 300 includes generally a single-ended amplifier 310, a first passive network 320, and a second passive network 330. Single-ended amplifier 310 has an inverting input, and an output for providing an amplified signal, shown here as a low-RF signal labeled “rfo”. First passive network 320 includes a resistor 321 and a capacitor 322 connected in series. Resistor 321 has a first terminal for receiving a low-RF input signal labelled “rfi”, and a second terminal, and has an associated resistance labelled “R₁”. Capacitor 322 has a first terminal connected to the second terminal of resistor 321, and a second terminal connected to the inverting input terminal of single-ended amplifier 310, and has an associated capacitance labelled “C₁”. Second passive network 330 includes a resistor 321 and a capacitor 322 connected in parallel. Resistor 331 has a first terminal connected to the inverting input of single-ended amplifier 310, and a second terminal connected to the output of single-ended amplifier 310, and has an associated resistance labelled “R₂”. Capacitor 322 has a first terminal connected to the inverting input of single-ended amplifier 310, and a second terminal connected to the output of single-ended amplifier 310, and has an associated capacitance labelled “C₂”.

In operation, capacitor 322 blocks any DC level of the rfi signal from being amplified by amplifier stage 300, and the DC level of amplifier stage 300 is set solely by single-ended amplifier 310. By using amplifier stage 300, LNA 210 of FIG. 2 avoids the need for DC offset cancellation that is required in conventional multi-stage differential amplifier designs such as a limiting amplifier, simplifying the circuitry for LNA 210 and allowing faster settling time for receive signal strength measurements compared to limiting amplifier 110 of FIG. 1.

In addition, the components of first passive network 320 and second passive network 330 give amplifier stage 300 a bandpass characteristic, such that the combination of serially-connected amplifier stages in LNA 210 of FIG. 2 has an overall bandpass characteristic that imitates a high-order bandpass filter. Thus, by using amplifier stages 300 for each of stages 211-215, LNA 210 creates a distributed a high-quality bandpass characteristic without providing a separate complex analog filter.

FIG. 4 illustrates in schematic form an envelope detector circuit 400 that can be used as an envelope detector circuit in receive signal strength indicator circuit 220 of FIG. 2. Envelope detector circuit 400 includes a transistor 410, a current source 420, and a capacitor 430. Transistor 410 is an N-channel metal-oxide-semiconductor (MOS) field effect having a drain connected to a power supply voltage terminal labelled “V_DD”, a gate forming an input of the envelope detector circuit and receiving the amplified signal of a corresponding one of the serially-coupled amplifier stages of LNA 210 of FIG. 2, and a source for providing a receive signal strength indicator component labelled “V_RSSI”. Current source 420 has a first terminal connected to the source of transistor 410, and a second terminal connected to ground. Capacitor 430 has a first terminal connected to the source of transistor 410, and a second terminal connected to ground.

Unlike the diode-based envelope detector circuits in envelope detector stage 230 shown in FIG. 2, envelope detector circuit 400 uses an N-channel MOS transistor in a source follower configuration to generate V_RSSI. Since the source of transistor 410 only drives either an inactive switch (if multiplexer 242 does not select its corresponding input) or the high-impedance input of an operational amplifier 252 (if multiplexer 242 selects its corresponding input), it resolves quickly and consumes no DC power, thus contributing to lower overall power consumption. Moreover, transistor 410, current source 420, and capacitor 430 can be made small to further reduce circuit area and improve settling time.

FIG. 5 illustrates a timing diagram 500 showing the settling time of receive signal strength indicator circuit 220 of FIG. 2. In timing diagram 500, the horizontal axis represents time in microseconds (μs), and the vertical axis represents voltage in volts. Shown in timing diagram 500 are three waveforms of interest, including a first waveform 510 representing a 50 μV peak-to-peak input, a second waveform 520 representing a 10 μV peak-to-peak input, and a third waveform 530 representing a 0 μV peak-to-peak input signal. Also shown in timing diagram 500 is a time point at about 10 μs at which time the peak detection measurement has settled for all three inputs. Timing diagram also shows that the input peak signal level versus output voltage shows a logarithmic characteristic, which can be easily corrected in the digital domain to obtain a linear RSSI measurement.

FIG. 6 illustrates in block diagram for a linear point detection circuit 600 suitable for use as linear point detection circuit 241 of FIG. 2. Linear point detection circuit 600 includes a set of comparator circuits 610 and a selection logic circuit 620. Each of comparator circuits 610 compares the two adjacent RSSI components and provides an output based on a difference between the two exceeding a threshold voltage. Thus, a first comparator circuit 610 compares rssi<1> to rssi<0> and provides an output labelled <0> if rssi<1> exceeds rssi<0> by more than the threshold, a second comparator circuit 610 compares rssi<2> to rssi<1> and provides an output labelled <1> if rssi<2> exceeds rssi<1> by more than the threshold, and so on until a last comparator circuit 610 compares rssi<n> to rssi<n−1> and provides an output labelled <n−1> if rssi<n> exceeds rssi<n−1> by more than the threshold. Selection logic circuit 620 looks for the pattern of changes in the measured rssi value that indicates the signal strength is in a desired linear range. In that case, selection logic circuit 620 picks that output as representative of the input signal and activates a corresponding control signal to control an analog switch in multiplexer 242 to pass the selected RSSI component to the output.

FIG. 7 illustrates in block diagram form a comparator circuit 700 that can be used as any one of comparator circuits 610 of FIG. 6. Comparator circuit 700 compares rssi<n> to rssi<n−1> and includes an offset voltage source 710 and a comparator 720. Offset voltage source 710 has a positive terminal for receiving rssi<n>, and a negative terminal, and generates a voltage difference labelled “V_offset” between the positive and negative terminals thereof. Offset voltage source 710 can be implemented by any of a number of circuits or circuit elements such as a diode, a diode-connected MOS transistor, etc. Comparator 720 has a positive input terminal connected to the negative terminal of offset voltage source 710, a negative input terminal for receiving rssi<n−1>, and an output terminal for providing a signal labelled “<n−1>”. Comparator 720 is a near-ideal voltage comparator with low offset voltage and high gain for forming substantially discrete output logic states. Because of the voltage reduction provided by offset voltage source 710, comparator 720 provides the <n−1> signal at a logic high if V_(rssi<n>)−V_offset> V_(rssi<n-1>), and at a logic low otherwise.

The unbalanced structure of comparator circuit 700 reduces the overall RSSI measurement time to an amount of time within one conversion cycle of ADC 255, providing near real-time determination of the linear output of the RSSI chain without requiring a multiple-cycle ADC conversion, and validates the RSSI output with minimum number of cycles during continuous operation. This advantage can be seen especially during short bursts of data frames that occur during alternating receive and transmit operation.

FIG. 8 illustrates a graph 800 showing the relationship between the two input voltages and the output voltage of comparator circuit 720 of FIG. 7. In graph 800, the horizontal axis represents V_(rssi<n>) in volts, and the vertical axis represents V_(rssi<n-1>) in volts. A line 810 illustrates the points at which V_(rssi<n>)=V_(rssi<n-1>). A line 820 illustrates the values of V_(rssi<n>) when V_(rssi<n-1>) equals a particular voltage labelled “k”. A waveform 830 illustrates the value of <n−1> at various values of V_(rssi<n>). Waveform 830 shows that the <n−1> signal has a high logic state when V_(rssi<n>)=V_(rssi<n-1>)+Voffset, and a logic low state otherwise. Thus, the <n−1> signal is active to indicate that there is a difference between successive rssi components of at least a certain magnitude, namely V_offset. In this case, the corresponding envelope detector circuit is in a desired linear range for estimating the overall receive signal strength of the input signal. Linear point detection circuit 241 selects the first RSSI component in an order from the least significant (earlier stage in the amplifier chain with less gain applied) to the most significant (later stage in the amplifier chain with more gain applied) having the desired linear range. The comparison measurements are decided very quickly and the validity of the rssi selection and measurement is limited only by settling time shown in FIG. 5, thus allowing a rapid RSSI measurement.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the claims. For example, the disclosed RSSI circuits can be used to measure the receive signal strength of either an IF signal or a low RF signal, such as an RF signal having a carrier frequency on the order of tens of MHz. The disclosed envelope detector circuit provides very low power and small area envelope detection, but in other embodiments, a conventional diode-base envelop detector can be used. While in some embodiments, a portion of the signal amplifier is used for the limiting amplifier of the RSSI circuit, in other embodiments the RSSI limiting amplifier can be dedicated to the RSSI function. Moreover, in other embodiments the selection circuit can use different techniques to determine whether the RSSI component is in the desired linear range besides the disclosed technique of comparing of pairs of RSSI components.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the forgoing detailed description.

Claims

1. A receive signal strength indicator circuit, comprising: a low-noise amplifier having a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal;an envelope detector stage comprising a plurality of envelope detector circuits, each having an input receiving said amplified signal of a corresponding one of said plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component; anda selection circuit coupled to said outputs of said plurality of envelope detector circuits, for providing said receive signal strength indicator component of one of said plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.

2. The receive signal strength indicator circuit of claim 1, wherein each of said plurality of envelope detector circuits comprises an MOS transistor having a gate for receiving said amplified signal of a corresponding one of said plurality of serially-coupled amplifier stages, and a source for providing said receive signal strength indicator component.

3. The receive signal strength indicator circuit of claim 2, wherein: said MOS transistor further has a drain coupled to a first power supply voltage terminal; andeach of said plurality of envelope detector circuits further comprises: a current source having a first terminal coupled to said source of said MOS transistor, and a second terminal coupled to a second power supply voltage terminal; anda capacitor having a first terminal coupled to said source of said MOS transistor, and a second terminal coupled to said second power supply voltage terminal.

4. The receive signal strength indicator circuit of claim 1, wherein said selection circuit comprises: and a linear point detection circuit (241) having inputs coupled to said output of each of said plurality of envelope detector circuits (232/233/234/235) in said envelope detector stage (230), and an output for providing said detected RSSI signal, wherein said linear point detection circuit (241) selects a first receive signal strength indicator component in an order from a least significant to a most significant having a desired linear range; anda multiplexer responsive to said output of said linear point detection circuit for coupling said receive signal strength indicator component of one of said plurality of envelope detector circuits that has said desired linear range in said order from least significant to more significant to said output of said selection circuit.

5. The receive signal strength indicator circuit of claim 4, wherein said linear point detection circuit comprises: a plurality of comparator circuits, each comparing said receive signal strength indicator component from a first envelope detector to said receive signal strength indicator component of a second envelope detector subsequent to said first envelope detector, and having an output that is active if said receive signal strength indicator component from said second envelope detector is greater than said receive signal strength indicator component from said second envelope detector by more than a predetermined amount; anda selection logic circuit coupled to said outputs of each of said plurality of comparator circuits, and having an output that provides a selection signal corresponding to a least-significant one of said plurality of comparator circuits whose output is active.

6. The receive signal strength indicator circuit of claim 5, wherein each of said plurality of comparator circuits comprises: an offset voltage generator having a positive terminal for receiving said receive signal strength indicator component from said second envelope detector, and a negative terminal; anda comparator having a positive input coupled to said negative terminal of said offset voltage generator, a negative terminal for receiving said receive signal strength indicator component from said second envelope detector, and an output forming said output of a respective one of said plurality of comparator circuits.

7. The receive signal strength indicator circuit of claim 1, wherein said low-noise amplifier further comprises: an initial amplifier stage, wherein gains of each of said plurality of serially-coupled amplifier stages are equal to each other but different than a gain of said initial amplifier stage; anda level shifter having an input coupled to a last one of said plurality of serially-coupled amplifier stages, and an output for providing a level-shifted amplified output signal.

8. The receive signal strength indicator circuit of claim 1, further comprising: an output stage for providing a digital RSSI signal having a value corresponding to said detected RSSI signal.

9. The receive signal strength indicator circuit of claim 8, wherein said output stage comprises a gain stage having an input for receiving said detected RSSI signal, and an output; and an analog-to-digital converter having an input coupled to said output of said gain stage, and an output for providing said digital RSSI signal.

10. A receive signal strength indicator circuit, comprising: a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal;a plurality of envelope detectors each comprising: an MOS transistor having a gate for receiving said amplified signal of a corresponding one of said plurality of serially-coupled amplifier stages, and a source for providing a receive signal strength indicator component;a current source having a first terminal coupled to said source of said MOS transistor, and a second terminal coupled to a second power supply voltage terminal; anda capacitor having a first terminal coupled to said source of said MOS transistor, and a second terminal coupled to said second power supply voltage terminal, anda selection circuit coupled to said source of said MOS transistor of said plurality of envelope detectors, wherein said selection circuit provides said receive signal strength indicator component of one of said plurality of envelope detectors having a desired liner range as a detected RSSI signal.

11. The receive signal strength indicator circuit of claim 10, wherein said selection circuit comprises: a linear point detection circuit having inputs coupled to said source of said MOS transistor of each of said plurality of envelope detectors, and an output for providing said detected RSSI signal, wherein said linear point detection circuit selects a first receive signal strength indicator component in an order from a least significant to a most significant having a desired linear range; anda multiplexer responsive to said output of said linear point detection circuit for coupling said receive signal strength indicator component of one said plurality of envelope detectors that has said desired linear range in said order from least significant to more significant to said output of said selection circuit.

12. The receive signal strength indicator circuit of claim 11, wherein said linear point detection circuit comprises: a plurality of comparator circuits, each comparing said receive signal strength indicator component from a first envelope detector to said receive signal strength indicator component of a second envelope detector subsequent to said first envelope detector, and having an output that is active if said receive signal strength indicator component from said second envelope detector is greater than said receive signal strength indicator component from said second envelope detector by more than a predetermined amount; anda selection logic circuit coupled to said outputs of each of said plurality of comparator circuits, and having an output that provides a selection signal corresponding to a least-significant one of said plurality of comparator circuits whose output is active.

13. The receive signal strength indicator circuit of claim 12, wherein each of said plurality of comparator circuits comprises: an offset voltage generator having a positive terminal for receiving said receive signal strength indicator component from said second envelope detector, and a negative terminal; anda comparator having a positive input coupled to said negative terminal of said offset voltage generator, a negative terminal for receiving said receive signal strength indicator component from said second envelope detector, and an output forming said output of a respective one of said plurality of comparator circuits.

14. The receive signal strength indicator circuit of claim 10, further comprising: an initial amplifier stage,wherein gains of each of said plurality of serially-coupled amplifier stages are equal to each other but different than a gain of said initial amplifier stage.

15. The receive signal strength indicator circuit of claim 10, further comprising: a level shifter having an input coupled to a last one of said plurality of serially-coupled amplifier stages, and an output for providing a level-shifted amplified output signal.

16. The receive signal strength indicator circuit of claim 10, further comprising: an output stage for providing a digital RSSI signal having a value corresponding to said detected RSSI signal.

17. The receive signal strength indicator circuit of claim 16, wherein said output stage comprises a gain stage having an input for receiving said detected RSSI signal, and an output; andan analog-to-digital converter having an input coupled to said output of said gain stage, and an output for providing said digital RSSI signal.

18. A method of measuring a receive signal strength indicator of a received signal, comprising: amplifying said received signal in successive ones of a plurality of amplifier stages;detecting corresponding envelope signals of outputs of said plurality of amplifier stages;determining which one of said corresponding envelope signals of said outputs of said plurality of amplifier stages provides a desired linear range; andproviding an output RSSI signal in response to said determining.

19. The method of claim 18, wherein said detecting said corresponding envelope signals comprises: for each successive one of said plurality of amplifier stages: receiving an output from a corresponding amplifier stage on a gate of a corresponding MOS transistor;conducting a predetermined current between a source of said corresponding MOS transistor and a reference voltage terminal;storing charge in a capacitor coupled between said source of said corresponding MOS transistor and said reference voltage terminal; andproviding a corresponding envelope signal from said source of said corresponding MOS transistor.

20. The method of claim 18, wherein said determining comprises: determining whether differences between pairs of successive envelope signals exceed a threshold; andselecting a corresponding envelope signal with said desired linear range as a first one in an order from least significant to more significant of pairs of successive envelope signals that exceed said threshold.