Patent Application
20050134344
The present invention relates generally to a fast start-up circuit, more particularly, to a fast start-up circuit for a prescaler device for reducing delay at a transition from a reset mode to a normal operation mode.
Prescaler devices may be used in various high speed applications including transceivers and other similar structures. In general, a prescaler may scale an input signal into a desired output signal. Further, a prescaler may divide an input signal into a plurality of desired output signals. Prescaler devices may also include a counter with a division ratio that may be switched from one value to another by a control signal.
A conventional self-biased prescaler output inverter generally misses several output pulses at a transition from a reset mode to a normal operation mode because the prescaler is AC coupled to an input signal through a capacitor with a large RC time constant. Since an output of self biased inverter does not swing rail to rail, some pulses are lost at the transition. Therefore, additional time is needed to reach a normal operating condition due to the large RC time constant.
Thus, the output voltage of the self biased inverter within a conventional prescaler does not swing rail to rail at the beginning of the transition and needs a couple of pulses to start full swing. As a result, a program counter receiving the output of the prescaler as input will likely miss a couple of pulse counts at the transition point, resulting in various inefficiencies. For example, this false delay is a problem for digital tuning applications because the prescaler is frequently reset for digital tuning.
Therefore, there is a need in the art of prescaler systems for a more efficient method and system for reducing delay at a transition from a reset mode to a normal operation mode.
Aspects of the present inventions overcome the problems noted above, and realize additional advantages. A method and system of the present inventions.
In accordance with an exemplary embodiment, a start-up circuit for reducing delay at a transition from a reset mode to a normal operation mode of a prescaler comprises an input for receiving an input voltage; a first switch for biasing the input voltage at a source voltage during a reset mode; a second switch for generating an output voltage at ground during the reset mode; and an output for transmitting the output voltage to a counter; wherein the first switch and the second switch are disabled at a start of the normal operation mode and the input voltage is pulled down from the source voltage to less than approximately ½ of the source voltage during the transition so that the output makes a substantially full swing at a first pulse.
In accordance with other aspects of this exemplary embodiment, the first switch comprises a PFET circuit; the second switch comprises a NFET circuit; the first switch biases the input voltage at {fraction (3/4)} of the source voltage during the reset mode; the first switch biases the input voltage between a range of approximately ½ of the source voltage to the source voltage during the reset mode; the first switch and the second switch are controlled by an inverter structure comprising a third switch and a fourth switch; the third switch comprises a PFET circuit and the fourth switch comprises a NFET circuit; a reset signal controls an input of the second switch and a complementary signal controls an input of the first switch; the input comprises an input to a self-based inverter; and the output makes a substantially full swing from ground at a first pulse.
In accordance with another exemplary embodiment, a method for implementing a start-up circuit for reducing delay at a transition from a reset mode to a normal operation mode of a prescaler comprises the steps of receiving an input voltage; biasing the input voltage at a source voltage by a first switch during a reset mode; generating an output voltage at ground by a second switch during the reset mode; and transmitting the output voltage to a counter; wherein the first switch and the second switch are disabled at a start of the normal operation mode and the input voltage is pulled down from the source voltage to less than approximately {fraction (1/2)} of the source voltage during the transition so that the output makes a substantially full swing at a first pulse.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the inventions and, together with the description, serve to explain the principles of the inventions.
The present inventions can be understood more completely by reading the following Detailed Description of the Invention, in conjunction with the accompanying drawings, in which:
The following description is intended to convey a thorough understanding of the inventions by providing a number of specific embodiments and details involving prescaler applications. It is understood, however, that the inventions are not limited to these specific embodiments and details, which are exemplary only. It is further understood that one possessing ordinary skill in the art, in light of known systems and methods, would appreciate the use of the inventions for their intended purposes and benefits in any number of alternative embodiments, depending upon specific design and other needs.
An embodiment of the present inventions is directed to a fast start-up circuit that provides that an inverter of a prescaler output generates correct pulses without missing any pulses at the transition from a Reset mode to a normal operation mode by biasing the input-side of the inverter and the output-side of the inverter at high and low during the Reset mode, respectively.
First switch 122 and second switch 124 may be controlled by a controller. In this example, the controller may include a third switch 126 and fourth switch 128. Other circuitry and components may be implemented.
At a reset mode, first switch 122 biases an input voltage at node B to VDD or a fraction of VDD (e.g., ¾ VDD, etc.). Also during the reset mode, an output voltage at node C is pulled to ground 104 by second switch 124. In addition, Reset signal and Reset_Bar signal may be VDD and ground during the reset mode, respectively.
Flip-flop outputs are connected to the In + and In− (A of
Two switches (PFET 122 and NFET 124) may be controlled by Reset_bar and Reset signals. The PFET 122 will make the input voltage of the self biased inverter at ¾ of VDD (or other fraction of VDD) and NFET 124 will make the output voltage of the self biased inverter at GND during the reset mode. The input node B of the self biased inverter will be pulled down hard from VDD to GND when normal operation starts. As a result, the output voltage 414 of the self biased inverter makes a full swing from the first pulse when normal operation starts. Therefore, a device, such as a program counter will receiver correct pulses from the output stage of the prescaler.
The fast start-up circuit of an embodiment of the present inventions provides that the prescaler generates an output pulse correctly without a delay at a transition from Reset mode to normal operation mode. Therefore, a program counter (or other device), which uses output pulses of the prescaler as input signals, may start counting without a false delay.
In accordance with various embodiments of the present invention, the inventive features associated with the prescaler as discussed above may be incorporated in various devices and systems. According to one exemplary embodiment, the prescaler with the fast start-up circuit may be incorporated in a transceiver device.
The transceiver of
The transceiver of
While the foregoing description includes many details and specificities, it is to be understood that these have been included for purposes of explanation only, and are not to be interpreted as limitations of the present inventions. Many modifications to the embodiments described above can be made without departing from the spirit and scope of the inventions.
The present inventions are not to be limited in scope by the specific embodiments described herein. Indeed, various modifications of the present inventions, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such modifications are intended to fall within the scope of the following appended claims. Further, although the present inventions have been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present inventions can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breath and spirit of the present inventions as disclosed herein.
