Patent Application
20130033104
Voltage regulators are often used in electronic devices to generate a stable output voltage from a varying power supply. The current load of a device may change dynamically during operation. This change may cause fluctuations in the output voltage, which may adversely affect operation of the device. A voltage regulator adjusts supplied power according to changes in the load in order to maintain a stable voltage.
Many modern integrated circuits (IC) include a power distribution network having multiple power pins to deliver the required current to the high-speed logic circuits. Distributing the power pins around the IC package may help avoid current crowding and/or large voltage drops in the power distribution network. The resulting power distribution network is more homogeneous, guaranteeing logic performance independent of location on the IC die. Regulator architecture is often scalable to accommodate different chips with different numbers of power supply pins.
Integrated circuits often use on-chip power regulators to convert power supplied by external supplies to meet internal requirements and/or to enable them to dynamically adjust on-chip voltage to reduce power consumption. However, on-chip voltage regulators require a certain time period to start-up before a regulated voltage can be generated. In a system that powers on for a brief time and then goes back to sleep, this start up time becomes an important component in the total power consumption of the electrical system. In some applications, the start-up time dictates whether the chip can power down fully, or must remain powered on in order to respond quickly to interrupts or other events.
One or more embodiments may address one or more of the above issues.
In one embodiment, a system for power regulation is provided. The system includes a reference generation circuit configured to generate a reference voltage and at least one reference current, and a plurality of regulator stages configured to generate a respective regulated output voltage at a respective output node. Each regulator stage includes a difference amplifier and a plurality of output transistors. The difference amplifier has a first input coupled to receive the reference voltage and a respective second input coupled to receive a feedback voltage that is proportional to the respective regulated output voltage. The plurality of output transistors, each have an input driven by a signal output from the difference amplifier and are configured to drive at least on regulated output voltage at the output node in response to a signal output from the difference amplifier. The system includes a start-up circuit configured to generate second and third source voltages from a first source voltage while operating in a start-up mode. The system includes a voltage boost circuit, configured to generate a fourth source voltage from the second source voltage. The fourth source voltage is coupled to a respective power supply voltage input of each of the difference amplifiers. While operating in the startup mode, the voltage boost circuit is powered using the second source voltage and the reference generation circuit is powered using the third source voltage.
In another embodiment, an integrated circuit (IC) is provided. The IC includes a power distribution network and a master power regulator circuit coupled to the power distribution network. The master power regulator includes a circuit configured to generate a reference voltage, at least one output stage, and a respective startup circuit. The output stages are each arranged and configured to generate one or more regulated output voltages from the reference voltage. The startup circuit is arranged and configured to, while operating in a startup mode, generate one or more auxiliary source voltages from a first source voltage and provide power to the reference generation circuit and the at least one output stage using the one or more auxiliary source voltages. The IC includes at least one active slave power regulator circuit and at least one passive slave power regulator circuit having respective outputs coupled to the power distribution network.
In yet another embodiment, a method for power regulation is provided. A reference voltage and at least one reference current are generated. At least one regulated output voltage is generated at an output nodes by: generating a feedback voltage that is proportional to the regulated output voltage; generating a control signal according to a difference between the feedback voltage and the regulated output voltage using a difference amplifier; and operating a plurality of output transistors using the control signal. While operating in a start-up mode, second and third source voltages are generated from a first voltage source. The reference generation circuit is powered using the fourth source voltage. A fourth source voltage is generated from the second source voltage and is used to power the difference amplifier.
The above discussion is not intended to describe each embodiment or every implementation. The figures and following description also exemplify various embodiments.
Various example embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:
While the disclosure is amenable to various modifications and alternative forms, examples thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments shown and/or described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.
The disclosed embodiments are believed to be applicable to a variety of different types of processes, devices, and arrangements for use with various regulator circuits. While the embodiments are not necessarily so limited, various aspects of the disclosure may be appreciated through a discussion of examples using this context.
In accordance with one or more example embodiments, a power regulation system includes a master power regulator and a plurality of slave regulator circuits that are controlled by the master power regulator. The master power regulator includes voltage boost circuit that provides a second source voltage to one or more regulator stages, which generate a regulated voltage output using a reference voltage produced at a reference generation circuit. The master power regulator includes a startup circuit that powers the voltage boost circuit and the reference generation circuit during startup of the power regulation system.
In one or more embodiments the startup circuit is implemented using a fast reference generator paired with a shunt regulator. The reference generator implements two reference generation sub-circuits. A first one of the reference generator sub-circuits is configured to quickly generate a reference current. A second one of the reference generation sub-circuits generates a reference current that is more accurate in comparison to the first reference generation sub-circuit. The reference generator circuit is configured to utilize the first reference generation sub-circuit at startup of the regulator and switch to the second reference generator sub-circuit after startup is complete.
In one or more implementations, the plurality of slave regulators includes at least one passive slave regulator. The passive slave regulator includes one or more regulator stages that generate a regulated voltage output using the second source voltage and reference voltage generated by the master regulator.
In accordance with other implementations, the plurality of slave regulators includes at least one active slave regulator that includes a respective startup circuit and voltage boost circuit. The active slave regulator includes one or more regulator stages that generate a regulated voltage output using a third source voltage generated by the voltage boost circuit of the active slave regulator, and a reference voltage generated by the master regulator. The startup circuit of the active slave regulator powers the voltage boost circuit of the active slave generator during startup of the power regulation system.
The master power regulator 200 includes a voltage boost circuit 202 and 204 that is configured to generate a second source voltage (boost) from a first source voltage (Vdd_chip). The second source voltage (boost) is use to power the difference amplifier 222 of each regulator stage to provide low dropout capability. For low supply voltages, the difference amplifier 222 has the capability to drive the gate voltage higher than the first supply voltage, fully turning on the output NMOS transistor.
In this example, the voltage boost circuit is implemented using a charge pump 204 that charges one or more energy storage elements, in response to the output of the oscillator 210, to produce the second source voltage (boost) from a first source voltage (Vdd) at a rate controlled by the oscillator.
The master power regulator 200 includes a start up circuit configured to generate a third and fourth source voltages from Vdd. While operating in the startup mode the third source voltage (vddaux1) is used to power the voltage boost circuit 202 and 204, and the fourth source voltage (vddaux2) is used to power a reference generation and the biasing circuits 208 and 210 which generate the reference voltage and biasing current used by each regulator stage 220 and 221. As described in more detail below, the startup circuit 212 has the capability to start up almost instantaneously and deliver a less accurate but sufficient supply voltage.
The output voltage of the regulator stage 220 is monitored by a voltage detector circuit 240 which is configured to determine when a stable output voltage is achieved. Once a stable out voltage is achieved, the voltage detector circuit 240 triggers the startup circuit 212 to operate turn off to reduce the power consumption. At this time, the voltage boost circuit, the reference generation circuit 208, and the biasing circuit 210 are powered by transistors 206, which provide a regulated replica voltage of the regulated output voltage.
In one of more embodiments, the output transistors 226 of each regulator stage 222 are implemented using thick gate oxide transistors. Due to this design choice, the second source voltage (boost) generated by the charge pump will not exceed the breakdown voltage of any transistor connected to the boost node, even when configured to produce the highest regulated output voltage.
For illustration, each regulator stage shown in
Because feedback of the difference amp 222 is provided using a replica feedback stage 224, an increase in load current on one of the output transistors 226 or 227 will not cause the regulator to increase voltage signal output from the charge pump. The net effect is reduced load regulation but also reduced peak-to-peak noise of the output voltage. This allows several output stages to be driven from the same voltage without transferring noise between output stages. This is useful to isolate noisy and power hungry loads from those that may be particularly sensitive to power supply
The second sub-circuit has an internal circuit that detects when the reference voltage has reached closely within the final value. It contains an additional delay circuitry to ensure that it has settled to its final value. The delay circuit automatically switches the output voltage and output current, via multiplexors 306 and 308, from the lower accuracy, power hungry first sub-circuit to the lower power, second sub-circuit and turns the first sub-circuit off to conserve power.
The fast reference waveform (fast vref) generated by the first sub-circuit 302 starts quicker than the accurate reference waveform (accurate vref) generated by the second sub-circuit 304. The third waveform illustrates the combination of the fast vref and accurate vref waveforms (combined vref), which switches to the accurate vref only after the accurate vref has completely started up. Therefore, high output accuracy takes longer to achieve. Until then, the voltage/current will have a greater error. This is shown in the reference error envelope. A greater error means that the regulator is not working at its peak performance. However, this is not necessary during startup, as the high-speed clock multipliers (PLL, DLL) will take longer than this reference will take to achieve highest performance. The output voltage of the regulator will be very close to the final value though, and the chip can operate almost at maximum speed.
This block contains a reference generation circuit 502 similar to the first sub-circuit 302 shown in
Transistors 511 and 512, and transistors 519, 520, and 521, mirror and amply the reference current (iref). Transistors 520 and 521 are thus current sources whose output current is several times the reference current. These current are designed to be larger than the maximum required load current connected at the outputs (out1) and (out2).
The transistors 513 and 514 and the transistors 517 and 518 are the load and clamp of the shunt regulator. The loads draw a certain amount of current. Since the transistors 520 and 521 can deliver more current from source, the output voltage rises. If the output voltage rises above the reference voltage vref+threshold voltage of the PMOS devices 517 and 518 respectively, 517 and 518 will become conductive and sink the additional current via the current loads 513 and 514.
This circuit is very fast and can be used to assist in the startup, but may be power inefficient. In one or more embodiments, the startup circuit 500 is configured to power down once the regulator outputs start up. While powered down, transistors 515 and 516 disable the parasitic current drain on the internal supplies and cut off current to transistors 520 and 521. In some implementations, the reference generation circuit 5302 included in the start-up circuit 500 may also be disabled.
The voltage detector operates by comparing the output voltage (vdet) with the reference voltage (vref) from the reference generation circuit. Vdet is derived by a tap into the feedback network at a slightly different point than the controlling amplifier 222 of the regulator stage. This causes the comparator 602 of the voltage detector to trip slightly ahead of time, before the output voltage reaches its final value. This earlier trip point helps to avoid oscillations of the reg_ok signal and to account for mismatch between the comparator 602 and the amplifier 222. In order to compensate for this, the voltage detector 600 includes a delay generator 604. This delay generator 604 will delay the comparator trip long enough to ensure that it has settled.
To prevent false trip when the internal references initially start up, the ref_ok_n signal from the startup block 212 is used to gate the output of the comparator using and gate 606. During the initial startup, both comparator inputs are low and the output of the comparator 602 is undetermined. This gating will ensure proper levels before the comparator trip.
In one of more implementations, the information of the voltage detector block may include circuitry to generate a power on reset (POR) signal (porconst) that may be used to signal logic of an integrated circuit powered by the regulator that a regulated voltage is achieved. The voltage detector trip point automatically changes with the programmed output voltage setting. As a result, the trip point of the POR automatically adjusts as well. A second delay generator 608 may also be included to generate a POR pulse signal (porpulse).
The internal voltage of the biasing circuit 710 is supplied from the master power regulator. The reference current and the boost node connection also come from the master power regulator. The passive slave regulator 700 can be thought of an extension of the output stage of the master power regulator 200 that is located at a different area of the IC. Since the passive slave regulator 700 increases the capacitive loading on the control amplifiers, the startup performance of the power supply will slowly deteriorate as a larger number of passive regulators are connected and enabled. However, for many applications, this may not be an issue. Passive slave regulators 700 can be used to create separate power islands and can be shut down individually as needed to meet the requirements of a particular application or to reduce leakage power of one logic circuits of the IC when inactive.
As a larger number of passive slave regulators 800 are added, start-up performance is reduced, which is limited by the loading to the charge pump. However, unlike the regulator of
The active slave regulator is thus very similar to the master power regulator, but it does not need to have a reference generation circuit. The reference generation circuit consumes a significant portion of the regulator die size, due to the accurate reference block. The other significant portion is the output transistor and gate capacitor. Using an active slave regulator helps to keep the startup performance independent of the number of slave regulators in the system. It also helps to reduce electromagnetic interference (EMI) that, since the inherent mismatch between oscillators of different reference generation circuits will result in a broader spectrum for the noise.
The active slave regulator may require more power than the passive slave regulators but allows regulated output voltages to be adjusted independent of the master power regulator. Each of the slaves can be enabled or disabled individually to suit power consumption and regulation requirements of a particular application and may be used to drive individual power domains or operate in parallel connection with the main regulator.
Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made without strictly following the exemplary embodiments and applications illustrated and described herein. Furthermore, various features of the different embodiments may be implemented in various combinations. Such modifications do not depart from the true spirit and scope of the present disclosure, including that set forth in the following claims.
