Patent Application
20110134330
1. Field of Art
The disclosure generally relates to the field of multimedia switching, receiving and repeating.
2. Description of the Related Art
A multimedia interface system transports multimedia signals from a multimedia source to a multimedia sink. Examples of a multimedia source include a computer, a DVD player, a set-top box, a game consoles or another device producing multimedia output. Examples of a multimedia sink include a monitor, a television, an audio/visual (A/V) receiver or other device which receives and presents video and/or audio. When a system includes more than one multimedia source, the system switches between different multimedia sources to modify the multimedia source providing data to the multimedia sink. Between the multimedia source and the multimedia sink, there is a multimedia link including a transmitter, a switch and a receiver. Examples of multimedia links in such a multimedia switching system are DISPLAYPORT, HDMI and DVI.
Often, the multimedia link is protected by a digital content protection scheme, e.g., HDCP. Before sending content-protected data, the transmitting device initiates an authentication process to confirm that the receiver is authorized to receive the data. Once the receiver has been authenticated, the transmitter encrypts the data stream to prevent eavesdropping and sends the encrypted data stream to the receiver. Hence, when switching to a second multimedia source, the second multimedia source initially starts content protection procedures before sending multimedia content to the multimedia sink. However, the authentication confirming that the receiver is authorized to receive data from the second multimedia source is time consuming. Normally, several seconds are required for the second multimedia source to authenticate that the multimedia sink is permitted to receive multimedia data from the second multimedia source. After the authentication process is completed, the second multimedia source begins transmitting content to the multimedia sink; however, the delay caused by authentication is disruptive for many content viewers.
Conventional techniques for reducing the delay caused by authorization of the multimedia sink by a multimedia source require a dedicated receiver and content decryption block for each input port of a multimedia switch. A logic switch selects an input from multiple input ports for communication to the multimedia sink. Hence, input ports are continuously connected to various multimedia sources so that the multimedia sink is authenticated to receive data from the various multimedia sources. This continuous connection and authorization allows switching from a first input port to a second input port without disrupting communication of multimedia content to the multimedia sink for display.
While this conventional method reduces switching delay by removing the need for re-authentication after switching to a new multimedia source, drawbacks remain. In particular, each port completely decodes and decrypts received data, increasing system cost and computing resources.
An alternative configuration reducing the delay in switching between multimedia sources uses two receiver cores. A main receiver core is dedicated for the currently selected port and receives multimedia content from a multimedia source coupled to the selected port. A roving receiver core receives data from different multimedia sources coupled to different background ports which are not selected. The background port providing data to the roving receiver core rotates over time, so that at different time intervals the roving receiver core receives data from different non-selected background ports.
In such an alternate configuration, each input port is an HDMI input port coupled to a high-bandwidth digital content protection (HDCP) engine. The HDCP engine coupled to the selected input port receives HDCP encryption status signaling from the main receiver core. HDCP engines coupled to the background, or non-selected, ports receive HDCP encryption status signaling from the roving receiver core. When the HDCP engine for a background port is connected to the roving receiver core, the HDCP engine for the background port uses HDCP encryption status signaling from the roving receiver core. When the HDCP engine for a background port is not connected to the roving receiver, the HDCP engine operates in an open-loop mode using assumed HDCP encryption status signaling. However, when an HDCP engine operates in an open-loop mode, the HDCP engine may miss HDCP encryption data indicating a status change. Additionally, this configuration is limited to application in an HDMI system with HDCP content protection.
The disclosed embodiments have other advantages and features which will be more readily apparent from the detailed description, the appended claims, and the accompanying figures (or drawings). A brief introduction of the figures is below.
The Figures (FIGS.) and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.
Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.
Various embodiments provide a system and method for reducing the cost of a switch while also reducing the switch time caused by authorizing a content protection link. Additionally, the disclosed system and method also improve the functional reliability of a switch or other receiver device. In an embodiment, a multimedia interface system includes a multimedia switch having two or more inputs and one or more outputs. The inputs may have different interface formats, such as DISPLAYPORT, HDMI, DVI or combinations of input types. The output, or outputs, may have a variety of formats, such as DISPLAYPORT, HDMI, DVI, TMDS. Different outputs may have different formats. Additionally, the multimedia interface system supports content protection, such as HDCP, DPCP (DISPLAYPORT Content Protection) or any other content protection method.
Although described for use in conjunction with multimedia switches, the described method is also applicable to any multiple input format multimedia receiver or display controller having at least one input protected by content protection.
Operationally, the multimedia source 110 outputs data to the transmitter 115. The M-to-1 multimedia switching system 120 selects which input from the transmitters 115 will be output to the receiver 125. Before sending content protected data, the transmitter 115 initiates an authentication process to confirm that the receiver 125 is authorized to receive the data. Once the receiver has been authorized and the data has been sent to the receiver 125, the receiver 125 transmits the data to the multimedia sink 130.
By way of example in describing
In an example embodiment, the M-to-1 switch 200 shown in
The full port receiver 210 fully decodes received multimedia input signals. In an embodiment, the full port receiver 210 includes a physical layer and a link layer. The decoded signal output by the full port receiver 210 includes CP signaling and multimedia data. The CP signaling is further sent to full port content protection cipher block 212. The multimedia data is further sent to a full port content protection decryption block 214.
The full port content protection cipher block 212 includes one or more content protection ciphers. The CP state is held in those content protection ciphers. When a new source port is selected to communicate data to the output port, the CP state in the full port content protection cipher block 212 is loaded with the CP state stored in the partial port content protection cipher block 224 for the newly-selected port. For example, when switching from port 1 to port 2, the CP state stored in the partial port content protection cipher block 224B associated with port 2 is selected and loaded to the full port content protection cipher block 212 at a proper time. The full port content protection cipher block 212 then continues updating the CP state according to the content protection encryption status signaling from the full port receiver 210. Meanwhile, the partial port receiver associated with port 2220B, partial port content protection authentication block associated with port 2222B and partial port content protection cipher block associated with port 2224B remain operational and keep the CP state associated with port 2 synchronized with the multimedia source device coupled to port 2. When switching from port 2 to a different port and back to port 2, the above-described process is repeated to load the full port content protection cipher block 212 and allow the full port content protection cipher block 212 to continue updating the CP state.
The full port content protection decryption block 214 performs decryption according to a current content protection scheme. The full port content protection decryption block 214 receives decryption keys from the full port content protection cipher block 212 and receives encrypted multimedia data from the full port receiver 210. The multimedia data is decrypted using the received decryption keys and decrypted multimedia data is output from the full port content protection decryption block 214 to the output port 250.
The partial port receiver 220 decodes the minimum amount of input data necessary to obtain CP signaling. Data from multiple channels or link from the multimedia input are not decoded if the data is not used to obtain CP signaling. By limiting the amount of data decoded, the partial port receiver 220 provides cost savings while enabling fast switching and high functional reliability.
The partial port content protection authentication block 222 responds to content protection requests from multimedia sources connected to the switching system that employ content protection in an embodiment, multimedia sources perform authentication via a side-band channel 204. After receiving a command from a multimedia source, the partial port content protection authentication block 222 generates a CP control signal which is transmitted to the partial port content protection cipher block 224. The partial port content protection authentication block 222 also receives an authentication value from partial port content protection cipher block 224 and returns the authentication value to a requesting multimedia source.
The partial port content protection cipher block 224 includes one or more content protection ciphers. The CP state is determined by a content protection ciphers. CP state data is synchronized with a corresponding multimedia source. When a partial port is not selected for communicating data to the multimedia sink, the partial port content protection cipher block 224 uses information from partial port receiver 220 to trigger a CP state change. When a partial port is selected for communicating data to the multimedia sink, the partial port content protection cipher block 224 transfers the CP state to the full port content protection cipher block 212. Meanwhile, the partial port content protection cipher block 224 and full port content protection cipher block 212 receive CP signaling from the full port receiver 210 and update the CP state accordingly.
The CP state in partial port content protection cipher block 224 is synchronized with the multimedia source coupled to the partial port content protection cipher block 224. When the port associated with a partial port content protection cipher block 224 is not selected, the partial port content protection cipher block 224 monitors CP signaling from partial port receiver 220. When the port associated with the partial port content protection cipher block 224 is selected, the partial port content protection cipher block 224 monitors CP signaling from the full port receiver 210.
The process starts and determines 404 if a current port is connected and stable. If not, the process reverts to waiting until that state is reached. After determining 404 that the current port is connected and stable, the process determines whether there is an upstream issue CP request. If not, the process waits. If so, the process receives 406 a content protection request from the multimedia source coupled to the current port, the partial port content protection authentication block 222 responds 408 to the received content protection request and the partial port content protection cipher block 224 performs 409 an authentication value calculation to authenticate the current port.
After authenticating 410 the current port, the switching system determines 412 whether the current port is selected as the output port 250. If the current port is selected as the output port 250, a multiplexer to select CP signaling is configured 420 to identify CP signaling from the full port receiver 210. A multiplexer for selecting content protection state is then configured 422 to select a CP state from the partial port content protection cipher block 224 associated with the current port. An additional multiplexer for loading a CP state is configured 424 to select the CP state from the partial port content protection cipher block 224 and communicate the included CP state to the full port content protection cipher block 212. The partial port content protection cipher block 224 and the full port content protection cipher block 212 then update 426 the CP state associated with the current port based on CP signaling received from the full port receiver 210. Step 426 repeats while the current port is selected as the output port 250.
If the current port is not selected 428 as the output port, the multiplexer to select CP signaling is configured 430 to select CP signaling from the partial port receiver associated with the current port. The multiplexer for selecting CP state is configured 432 to select CP state from a partial port content protection cipher block associated with the port selected as the output port and the multiplexer for loading CP state is configured 434 to communicate the CP state from the partial port content protection cipher block associated with the port selected as the output port to the full port content protection cipher block. The partial port content protection cipher associated with the current port subsequently updates 436 the CP state based on CP signaling received from the partial port receiver associated with the current port. A determination 438 is then made whether the current port is selected as the output port, and the appropriate steps are performed, as described above, based on the results of the determination.
The system includes input ports 502, each of which has a related AUX channel input 504 which transmits a subset of the lanes included in the input port 502. Each of the 1-M input ports 502 are communicatively coupled to an M-to-1 switch 200 which outputs data to the full port receiver 510. The full port receiver 510 is communicatively coupled to a full port CP decryption block 514 and a full port CP cipher block 512. The full port decryption block 514 is communicatively coupled to an output port 550. The input ports 502 are communicatively coupled to partial port receivers 520 and the auxiliary input ports 504 are communicatively coupled to the partial port CP authentication blocks 522. The partial port CP cipher blocks 524 are communicatively coupled to the partial port authentication blocks 522, partial port receivers 520 and full port receiver 510.
As shown in
The port content protection decryption block 514 decrypts data received from the full port receiver 510 and outputs the decrypted data for transmission to the multimedia sink via the output port 550. When switching to a new port, the CP state of the full port content protection cipher block 512 is loaded with the value stored in the partial port content protection cipher block 524 associated with the new port and continues to update the CP state using CP signaling from the full port receiver block 510.
When receiving DISPLAYPORT input, as shown in
The partial port content protection authentication block 522 and the partial port content protection cipher block 524 are configured to response to a CP authentication request from the multimedia source as needed. This allows the partial port content protection authentication block 522 and the partial port content protection cipher block 524 to respond to a CP authentication request when it is received. After an input port associated with a partial port receiver 520 is authenticated, the input port maintains a CP state synchronized with the multimedia source. The partial port content protection cipher block 524 monitors CP signaling from partial port DISPLAYPORT receiver 520, or full port DISPLAYPORT receiver 510, and updates the CP state accordingly. In an embodiment, a link integrity check is also performed using lane 0. If there is a link integrity failure, the partial port content protection cipher block 524 asserts an interrupt to notify the multimedia source.
In one embodiment, DDC channel input ports 604 are included to accompany the HDMI input ports 602. The HDMI input ports 602 are communicatively coupled with the M-to-1 switch 200 which outputs data to a full port HDMI receiver 610. The full port HDMI receiver 610 is communicatively coupled to a full port HDCP decryption block 614 and full port HDCP cipher block 612. The full port decryption block 614 receives data from the full port cipher block 612 and transmits data to the output port 650. Each of the HDMI input ports 602 are communicatively coupled to a partial port HDMI receiver 620 and a partial port HDCP cipher block 624 is communicatively coupled to a partial port authentication block 622, a partial port HDMI receiver 620 and the full port HDMI receiver 610. The partial port HDCP authentication blocks are also communicatively coupled to DDC channel input ports 604.
In the example shown by
The partial port HDMI receiver 620 decodes data from a subset of the channels, such as from channel 2. In HDMI, HDCP encryption status signaling is indicated by CTL3. When encryption is enabled, a multimedia source asserts a CTL3 signal in a specified window during VSYNC. When encryption is disabled, the multimedia source does not assert CTL3. When CTL3 is asserted by the multimedia source, a frame key is re-calculated. Hence, by decoding data on a subset of channels, such as channel 2, HDCP status is obtained.
A partial port HDCP authentication block 622 and a partial port HDCP cipher block 624 associated with an input port is configured to respond to an HDCP authentication request from a multimedia source as the authentication request is received. After the input port is authenticated, the CP state of the input port is synchronized with the corresponding multimedia source. The partial port HDCP cipher block 624 monitors the HDCP encryption status signaling from partial port HDMI receiver 620, or full port HDMI receiver 610, and updates the CP state as needed. The partial port HDCP cipher block 624 also generates a HDCP authentication value, Ri, and sends the authentication value to a corresponding partial port HDCP authentication block 622, which communicates the HDCP authentication value to the multimedia source device upon request. The HDCP authentication value, Ri, is used by multimedia source to perform link integrity verification.
The switching system shown by
The input ports 702 in
The switching system and method described above enable fast switching in a multimedia interface system with content protection. By using a partial port receiver for different input ports 702, the design of the switching system is simplified and silicon costs are reduced. Additionally, the switching system and method reduces switching delay by maintaining authentication of different input ports, eliminating re-authentication of a multimedia source when the input port providing input to the multimedia sink is switched.
In one embodiment, all of the connected input ports are partially decoded without any being output. This would be useful for operation in a low power state when no multimedia sink is connected and ready to receive output. Even with no output, CP signaling with each of the inputs is maintained in order to minimize the delay in output when a multimedia sink is connected.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Certain embodiments are described herein as including logic or a number of components, modules, or mechanisms. Modules may constitute either software modules (e.g., code embodied on a machine-readable medium or in a transmission signal) or hardware modules. A hardware module is tangible unit capable of performing certain operations and may be configured or arranged in a certain manner. In example embodiments, one or more computer systems (e.g., a standalone, client or server computer system) or one or more hardware modules of a computer system (e.g., a processor or a group of processors) may be configured by software (e.g., an application or application portion) as a hardware module that operates to perform certain operations as described herein.
In various embodiments, a hardware module may be implemented mechanically or electronically. For example, a hardware module may comprise dedicated circuitry or logic that is permanently configured (e.g., as a special-purpose processor, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)) to perform certain operations. A hardware module may also comprise programmable logic or circuitry (e.g., within a general-purpose processor or other programmable processor) that is temporarily configured by software to perform certain operations. It will be appreciated that the decision to implement a hardware module mechanically, in dedicated and permanently configured circuitry, or in temporarily configured circuitry (e.g., configured by software) may be driven by cost and time considerations.
The various operations of example methods described herein may be performed, at least partially, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors may constitute processor-implemented modules that operate to perform one or more operations or functions. The modules referred to herein may, in some example embodiments, comprise processor-implemented modules.
The performance of certain of the operations may be distributed among the one or more processors, not only residing within a single machine, but deployed across a number of machines. In some example embodiments, the one or more processors or processor-implemented modules may be located in a single geographic location (e.g., a home environment, an office environment, or a server farm). In other example embodiments, the one or more processors or processor-implemented modules may be distributed across a number of geographic locations.
Some portions of this specification are presented in terms of algorithms or symbolic representations of operations on data stored as bits or binary digital signals within a machine memory (e.g., a computer memory). These algorithms or symbolic representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others skilled in the art. As used herein, an “algorithm” is a self-consistent sequence of operations or similar processing leading to a desired result. In this context, algorithms and operations involve physical manipulation of physical quantities. Typically, but not necessarily, such quantities may take the form of electrical, magnetic, or optical signals capable of being stored, accessed, transferred, combined, compared, or otherwise manipulated by a machine. It is convenient at times, principally for reasons of common usage, to refer to such signals using words such as “data,” “content,” “bits,” “values,” “elements,” “symbols,” “characters,” “terms,” “numbers,” “numerals,” or the like. These words, however, are merely convenient labels and are to be associated with appropriate physical quantities.
Unless specifically stated otherwise, discussions herein using words such as “processing,” “computing,” “calculating,” “determining,” “presenting,” “displaying,” or the like may refer to actions or processes of a machine (e.g., a computer) that manipulates or transforms data represented as physical (e.g., electronic, magnetic, or optical) quantities within one or more memories (e.g., volatile memory, non-volatile memory, or a combination thereof), registers, or other machine components that receive, store, transmit, or display information.
As used herein any reference to “one embodiment” or “an embodiment” means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase “in one embodiment” in various places in the specification is not necessarily all referring to the same embodiment.
Some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. For example, some embodiments may be described using the term “coupled” to indicate that two or more elements are in direct physical or electrical contact. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments are not limited in this context.
As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
In addition, use of the “a” or “an” are employed to describe elements and components of the embodiments herein. This is done merely for convenience and to give a general sense of the invention. This description should be read to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise.
Upon reading this disclosure, those of skill in the art will appreciate still additional alternative structural and functional designs for a system and a process for enabling fast switching in a multimedia interface system with content protection through the disclosed principles herein. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims.
This application claims the benefit of, and priority to, U.S. Provisional Application No. 61/266,998, filed Dec. 4, 2009, which is incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61266998 | Dec 2009 | US |
