Patent Application
20240361793
The present disclosure relates generally to power circuits, and more particularly but not exclusively to linear regulator circuits.
Linear regulator circuits such as low dropout (LDO) regulator circuits have been used in many applications. Typically, an LDO regulator circuit includes a pass element to connect between the input source and the output node. An error amplifier compares a reference voltage and the feedback signal and control the pass element to regulate the output voltage. Here, the LDO regulator circuit acts as a variable resistor to maintain output voltage level. The balance among parameters such as quiescent current, transient response, and the total occupied area are important for the LDO circuit design.
According to an embodiment of the present disclosure, a linear regulator circuit is provided. The linear regulator includes a pass element, an error amplifier, and a miller compensation circuit. The pass element has a first terminal, a second terminal and a control terminal. The first terminal of the pass element is configured to receive an input voltage, and the second terminal of the pass element is configured to provide an output voltage. The error amplifier is configured to provide an error signal to the control terminal of the pass element in response to a reference voltage and a feedback voltage representing the output voltage. The error amplifier includes a current mirror stage and a first stage. The current mirror stage is configured to receive the input voltage. The first stage is coupled to the current mirror stage. The first stage is configured to provide a first current signal to a first terminal of the current mirror stage in response to the reference voltage, and provide a second current signal to a second terminal of the current mirror stage in response to the feedback voltage. The miller compensation circuit is coupled between the second terminal of the pass element and the error amplifier. The miller compensation circuit is configured to control the first current signal.
According to another embodiment of the present disclosure, a linear regulator circuit is provided. The linear regulator includes a pass element, an error amplifier, and a buffer. The pass element has a first terminal, a second terminal and a control terminal. The first terminal of the pass element is configured to receive an input voltage, and the second terminal of the pass element is configured to provide an output voltage. The error amplifier is configured to provide an error signal in response to a reference voltage and a feedback voltage representing the output voltage. The buffer is configured to provide a control signal to the control terminal of the pass element in response to the error signal. The buffer includes a first transistor, a second transistor and a current source. The first transistor has a first terminal, a second terminal and a control terminal. The control terminal of the first transistor is configured to receive the error signal, and the first terminal of the first transistor is coupled to the control terminal of the pass element. The second transistor has a first terminal, a second terminal and a control terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is coupled to the control terminal of the pass element. The current source is coupled in series with the first transistor, and is configured to provide a current signal to the first transistor.
According to yet another embodiment of the present disclosure, a linear regulator circuit is provided. The linear regulator includes a pass element, an error amplifier, a buffer, a feed-forward loading stage, and a miller compensation circuit. The pass element has a first terminal, a second terminal and a control terminal. The first terminal of the pass element is configured to receive an input voltage, and the second terminal of the pass element is configured to provide an output voltage. The error amplifier includes a differential pair configured to provide a first current signal at a first output terminal in response to a reference voltage and provide a second current signal at a second output terminal in response to a feedback voltage representing the output voltage. The error amplifier is configured to provide an error signal in response to the reference voltage and the feedback voltage. The buffer is configured to provide a control signal to the control terminal of the pass element in response to the error signal. The feed-forward loading stage is coupled between the error amplifier and the second terminal of the pass element. The feed-forward loading stage is configured to adjust a loading current of the pass element. The miller compensation circuit is coupled between the second terminal of the pass element and the error amplifier. The pass element is controlled in response to the control signal via a first feedback path. The first feedback path starts from the second current signal flowing through the second output terminal of the differential pair, through a second current mirror coupled to the second output terminal of the differential pair, and through the buffer to the control terminal of the pass element.
The present disclosure can be further understood with reference to the following detailed description and appended drawings, where like elements are provided with like reference numerals. These drawings are only for illustration purpose, thus may only show part of the devices and are not necessarily drawn to scale.
Various embodiments of the present disclosure will now be described. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the present disclosure can be practiced without one or more specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, processes or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.
Throughout the specification and claims, the phrases “in one embodiment”, “in some embodiments”, “in one implementation”, and “in some implementations” as used includes both combinations and sub-combinations of various features described herein as well as variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although it may. Those skilled in the art should understand that the meanings of the terms identified above do not necessarily limit the terms, but merely provide illustrative examples for the terms. It is noted that when an element is “connected to” or “coupled to” the other element, it means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element via another element. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
In one embodiment, the LDO circuit 100 further includes a buffer 120. The buffer 120 is coupled to the error amplifier 110. The buffer 120 is configured to receive the error signal SERR, and provide a control signal Sc to the control terminal (e.g., gate) of the pass element P1 in response to the error signal SERR.
In another embodiment, the LDO circuit 100 further includes a feed-forward loading stage 130. The feed-forward loading stage 130 is coupled between the output node Vout and the error amplifier 110. The feed-forward loading stage 130 is configured to adjust a loading current of the pass element P1 to enhance the transient response. When the transient event happens, the feed-forward stage 130 increases or decreases the loading current based on the information from the error amplifier 110 to stabilize the output voltage at the output node Vout.
In some embodiments, the LDO circuit 100 further includes a miller compensation circuit 140. The miller compensation circuit 140 is configured to provide miller compensation between the error amplifier 110 and the output node Vout. In one embodiment, the miller compensation circuit 140 is coupled to the reference voltage VREF side of the error amplifier 110.
For instance, the first stage 212 includes transistors M1-M10 and a current source I1 as shown in
The current mirror stage 214 is implemented by two transistors M11 and M12. The transistors M7 and M8 are coupled in series with the transistor M11, and the transistors M9 and M10 are coupled in series with the transistor M12. In one embodiment, the pass element MPASS is a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (i.e., PMOS). In one implementation, the current mirror stage 214 is realized by the PMOS (i.e., M11 and M12) and is configured to receive the input voltage VIN.
In one embodiment, the buffer 220 includes a first amplifier. The first amplifier serves as a source follower configured to buffer an input voltage and provide a lower impedance voltage. The first amplifier includes a transistor MSF. The transistor MSF is configured to receive the error signal (e.g., the voltage signal at the second terminal N2 of the current mirror stage 214), and provide a control signal Sc to the control terminal of the pass element MPASS. The second terminal N2 of the current mirror stage 214 is the push-pull output coupled to the control terminal (e.g., gate) of the transistor MSF to control the buffer 220. In one embodiment, a bipolar junction transistor (BJT) Q1 provides a feedback loop to further reduce the output impedance. Specifically, the control terminal (e.g., base) of the BJT Q1 is coupled to the second terminal (e.g., drain) of the transistor MSF, and the second terminal (e.g., collector) of the BJT Q1 is coupled to the control terminal (e.g., gate) of the pass element MPASS. In response to the current signal IB (i.e., the base current of the BJT Q1), the output impedance can be further reduced by (1+β) times. It should be noted that, in some embodiments, the bipolar junction transistor (BJT) Q1 may be replaced by a MOSFET.
In one implementation, the first amplifier of the buffer 220 further includes a current source, coupled in series with the transistor MSF. The current source is configured to provide a current signal to the transistor MSF. In one embodiment, the current source is realized by the transistor M13. The transistors M13 and MSF are coupled in series, and the transistors M11 and M13 form a PMOS mirror to set the minimum operating current IBF1 for the buffer 220. The control terminal (e.g., gate) of the transistor MSF is coupled to the second terminal (e.g., drain) of the transistor M12, and the second terminal (e.g., drain) of the transistor MSF is coupled to the control terminal (e.g., base) of the BJT Q1. With proper biasing scheme, the biasing current set by the PMOS mirror guarantees the BJT Q1 performance and avoids the BJT Q1 working at low-beta region. Moreover, the transistor M13 further improves the transient performance. Specifically, when a transient event occurs, for example, from heavy load to light load, the output voltage increases. Therefore, the current flowing through the transistor M4 (i.e., the second current signal ID2) decreases as the feedback voltage VFB increases, and thus the gate voltage of the transistor MSF also increases. Meanwhile, the current flowing through the transistor M1 (i.e., the first current signal ID1) increases, and therefore the biasing current of the transistor M13 also increases. As a result, the gate voltage of the pass element MPASS also increases to make the output voltage at the output node VOUT return to the target value.
In one implementation, the buffer 220 further includes a sensing transistor MSEN. The sensing transistor MSEN is coupled in series with the BJT Q1. The control terminal (e.g., gate) of the transistor MSEN is coupled to the first terminal (e.g., source) of the transistor MSF, the second terminal (e.g., drain) of the transistor MSEN, and the control terminal (e.g., gate) of the pass element MPASS. The sensing transistor MSEN is configured to monitor the operating condition (e.g., a loading current) of the pass element MPASS. The biasing current IBF2 of the buffer 220 may be automatically adjusted with the transistor MSEN.
In one embodiment, the buffer 220 further includes a resistor R2 coupled in series with the transistor MSEN to limit the biasing current IBF2 at light load. In another embodiment, the buffer 220 further includes a resistor R3 coupled in series with the transistor MSF to pull down the voltage level of the base of the BJT Q1 for shutdown (standby) mode. That is, the BJT Q1 is turned off. On the other hand, under light load condition, the BJT Q1 is controlled to minimize the operating current, according to the operating current IBF1, to achieve low quiescent current.
The feed-forward loading stage 230 includes a transistor (e.g., transistors M14 and M15). The transistors M14 and M15 are coupled in series with the pass element MPASS. The control terminal (e.g., gate) of the transistor M14 is coupled to the control terminal (e.g., gate) of the transistor M2, and the control terminal (e.g., gate) of the transistor M15 is coupled to the control terminal (e.g., gate) of the transistor M3, and the second terminal (e.g., drain) of the transistor M2. The transistors M2, M3, M14, and M15 form a current mirror to copy the current flowing through the transistor M1 (i.e., the first current signal ID1) and provide the loading current of the pass element MPASS. That is, the feed-forward loading stage 230 is configured to adjust the loading current of the pass element MPASS in response to information from the error amplifier 210. Specifically, when a transient event occurs, for example, from light load to heavy load, the output voltage drops. Therefore, the current flowing through the transistor M4 (i.e., the second current signal ID2) increases as the feedback voltage VFB decreases, and thus the current flowing through the transistor M1 (i.e., the first current signal ID1) decreases. As a result, the current flowing through the transistors M14 and M15 also decreases such that the output voltage at the output node VOUT can return to the target value easier and faster. Furthermore, the feed-forward loading stage 230 is further configured to avoid the pass element MPASS to enter the fully off state during light load condition. This further minimizes the voltage dip when transient event happens, such as the high-frequency, periodic, and/or burst-type current profiles.
As shown in
Specifically, when the output voltage at the output node VOUT drops as the load current increases, the current flowing through the transistor M4 increases (e.g., the second current signal ID2+ΔI), and thus the current flowing through the transistor M1 decreases (e.g., the first current signal ID1−ΔI). Accordingly, the second current signal ID2 provided to the second terminal N2 of the current mirror stage 314 also increases (e.g., ID2+ΔI) and the first current signal ID1 provided to a first terminal N1 of the current mirror stage 314 decreases (e.g., ID1−ΔI). As a result, the current ΔI flows through the resistors R4 and R5. For a conventional current mirror, the current flowing through the transistor is controlled by the gate voltage, and therefore the transient response is slow due to charging and discharging the gate capacitance (e.g., the gate to source capacitance CGS). With the two resistors R4 and R5, the current ΔI flows through the resistors R4 and R5 without charging the gate capacitor, and the error signal generated by the error amplifier may be passed to the buffer quickly. Therefore, faster transient performance could be achieved.
Meanwhile, when the output voltage at the output node VOUT drops, the other terminal of the miller compensation circuit (e.g., a capacitor C1) that is connected to the control terminal of the transistors M3, M8, and M15 also drops. In other words, the feed-forward loading stage (e.g., transistors M14 and M15) now draws less loading current from the output node VOUT. Since the second current signal ID2 provided to the second terminal N2 of the current mirror stage 314 increases (e.g., ID2+ΔI), the voltage level at the second terminal N2 of the current mirror stage 314 decreases, and therefore the transistor MSF draws more current and the pass element MPASS also draws more current. The voltage level of the control terminal (e.g., gate) of the pass element MPASS will decrease. As a result, the pass element MPASS provides more current to the output node VOUT. With the two mechanism described above, fast transient response can be achieved.
In one embodiment, the resistor R3 of the buffer 220 as shown in
In another embodiment, the buffer circuit 420 further includes a resistor R1 configured to pull up the gate of the transistor MSEN for shutdown (standby) mode. That is, the transistor MSEN is turned off to achieve low quiescent current.
In another embodiment, the LDO circuit 500 further includes high voltage switches HV1, HV2, HV3, HV4 and HV5 to withstand high voltage.
It should be understood that, the control circuit and the related components, circuit structures, signals, and waveforms described or shown above in the present disclosure are only for illustration purpose. However, the present disclosure is not limited thereto. Persons having ordinary skill in the art may understood that the control circuit of the present disclosure could be realized, according to practical applications, by any other circuits with different circuit structures, and thus controlled by different types of the corresponding signals to achieve the corresponding functions. For example, the compensation circuit, the ramp generation circuit, the comparison circuit and the logic circuit could be realized by a digital circuit, an analog circuit, a software, an automatic generation circuit by hardware description language, or a combination of the above.
It will be appreciated by persons skilled in the art that the present disclosure is not limited to what has been particularly shown and described herein above. Rather the scope of the present disclosure is defined by the claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.
The present application claims the benefit of and priority to a U.S. Provisional Patent Application Ser. 63/462,677 filed Apr. 28, 2023, which is hereby incorporated fully by reference into the present application.
| Number | Date | Country | |
|---|---|---|---|
| 63462677 | Apr 2023 | US |
