Claims
- 1. A circuit for protecting a power supply from fault conditions, comprising:a switching device coupled to receive a switching signal and operable to control power delivered to an output of the power supply; a feedback input for receiving a feedback signal representative of the output of the power supply, the feedback signal cycling periodically between a first state and a second state when the power supply operates normally and not cycling between the first and second states when the power supply is in a fault condition, the switching signal cycling separately from the cycling of the feedback signal; and a timer coupled to the feedback input, the timer operable to reduce power delivery to the output after detection of the fault condition.
- 2. The circuit of claim 1 wherein the timer disables the switching device after a first period of existence of the fault condition and wherein the timer enables the switching device after a second period.
- 3. The circuit of claim 2 wherein the switching device is alternately enabled for the first period and disabled for the second period when the fault condition exists.
- 4. The circuit of claim 3 wherein the switching device is enabled upon removal of the fault condition.
- 5. The circuit of claim 1 wherein the switching device is a power transistor.
- 6. The circuit of claim 1 wherein the timer comprises a digital counter.
- 7. The circuit of claim 6 further comprising an oscillator coupled to the counter, the oscillator having a predetermined frequency.
- 8. The circuit of claim 7, wherein the oscillator has a control input for changing the predetermined frequency, further comprising a first current source coupled to the oscillator control input to generate a first frequency.
- 9. The circuit of claim 8 further comprising a second current source coupled to the oscillator control input to generate a second frequency.
- 10. The circuit of claim 9 wherein the counter has an output coupled to the first and second current sources.
- 11. The circuit of claim 1 wherein the fault condition includes one or more of an output overload fault condition, an output short circuit fault condition and an open feedback control loop fault condition.
- 12. The circuit of claim 4 further comprising a capacitor that is charged at a first rate from a first threshold to a second threshold to generate the first period, the capacitor further being discharged from the second threshold to the first threshold at a second rate to generate the second period.
- 13. The circuit of claim 12 wherein the capacitor is discharged to a voltage below the first threshold each time the feedback signal changes state.
- 14. The circuit of claim 12 wherein the capacitor is discharged to a voltage below the first threshold each time the feedback signal enters the first state.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a continuation of U.S. Application Ser. No. 09/941,905, filed Aug. 29, 2001, now issued as U.S. Pat. No. 6,456,475 B1 on Sep. 24, 2002, which is a continuation of U.S. Application Ser. No. 09/192,871, filed Nov. 16, 1998 and issued as U.S. Pat. No. 6,337,788 B1 on Jan. 8, 2002.
US Referenced Citations (7)
Non-Patent Literature Citations (1)
Entry |
Ashok Bindra, “Power-Conversion Chip Cuts Energy Wastage in Off-Line Switchers,” Electronic Design, pp. 46,48, Oct. 1998. |
Continuations (2)
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Number |
Date |
Country |
Parent |
09/941905 |
Aug 2001 |
US |
Child |
10/183927 |
|
US |
Parent |
09/192871 |
Nov 1998 |
US |
Child |
09/941905 |
|
US |