Claims
- 1. A multi-processor computer system, comprising:
a plurality of processors coupled together to permit messages to be transmit from one processor to another processor; at least one of said processor coupled to at least one input/output device; and each processor having at least one timer that expires when a message is not sent from the processor in a predetermined amount of time.
- 2. The multi-processor computer system of claim 1 further wherein each processor can send a plurality of different message types to other of said processors and each includes a separate timer associated with each of said message types to expire when a message of the associated message type is not sent from the processor in a predetermined amount of time.
- 3. The multi-processor computer system of claim 2 wherein said message types include forward, request, response and input/output message types.
- 4. The multi-processor computer system of claim 1 wherein each processor includes a directory in-flight table that tracks pending messages and a timer associated with said directory in-flight table to monitor for traffic congestion.
- 5. The multi-processor computer system of claim 1 further including at least one register associated with each timer to permit the timer to be programmed.
- 6. The multi-processor computer system of claim 1 wherein each processor has at least one port connection to another processor and wherein each processor further includes a port timer associated with said inter-processor port connection.
- 7. The multi-processor computer system of claim 6 wherein each port timer increments if the associated port is being used to send messages.
- 8. The multi-processor computer system of claim 7 wherein each port timer is reset when a message is sent from the port.
- 9. The multi-processor computer system of claim 7 wherein each port timer is reset when it receives a signal from a processor that receives a message from the port that indicates that the receiving processor has freed up an entry in an input buffer.
- 10. A processor that can be coupled to other processors to form a multi-processor system and can exchange messages with other processors in the system, the processor comprising:
router logic that can be coupled to at least one other processor; said router logic having at least one timer that expires when a message is not sent from the processor in a predetermined amount of time.
- 11. The processor of claim 10 further wherein each processor can send a plurality of different message types to other of said processors and each includes a separate timer associated with each of said message types to expire when a message of the associated message type is not sent from the processor in a predetermined amount of time.
- 12. The processor of claim 11 wherein said message types include forward, request, response and input/output message types.
- 13. The processor of claim 10 wherein each processor includes a directory in-flight table that tracks pending messages and a timer associated with said directory in-flight table to monitor for traffic congestion.
- 14. The processor of claim 10 further including at least one register associated with each timer to permit the timer to be programmed.
- 15. The processor of claim 10 wherein each processor has at least one port connection to another processor and wherein each processor further includes a port timer associated with said inter-processor port connection.
- 16. The processor of claim 15 wherein each port timer increments if the associated port is being used to send messages.
- 17. The processor of claim 16 wherein each port timer is reset when a message is sent from the port.
- 18. The processor of claim 16 wherein each port timer is reset when it receives a signal from a processor that receives a message from the port that indicates that the receiving processor has freed up an entry in an input buffer.
- 19. A method of monitoring a computer system for traffic congestion, comprising:
starting a timer on the occurrence of a first predetermined event; resetting the timer on the occurrence of a second predetermined event; and if the timer is not reset and the timer expires, blocking further messages from being sent by a processor.
- 20. The method of claim 19 further including programming the timer.
- 21. The method of claim 19 wherein said first predetermined event is a buffer having at least one message in it.
- 22. The method of claim 19 wherein said second predetermined event is a message being sent from one processor to another.
- 23. A method of isolating failures in a multi-processor system, comprising:
(a) programming the system to have at least one partition selected from the group consisting of: hard partition, firm partition, semi-hard partition, and soft partition; (b) detecting a failure in the system; (c) blocking messages from being sent from one processor to another processor upon detecting said failure; and (d) using timers to monitor the system for messages that are not able to be completed due to (c).
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application relates to the following commonly assigned co-pending applications entitled:
[0002] “Apparatus And Method For Interfacing A High Speed Scan-Path With Slow-Speed Test Equipment,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-23700; “Rotary Rule And Coherence Dependence Priority Rule,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27300; “Speculative Scalable Directory Based Cache Coherence Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27400; “Scalable Efficient I/O Port Protocol,” Ser. No. _______, filed Aug. 31, 2000, Attorney Docket No. 1662-27500; “Efficient Translation Buffer Miss Processing For Applications Using Large Pages In Systems With A Large Range Of Page Sizes By Eliminating Page Table Level,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27600; “Speculative Directory Writes In A Directory Based Cache Coherent Nonuniform Memory Access Protocol,” Ser. No. _______, filed Aug. 31, 2000, Attorney Docket No. 1662-27800; “Special Encoding Of Known Bad Data,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27900; “Broadcast Invalidate Scheme,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28000; “Mechanism To Keep All Pages Open In A DRAM Memory System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28100; “Programmable DRAM Address Mapping Mechanism,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28200; “Mechanism To Enforce Memory Read/Write Fairness, Avoid Tristate Bus Conflicts, And Maximize Memory Bandwidth,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29200; “An Efficient Address Interleaving With Simultaneous Multiple Locality Options,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29300; “A High Performance Way Allocation Strategy For A Multi-Way Associative Cache System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29400; “Method And System For Absorbing Defects In High Performance Microprocessor With A Large N-Way Set Associative Cache,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29500; “A Method For Reducing Directory Writes And Latency In A High Performance, Directory-Based, Coherency Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29600; “Mechanism To Reorder Memory Read And Write Transactions For Reduced Latency And Increased Bandwidth,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-30800; “Look-Ahead Mechanism To Minimize And Manage Bank Conflicts In A Computer Memory System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-30900; “Computer Resource Management And Allocation System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31000; “Input Data Recovery Scheme,” Ser. No. _______, filed Aug. 31, 2000, Attorney Docket No. 1662-31100; “Fast Lane Prefetching, ” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31200; “Mechanism For Synchronizing Multiple Skewed Source-Synchronous Data Channels With Automatic Initialization Feature,” Ser. No. _____, filed Aug. 31, 2000, Attorney Docket No. 1662-31300; “Mechanism To Control The Allocation Of An N-Source Shared Buffer,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31400; and “Chaining Directory Reads And Writes To Reduce DRAM Bandwidth In A Directory Based CC-NUMA Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31500; and provisional application titled “Alpha Processor,” Ser. No. filed Aug. 31, 2000, all of which are incorporated by reference herein.
Continuations (1)
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Number |
Date |
Country |
Parent |
09651949 |
Aug 2000 |
US |
Child |
10691744 |
Oct 2003 |
US |