Claims
- 1. A method for providing for error recovery during in-circuit programming of a computer system, comprising:
monitoring the in-circuit programming process in order to detect a delay in transmission of in-circuit programming instructions from a remote host; and restarting the in-circuit programming process if the delay exceeds a timeout value.
- 2. The method of claim 1, including the step of reinitializing the computer system if the delay exceeds the timeout value.
- 3. The method of claim 1, wherein the step of monitoring is performed by using a watch dog timer coupled to the computer system.
- 4. A device providing error recovery on an integrated circuit, comprising:
a processor on the integrated circuit; a mini-boot code segment in non-volatile memory on the integrated circuit, coupled to the processor; a status register on the integrated circuit coupled to the processor; an additional code segment in non-volatile memory on the integrated circuit, coupled to the processor; a watchdog timer coupled to the processor on the integrated circuit; and logic on the processor, to
load a program in the additional code segment, with the watchdog timer running; modify the status register when the program is successfully loaded in the additional code segment; during initialization of the system, boot to the program if the status register has been modified and boot to the mini-boot code otherwise.
- 5. A device providing error recovery on an integrated circuit, comprising:
a processor on the integrated circuit; a first memory segment of non-volatile memory on the integrated circuit, coupled to the processor, loaded with a first boot code provided by a manufacturer; a status register on the integrated circuit coupled to the processor; a second memory segment of non-volatile memory on the integrated circuit, coupled to the processor; a watchdog timer coupled to the processor on the integrated circuit; and logic on the processor, to
load a program in the additional code segment, with the watchdog timer running; modify the status register when the program is successfully loaded in the second memory segment; during initialization of the system, boot to the second memory segment if the status register has been modified and boot to the first memory segment code otherwise.
- 6. A device providing error recovery on an integrated circuit, comprising:
a processor on the integrated circuit; a first boot code present in a non-volatile memory on the integrated circuit prior to in-circuit programming, coupled to the processor; a status register on the integrated circuit coupled to the processor; second boot code in a non-volatile memory on the integrated circuit, coupled to the processor; a watchdog timer coupled to the processor on the integrated circuit; and logic on the processor, to
initiate in-circuit programming to load a program in the additional code segment, with the watchdog timer running; modify the status register when the in-circuit programming is successful; during initialization of the system, booting to the program if the status register has been modified and booting to the mini-boot code otherwise.
- 7. A method of providing for error recovery on an integrated circuit, comprising:
providing an in-circuit programming status on the integrated circuit having an initial value; initiating an in-circuit programming process, with a watchdog timer running; when the in-circuit programming process successfully terminates, changing the in-circuit programming status to a changed value; and during initialization of the system, executing a first boot code sequence on the integrated circuit if the in-circuit programming status has the initial value, the first boot code sequence being programmable through the in-circuit programming process, and executing a second boot code sequence on the integrated circuit if the in-circuit programming status has the changed value, the second boot code sequence not being modified during the in-circuit programming process.
- 8. The method of claim 7, wherein the first boot code sequence is an application program and the second boot code sequence is a mini-boot program.
- 9. The method of claim 7, wherein the second boot code sequence is loaded on the integrated circuit as delivered by a manufacturer.
- 10. An apparatus for in-circuit programming of an integrated circuit, comprising:
a processor on the integrated circuit which executes instructions; an external port on the integrated circuit through which data is received from an external source; a first memory array comprising in-circuit modifiable, non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling transfer of instructions into the integrated circuit from the external source through the external port; and a second memory array on the integrated circuit, which stores instructions for execution by the processor that are not to be modified by the set of instructions for controlling transfer of instructions into the integrated circuit from the external source, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.
- 11. The integrated circuit of claim 10, wherein said first set of instructions includes a first boot program of instructions, and the second set of instructions includes a second boot program of instructions.
- 12. In an integrated circuit including a processor and an external port, a method for in-circuit programming of the integrated circuit, comprising:
providing on the integrated circuit a first memory array comprising non-volatile memory cells, and a second memory array to store instructions that are not to be modified by in-circuit programming; receiving an in-circuit program command from an initiator external to the integrated circuit; in response to the in-circuit program command, using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array; and using the processor to execute a set of instructions from the first memory array to control the transfer of a set of instructions into the integrated circuit from an external source through the external port.
- 13. The integrated circuit of claim 12, including a store on the substrate holding first and second boot vectors, the first boot vector pointing to the first boot program of instructions, and the second boot vector pointing to the second boot program of instructions.
- 14. The integrated circuit of claim 12, including a status indicator which indicates status of an instance of transferring instructions into the modifiable non-volatile memory from an external source.
- 15. An integrated circuit on a substrate, including a processor which executes instructions, and comprising:
memory on the substrate to store instructions for execution by the processor, comprising modifiable non-volatile memory; a first set of instructions stored in the memory, the first set of instructions being protected from modification by the processor, and including instructions for controlling erasing, programming and verifying instructions in the modifiable non-volatile memory; a second set of instructions stored in the memory and accessible by the processor, the second set of instructions being modifiable by the processor, and including a set of instructions for controlling transfer of instructions into the modifiable non-volatile memory on the substrate from an external source; and a watchdog timer on the substrate, which operates during execution of the set of instructions for controlling transfer of instructions into the modifiable non-volatile memory from an external source.
- 16. An integrated circuit on a substrate, including a processor which executes instructions, and comprising:
memory on the substrate to store instructions for execution by the processor, comprising modifiable non-volatile memory; a first set of instructions stored in the memory, the first set of instructions being protected from modification by the processor, and including instructions for controlling erasing, programming and verifying instructions in the modifiable non-volatile memory and a first boot program of instructions in the modifiable non-volatile memory; a second set of instructions stored in the memory and accessible by the processor, the second set of instructions being modifiable by the processor, and including a set of instructions for controlling transfer of instructions into the modifiable non-volatile memory on the substrate from an external source which call the instructions for controlling erasing, programming and verifying instructions in the modifiable non-volatile memory, and a second boot program of instructions; and a watchdog timer on the substrate, which operates during execution of the set of instructions for controlling transfer of instructions into the modifiable non-volatile memory from an external source; a status indicator which indicates status of an instance of transferring instructions into the modifiable non-volatile memory from an external source, and a store on the substrate holding first and second boot vectors, the first boot vector pointing to the first boot program of instructions, and the second boot vector pointing to the second boot program of instructions, and logic responsive to the watchdog timer to signal a reset, and in response to the reset, to select one of the first boot vector or the second boot vector in response to the status indicator.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of application Ser. No. 10/097,839 filed Mar. 13, 2002, which is a continuation of application Ser. No. 09/925,920 filed Aug. 9, 2001, now U.S. Pat. No. 6,401,221; which is a continuation application of application Ser. No. 09/029,118 filed Feb. 23, 1998, now U.S. Pat. No. 6,282,675; which is the national stage filing of International Application No. PCT/US97/13848, filed Aug. 6, 1997.
[0002] This application is also a continuation-in-part of application Ser. No. 10/314,638 filed Dec. 9, 2002; which is a continuation of application Ser. No. 09/525,835 filed Mar. 15, 2000, now U.S. Pat. No. 6,493,788; which is a continuation of application Ser. No. 08/952,045 filed Oct. 3, 1997, now U.S. Pat. No. 6,151,657; which is the national stage filing of International Application No. PCT/US96/17302 filed Oct. 28, 1996.
[0003] This application is related to international application No. PCT/US96/17302, entitled, “PROCESSOR WITH EMBEDDED IN-CIRCUIT PROGRAM STRUCTURES,” filed Oct. 28, 1996 by applicants Macronix International Co., Ltd., for all states other than the United States, and Albert C. Sun, Chee H. Lee and Chang L. Chen for the United States. This application hereby incorporates by reference this prior application to the extent that it has not been bodily incorporated herein.
[0004] This application is also related to international application No. PCT/US97/05622, entitled, “IN-CIRCUIT PROGRAMMING ARCHITECTURE WITH ROM AND FLASH MEMORY,” filed Apr. 3, 1997 by applicants Macronix International Co., Ltd., for all states other than the United States, and Albert C. Sun, Chee H. Lee and Chang L. Chen for the United States. This application hereby incorporates by reference this prior application to the extent that it has not been bodily incorporated herein.
[0005] This application is further related to International Application No. PCT/US96/17302 entitled PROCESSOR WITH EMBEDDED IN-CIRCUIT PROGRAMMING STRUCTURES, filed Oct. 28, 1996 by applicant Macronix International Co., Ltd., for all states other than the United States, and by applicants Albert C. Sun, Chee H. Lee and Chang L. Chen for the United States.
Continuations (5)
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Continuation in Parts (1)
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