Patent Application
20130332775
In fault tree analysis (FTA), and in a case that minimal cut sets are required to have at most a certain maximal order, for example, M, a weeding method is introduced to remove an overlong conjunction (combination) of events generated during evaluation of the MCSs.
In fault tree analysis (FTA), and in a case that minimal cut sets are required to have at most a certain maximal order, for example, M, a weeding algorithm is introduced to remove an overlong conjunctions (or combinations) of events generated during evaluation of the MCSs.
A classical weeding algorithm is disclosed in NPL 1. Given a conjunction, and representing the number of order of the conjunction as V, it can be calculated by: V=α+β+δ. in which α and β denote the numbers of the basic events of the conjunction and the disjunctions (OR gates) with only basic events none of which is included in category 1 and no commonality among themselves, respectively. The parameter δ is set to 1 if the conjunction contains a set of disjunctions with only basic events none of which is included in category 1 but contain a commonality among themselves; otherwise, δ is set 0.
In this algorithm, basic events and two types of OR gates are taken into account, and individual numbers of orders of other gates, such as k/n gates, are excluded (that is, the numbers of orders are simply regarded as zero when calculating V).
Moreover, a standard expanding algorithm of k/n gate is disclosed in NPL 2. According to NPL 2, and representing e1, . . . , en as events, a k/n gate as given by:
k/n=(e1, . . . , en)
can be expanded in the form given by:
k/n=(e1, . . . , en)=e1·(k−1/n−1)(e2, . . . , en)+(k)/(n−1)(e2, . . . , en)
The time complexity of this expanding algorithm can be reduced by:
O(k·n)
as compared with a conventional calculating method.
NPL 1: D. M. Rasmuson and N. H. Marshall, “FATRAM—A Core Efficient Cut-Set Algorithm”, IEEE Trans. on Reliability, Vol. R-27, 1978, pp. 250-253.
NPL 2: A. Rauzy, “Toward an Efficient Implementation of the MOCUS Algorithm”, IEEE Trans. on Reliability, Vol. 52, 2003, pp. 175-180.
However, the expanding still results in a factorial space complexity in terms of the number of final resulting conjunctions, even given a maximal order M and the weeding algorithm of the non-patent reference 1. The space problem can easily result in memory out in practice, even for not so big k, n, and M. The traditional algorithms are apt to fail when relatively large and complex k/n gates are introduced, such as the server clusters of data centers in cloud computing. As used herein, “complex” refers to a condition that inputs to a k/n gate are not basic but intermediate events.
The reason is that the orders of k/n gates are not evaluated by traditional methods (i.e., simply treated as 0), and the k/n gates are supposed to be expanded repeatedly until k=1 or k=n, or the orders of the conjunctions including them are bigger than the maximal order of MCSs. This may result in a huge number of overlong conjunctions and cause memory out problem due to the factorial space complexity of expanding.
The present invention has been thus made in view of such a problem, and its object is to provide a fault tree analysis system, a fault tree analysis method, and a program therefor capable of weeding an overlong conjunction including a k/n gate at the early stage during evaluation of MCSs in a fault tree without expanding such a k/n gate.
The present invention is a fault tree analysis system, comprising: k/n conjunction weeding means for weeding a conjunction including disjoint basic k/n gates and disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
The present invention is a fault tree analysis method, comprising: weeding a conjunction including disjoint basic k/n gates and disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
The present invention is a program for fault tree analysis, causing an information processing apparatus to execute: k/n conjunction weeding processing of weeding a conjunction including disjoint basic k/n gates and disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
The present invention can weed out some overlong conjunctions including k/n gates at the early stage during evaluation of minimal cut sets (MCSs) in a fault tree.
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
Referring to
These means operate as generally described below:
The general MCS evaluating means 110 reduces the MCSs from a logically expressed fault tree, and weeds non-k/n conjunctions (that do not include k/n gates) generated during the reduction of the MCSs.
The k/n conjunction weeding means 120 weeds a conjunction including disjoint basic and/or simple k/n gates. A result of the weeding (either the original conjunction or logic False according to whether its order is less than or equal to the maximal order or not, respectively) is sent back to the general MCS evaluating means 110 for further evaluation of MCSs.
As used herein, a basic k/n gate refers to a k/n gate with inputs of only basic events.
Moreover, a simple k/n gate refers to a k/n gate with inputs of DNFs of basic events, and I call the conjunctive clauses of the DNFs as the input clauses of the k/n gate for short afterwards.
Furthermore, a disjoint k/n gate refers to a k/n gate that includes no common (repeated) input event or clause with the other events of the same conjunction.
Next, a general operation of the present embodiment will be described in detail with reference to
First, a fault tree in a logical expression is input to the present system (Step A1).
Subsequently, the general MCS evaluating means 110 evaluates the MCSs with traditional methods such as first transforming the input fault tree into a DNF and then removing redundant conjunctions from the DNF (Step A2).
A check is made for each (intermediate) conjunction whether the conjunction includes a k/n gate or not.
In a case that it includes a k/n gate, the conjunction is called a k/n conjunction; otherwise, a non-k/n conjunction. For a k/n conjunction, the k/n conjunction weeding means 120 applies a weeding process (Step A3). For a non-k/n conjunction, the general MCS evaluating means 110 applies a conventional weeding process (e.g., the one according to NPL 1) to it (Step A4).
The k/n conjunction weeding process proceeds by classifying events in the conjunction. Four kinds of events are considered as the order contributors of the conjunction as follows:
(1) A set of basic events, let the number (of such basic events) be α;
(2) A set of OR gates with inputs of only basic events, none of which is included in (1) and contain no commonality (not repeated input) among themselves, let the number (of such OR gates) be β;
(3) A set of OR gates with inputs of only basic events, none of which is included in (1) but contain some commonality among themselves. A parameter δ is set to 1 in a case that the cardinality of such a set of OR gates is greater than 0; otherwise, to 0;
(4) A set of disjoint basic and simple k/n gates, let the number (of such k/n gates) be m, and a parameter ε is defined as:
ε=Σi=1mki
The other events of the conjunction, such as AND gates with inputs of non basic events, are not considered as the contributors and their orders are treated as 0.
Representing the order of a conjunction as V, it can be calculated by V=α+β+δ+ε. In a case that V>M, the conjunction is weeded out; otherwise, it is retained for further MCS reduction.
After the weeding, the system makes a check whether all conjunctions are MCSs or not. In a case that all the conjunctions are MCSs, the resulting MCSs are output (Step A5). In a case that not all conjunctions are MCSs, the process goes back to Step A2, and further MCS reduction is made.
Next, an effect of the present embodiment will be described.
The present embodiment comprises the step of evaluating the order of a disjoint basic k/n gates or a disjoint simple k/n gate, such that the order of a conjunction including disjoint basic and/or simple k/n gates can be evaluated more accurately without expanding the k/n gates. Therefore, an overlong conjunction including disjoint basic and/or simple k/n gates can be timely weeded out and the space (memory) for storing otherwise expanded k/n gates can be saved.
Next, a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.
The second embodiment comprises k/n gate simplifying means 111 in addition to the first embodiment.
The k/n gate simplifying means 111 simplifies a k/n gates into a disjoint basic or a simple k/n gate by removing the repeated input events and clauses to the k/n gate.
Next, a general operation of the second embodiment will be described in detail with reference to
The second embodiment is similar to the first embodiment, except an additional Step A2a is added between Steps A2 and A3.
At Step A2a, the k/n gate simplifying means 111 removes the repeated inputs to simplify a k/n gate into a disjoint basic or simple k/n gate.
Representative simplifying rules are listed in
Next, an effect of the second embodiment will be described.
The second embodiment comprises a step of simplifying a k/n gate into a disjoint basic k/n gate or a disjoint simple k/n gate. Hence, a non-disjoint k/n gate can be accurately weeded without expanding any part thereof.
Next, an operation of the embodiments of the present invention will be described using specific examples.
Two cases are used to demonstrate effectiveness of the present invention. It should be noted that the maximal order for MCSs is defined as five in the two cases.
A fault tree in the first case is comprised of only one basic k/n gate.
A fault tree in the second case is comprised of many k/n gates having repeated inputs.
A logical expression of the fault tree in the first case is shown in
Referring to
As compared with a conventional method, the computation time in the present case for the present invention is almost zero, whereas the ITEM ToolKit 7.08 (a commercial FTA tool) based on the conventional method requires approximately 700 milliseconds.
Further, the ITEM ToolKit encounters a memory overflow error when k≧8 and n≧16, while the present invention is still capable of processing within a negligible period of time.
Referring to
Two kinds of methods can be applied in this case as shown in
A final result of the fault tree in the example obtained by repetitively applying the simplifying and weeding processes is shown in
Regarding the present case, the present invention requires approximately 48 milliseconds in evaluating NCSs, whereas the ITEM ToolKit requires approximately 21 seconds (not milliseconds, unlike the present invention). This comparison proves efficiency of the present invention.
Moreover, while several components may be configured in hardware, they also may be implemented by a computer program, as is obvious from the preceding description. In this case, a processor that is operated by programs stored in a program memory implements functions and/or operations similar to those in the aforementioned embodiments. It is also possible to implement part of functions of the aforementioned embodiments by a computer program.
Further, the content of the above-mentioned exemplary embodiments can be expressed as follows.
(Supplementary note 1) A fault tree analysis system, comprising:
k/n conjunction weeding means for weeding a conjunction including disjoint basic k/n gates and simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
(Supplementary note 2) The fault tree analysis system according to Supplementary note 1, comprising:
k/n gate simplifying means for removing the repeated input events and clauses to a k/n gate and simplifying the k/n gate into a disjoint basic or a disjoint simple k/n gate based on a set of simplifying rules.
(Supplementary note 3) The fault tree analysis system according to Supplementary notes 1 or 2, wherein:
said basic k/n gate refers to a k/n gate whose inputs are basic events only;
said simple k/n gate refers to a k/n gate whose inputs are DNFs (disjunctive normal forms) of basic events; and
said disjoint k/n gate refers to a k/n gate that includes no input event or clause common to another event in the same conjunction.
(Supplementary note 4) A fault tree analysis method, comprising:
weeding a conjunction including disjoint basic k/n gates and disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
(Supplementary note 5) The fault tree analysis method according to Supplementary note 4, further comprising:
removing the repeated input events and clauses to a k/n gate and
simplifying the k/n gate into a disjoint basic k/n gate or a disjoint simple k/n gate based on a set of simplifying rules.
(Supplementary note 6) The fault tree analysis method according to Supplementary notes 4 or 5, wherein:
said basic k/n gate refers to a k/n gate whose inputs are basic events only;
said simple k/n gate refers to a k/n gate whose inputs are DNFs (disjunctive normal forms) of basic events; and
said disjoint k/n gate refers to a k/n gate that includes no input event or clause common to another event in the same conjunction.
(Supplementary note 7) A program for fault tree analysis, causing an information processing apparatus to execute:
k/n conjunction weeding processing of weeding a conjunction including disjoint basic k/n gates and disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of MCSs.
(Supplementary note 8) The program according to Supplementary note 7, causing the information processing apparatus to execute:
k/n gate simplifying processing of removing the repeated input events and clauses to a k/n gates and simplifying the k/n gate into a disjoint basic k/n gate or a disjoint simple k/n gate based on a set of simplifying rules.
(Supplementary note 9) The program according to Supplementary notes 7 or 8, wherein:
said basic k/n gate refers to a k/n gate whose inputs are basic events only;
said simple k/n gate refers to a k/n gate whose inputs are DNFs (disjunctive normal forms) of basic events; and
said disjoint k/n gate refers to a k/n gate that includes no input event or clause common to another event in the same conjunction.
Above, although the present invention has been particularly described with reference to the preferred embodiments and examples, it should be readily apparent to those of ordinary skill in the art that the present invention is not always limited to the above-mentioned embodiments and examples, and changes and modifications in the form and details may be made without departing from the spirit and scope of the invention.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2011-035872, filed on Feb. 22, 2011, the disclosure of which is incorporated herein in its entirety by reference.
110 General MCS evaluating means
111 k/n gate simplifying means
120 k/n conjunction weeding means
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011035872 | Feb 2011 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2012/053826 | 2/17/2012 | WO | 00 | 8/21/2013 |
