FEDERATED LEARNING MECHANISM

BACKGROUND

Machine Learning (ML) models are trained using sensitive real-world data in order to provide improvements to a wide variety of applications (e.g., medical screening, fraud detections, autonomous driving, etc.). However, large scale collection of sensitive data entails risks in which consequences of mishandling such data could be devastating. Federated learning is a technique that trains a joint model across multiple decentralized edge computing nodes. In federated learning, a centralized server chooses a model and transmits to the model to participating edge nodes. Each node subsequently trains its local copy on its private data and transmits updates to the centralized server, which aggregates the updates to a new global model.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

FIG. 1 illustrates one embodiment of a system;

FIG. 2 illustrates one embodiment of a federated learning training scheme;

FIG. 3 illustrates one embodiment of a federated learning mechanism;

FIG. 4 illustrates one embodiment of the transmission of matrices from a server to edge devices;

FIG. 5 illustrates one embodiment of a learning client;

FIG. 6 illustrates one embodiment of an edge device sampling a trained model and transmitting the sampled train model to the server as sampled trained model updates.

FIG. 7 illustrates one embodiment of reconstruction and aggregation.

FIG. 8 is a flow diagram illustrating one embodiment of a process performed by a federated learning mechanism;

FIG. 9 is a flow diagram illustrating one embodiment of a performed by a federated client; and

FIG. 10 is a schematic diagram of an illustrative electronic computing device.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.

FIG. 1 illustrates one embodiment of a system 100 having a computing device 120 employing a federated learning mechanism 110. As shown in FIG. 1, computing device 120 includes a host server computer serving as a host machine for employing federated learning mechanism 110 to facilitate a machine learning technique to train an algorithm across multiple decentralized edge devices 121A-121N. Computing device 120 may include (without limitation) server computers (e.g., cloud server computers, etc.), desktop computers, cluster-based computers, set-top boxes (e.g., Internet-based cable television set-top boxes, etc.), etc. Computing device 120 includes an operating system (“OS”) 406 serving as an interface between one or more hardware/physical resources of computing device 120 and one or more edge devices 121A-121N, etc. Computing device 120 further includes processor(s) 102, memory 104, input/output (“I/O”) sources 108, such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, etc.

Edge devices 121A-N may include (without limitation) organization-based server computers, desktop computers, laptop computers, mobile computing devices, such as smartphones, tablet computers, personal digital assistants, e-readers, media Internet devices, smart televisions, television platforms, wearable devices (e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc.), media players, global positioning system-based navigation systems, cable setup boxes, etc.

In one embodiment, the illustrated database(s) 140 store (without limitation) information and underlying database records having customer and user data therein on to process data on behalf of edge devices 121A-N. In some embodiments, computing device 120 receives input and other requests from a plurality of edge devices 121A-N over one or more networks 135.

In one embodiment, computing device 120 may include a server computer that may be further in communication with one or more databases or storage repositories, such as database(s) 140, which may be located locally or remotely over one or more networks, such as network(s) 135 (e.g., cloud network, Internet, proximity network, intranet, Internet of Things (“IoT”), Cloud of Things (“CoT”), etc.). Computing device 120 is further shown to be in communication with any number and type of other computing devices, such as client computing devices 121A-N, over one or more networks, such as network(s) 135.

In one embodiment, computing device 120 may serve as a host for federated learning mechanism 110, and be in communication with one or more edge devices 121A-N, over one or more network(s) 135, and any number and type of dedicated nodes. Edge devices 121A-N each comprise a learning client 122 (e.g., 122A-122N) to operate in coordination with federated learning mechanism 110 to federated learning. In such an embodiment, a model is distributed to each of edge devices 121A-121N, where it is stored at a database 123 (e.g., 123A-123N), trained and transmitted back to federated learning mechanism 110.

FIG. 2 illustrates one embodiment of a conventional federated learning training scheme. The first stage of the federated learning training scheme is to transmit gradients from databases at edge device (or edges) to a server, where the gradients are aggregated. Subsequently, model updates are transmitted back to the edges and local learning and model updates are performed. The above-described federated learning training scheme enables training a unified model without sharing the data, thus preserving the confidentiality of the training data. However, the scheme does not prevent malicious use of the data by the centralized server. As a result, a malicious server may infer sensitive properties on the training data or even reconstruct training samples, which could lead to potential privacy violation.

According to one embodiment, federated learning mechanism 110, in conjunction with learning clients 122, perform federated learning based on compressed sensing. In such an embodiment, a compressed sensing process is performed in which each client 122 provides only a sampled subset of an update to a learning model to federated learning mechanism 110 at computing device 120. In a further embodiment, the subsets are sampled for each edge device 121 based on a pre-defined measurement matrix that significantly increases the complexity of original data reconstruction while preserving its contribution to the model improvement.

FIG. 3 illustrates one embodiment of a federated learning mechanism 110, including matrix generation engine 310, reconstruction logic 320 and aggregation logic 330. Matrix generation engine 310 generates a unique measurement matrix (Φ_i) for each edge device 121. Subsequently, the matrices are transmitted to edge devices 121 (e.g., via a secure communication channel). FIG. 4 illustrates one embodiment of the transmission of secured matrix data (Φ_i-Φ_n) from a server to edge devices. In one embodiment, the generated matrices are used at a respective learning client 122 as a compressive-sensing measurement matrix. In such an embodiment, learning client 122 uses its unique measurement matrix as a sampling matrix to sample trained model updates received from federated learning mechanism 110 during each iteration of training.

Reconstruction logic 320 receives sampled trained model updates from each edge device 121 and reconstructs each of the sampled trained model update data (or updates) using the associated unique measurement matrix to generate the trained model updates. In one embodiment, reconstruction logic 320 performs the reconstruction by applying a reconstruction optimization algorithm using a corresponding measurement matrix.

In one embodiment, the trained model updates comprises machine learning gradient updates. Aggregation logic 330, aggregates the trained model updates to generate an updated unified model that is transmitted back to edge devices 121. Since weights in trained model updates are compressed, the unified model is undergoing sparsification. In one embodiment, sparsification occurs because compressed sensing reconstruction is not lossless (e.g., model updates are not perfectly sparse). Thus, the compression is lossy and sparsification is a by-product of the measurement.

FIG. 5 illustrates one embodiment a learning client 122. As shown in FIG. 5, learning client 122 includes training logic 510 and compression logic 520. Training logic 510 trains a unified model received from federated learning mechanism 110 to generate the trained model updates. In one embodiment, the model is trained using a machine learning algorithm. In such an embodiment, the trained model updates may comprise a combination of training weights and/or gradients based on the training scheme that is implemented.

Compression logic 520 implements compressed sensing to sample the trained model updates using a measurement matrix to generate the sampled trained model updates. Accordingly, trained model updates comprise encrypted updates that are transmitted to computing device 120. FIG. 6 illustrates one embodiment of an edge device sampling a trained model and transmitting the sampled train model to the server as sampled trained model updates. In one embodiment, compressed sensing is a way to reconstruct a signal from a series of sampling measurements. In such an embodiment, compressed sensing is typically applied in a data acquisition stage to make the signal acquisition stage more efficient (e.g., requiring less sensors to acquire the signal). In a further embodiment, applying the measurement matrix to the model updates specifies indexes of the values of the models updates to send to federated learning mechanism 110.

As discussed above, federated learning mechanism 110 receives the sampled trained model updates, applies a reconstruction optimization algorithm using a corresponding measurement matrix and aggregates the trained models to generate the updated unified model. Subsequently, the updated unified model is transmitted back to edge devices 121. FIG. 7 illustrates one embodiment of reconstruction and aggregation at the server.

FIG. 8 is a flow diagram illustrating one embodiment of a process performed by a federated learning mechanism. At processing block 810, measurement matrices (Φ_i-Φ_n) are generated. At processing block 820, the measurement matrices are transmitted to edge devices. At processing block 830, sampled trained models are received from the edge devices as sampled trained model updates. At processing block 840, the trained models are reconstructed to generate the trained model updates. As discussed above, a trained model is reconstructed by using a measurement matrix to a sampled trained model. At processing block 850, the trained model updates are aggregated to generate the unified model. At processing block 860, the unified model is transmitted to the edge devices.

FIG. 9 is a flow diagram illustrating one embodiment of a performed by a federated client. At processing block 910, an initial model to be trained is received. As discussed above, the model may be a unified model generated at computing device 120. At processing block 920, a measurement matrix is received. At processing block 930, the model is trained to generate a trained model update. At processing block 940, the trained model update is sampled via a compressed sensing model to generate a sampled trained model update. At processing block 950, the sampled trained model update is transmitted to the server.

FIG. 10 is a schematic diagram of an illustrative electronic computing device to enable enhanced protection against adversarial attacks according to some embodiments. In some embodiments, the computing device 1000 includes one or more processors 1010 including one or more processors cores 1018 and a Trusted Execution Environment (TEE) 1064, the TEE including a machine learning service enclave (MLSE) 1080. In some embodiments, the computing device 1000 includes a hardware accelerator (HW) 1068, the hardware accelerator including a cryptographic engine 1082 and a machine learning model 1084. In some embodiments, the computing device is to provide enhanced protections against ML adversarial attacks, as provided in FIGS. 1-9.

The computing device 1000 may additionally include one or more of the following: cache 1062, a graphical processing unit (GPU) 1012 (which may be the hardware accelerator in some implementations), a wireless input/output (I/O) interface 1020, a wired I/O interface 1030, memory circuitry 1040, power management circuitry 1050, non-transitory storage device 1060, and a network interface 1070 for connection to a network 1072. The following discussion provides a brief, general description of the components forming the illustrative computing device 1000. Example, non-limiting computing devices 1000 may include a desktop computing device, blade server device, workstation, or similar device or system.

In embodiments, the processor cores 1018 are capable of executing machine-readable instruction sets 1014, reading data and/or instruction sets 1014 from one or more storage devices 1060 and writing data to the one or more storage devices 1060. Those skilled in the relevant art will appreciate that the illustrated embodiments as well as other embodiments may be practiced with other processor-based device configurations, including portable electronic or handheld electronic devices, for instance smartphones, portable computers, wearable computers, consumer electronics, personal computers (“PCs”), network PCs, minicomputers, server blades, mainframe computers, and the like.

The processor cores 1018 may include any number of hardwired or configurable circuits, some or all of which may include programmable and/or configurable combinations of electronic components, semiconductor devices, and/or logic elements that are disposed partially or wholly in a PC, server, or other computing system capable of executing processor-readable instructions.

The computing device 1000 includes a bus or similar communications link 1016 that communicably couples and facilitates the exchange of information and/or data between various system components including the processor cores 1018, the cache 1062, the graphics processor circuitry 1012, one or more wireless I/O interfaces 1020, one or more wired I/O interfaces 1030, one or more storage devices 1060, and/or one or more network interfaces 1070. The computing device 1000 may be referred to in the singular herein, but this is not intended to limit the embodiments to a single computing device 1000, since in certain embodiments, there may be more than one computing device 1000 that incorporates, includes, or contains any number of communicably coupled, collocated, or remote networked circuits or devices.

The processor cores 1018 may include any number, type, or combination of currently available or future developed devices capable of executing machine-readable instruction sets.

The processor cores 1018 may include (or be coupled to) but are not limited to any current or future developed single- or multi-core processor or microprocessor, such as: on or more systems on a chip (SOCs); central processing units (CPUs); digital signal processors (DSPs); graphics processing units (GPUs); application-specific integrated circuits (ASICs), programmable logic units, field programmable gate arrays (FPGAs), and the like. Unless described otherwise, the construction and operation of the various blocks shown in FIG. 10 are of conventional design. Consequently, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art. The bus 1016 that interconnects at least some of the components of the computing device 1000 may employ any currently available or future developed serial or parallel bus structures or architectures.

The system memory 1040 may include read-only memory (“ROM”) 1042 and random access memory (“RAM”) 1046. A portion of the ROM 1042 may be used to store or otherwise retain a basic input/output system (“BIOS”) 1044. The BIOS 1044 provides basic functionality to the computing device 1000, for example by causing the processor cores 1018 to load and/or execute one or more machine-readable instruction sets 1014. In embodiments, at least some of the one or more machine-readable instruction sets 1014 cause at least a portion of the processor cores 1018 to provide, create, produce, transition, and/or function as a dedicated, specific, and particular machine, for example a word processing machine, a digital image acquisition machine, a media playing machine, a gaming system, a communications device, a smartphone, or similar.

The computing device 1000 may include at least one wireless input/output (I/O) interface 1020. The at least one wireless I/O interface 1020 may be communicably coupled to one or more physical output devices 1022 (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wireless I/O interface 1020 may communicably couple to one or more physical input devices 1024 (pointing devices, touchscreens, keyboards, tactile devices, etc.). The at least one wireless I/O interface 1020 may include any currently available or future developed wireless I/O interface. Example wireless I/O interfaces include, but are not limited to: BLUETOOTH®, near field communication (NFC), and similar.

The computing device 1000 may include one or more wired input/output (I/O) interfaces 1030. The at least one wired I/O interface 1030 may be communicably coupled to one or more physical output devices 1022 (tactile devices, video displays, audio output devices, hardcopy output devices, etc.). The at least one wired I/O interface 1030 may be communicably coupled to one or more physical input devices 1024 (pointing devices, touchscreens, keyboards, tactile devices, etc.). The wired I/O interface 1030 may include any currently available or future developed I/O interface. Example wired I/O interfaces include, but are not limited to: universal serial bus (USB), IEEE 1394 (“FireWire”), and similar.

The computing device 1000 may include one or more communicably coupled, non-transitory, data storage devices 1060. The data storage devices 1060 may include one or more hard disk drives (HDDs) and/or one or more solid-state storage devices (SSDs). The one or more data storage devices 1060 may include any current or future developed storage appliances, network storage devices, and/or systems. Non-limiting examples of such data storage devices 1060 may include, but are not limited to, any current or future developed non-transitory storage appliances or devices, such as one or more magnetic storage devices, one or more optical storage devices, one or more electro-resistive storage devices, one or more molecular storage devices, one or more quantum storage devices, or various combinations thereof. In some implementations, the one or more data storage devices 1060 may include one or more removable storage devices, such as one or more flash drives, flash memories, flash storage units, or similar appliances or devices capable of communicable coupling to and decoupling from the computing device 1000.

The one or more data storage devices 1060 may include interfaces or controllers (not shown) communicatively coupling the respective storage device or system to the bus 1016. The one or more data storage devices 1060 may store, retain, or otherwise contain machine-readable instruction sets, data structures, program modules, data stores, databases, logical structures, and/or other data useful to the processor cores 1018 and/or graphics processor circuitry 1012 and/or one or more applications executed on or by the processor cores 1018 and/or graphics processor circuitry 1012. In some instances, one or more data storage devices 1060 may be communicably coupled to the processor cores 1018, for example via the bus 1016 or via one or more wired communications interfaces 1030 (e.g., Universal Serial Bus or USB); one or more wireless communications interfaces 1020 (e.g., Bluetooth®, Near Field Communication or NFC); and/or one or more network interfaces 1070 (IEEE 802.3 or Ethernet, IEEE 802.11, or Wi-Fi®, etc.).

Processor-readable instruction sets 1014 and other programs, applications, logic sets, and/or modules may be stored in whole or in part in the system memory 1040. Such instruction sets 1014 may be transferred, in whole or in part, from the one or more data storage devices 1060. The instruction sets 1014 may be loaded, stored, or otherwise retained in system memory 1040, in whole or in part, during execution by the processor cores 1018 and/or graphics processor circuitry 1012.

The computing device 1000 may include power management circuitry 1050 that controls one or more operational aspects of the energy storage device 1052. In embodiments, the energy storage device 1052 may include one or more primary (i.e., non-rechargeable) or secondary (i.e., rechargeable) batteries or similar energy storage devices. In embodiments, the energy storage device 1052 may include one or more supercapacitors or ultracapacitors. In embodiments, the power management circuitry 1050 may alter, adjust, or control the flow of energy from an external power source 1054 to the energy storage device 1052 and/or to the computing device 1000. The power source 1054 may include, but is not limited to, a solar power system, a commercial electric grid, a portable generator, an external energy storage device, or any combination thereof.

For convenience, the processor cores 1018, the graphics processor circuitry 1012, the wireless I/O interface 1020, the wired I/O interface 1030, the storage device 1060, and the network interface 1070 are illustrated as communicatively coupled to each other via the bus 1016, thereby providing connectivity between the above-described components. In alternative embodiments, the above-described components may be communicatively coupled in a different manner than illustrated in FIG. 10. For example, one or more of the above-described components may be directly coupled to other components, or may be coupled to each other, via one or more intermediary components (not shown). In another example, one or more of the above-described components may be integrated into the processor cores 1018 and/or the graphics processor circuitry 1012. In some embodiments, all or a portion of the bus 1016 may be omitted and the components are coupled directly to each other using suitable wired or wireless connections.

The following clauses and/or examples pertain to further embodiments or examples. Specifics in the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples may be variously combined with some features included and others excluded to suit a variety of different applications. Examples may include subject matter such as a method, means for performing acts of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method, or of an apparatus or system for facilitating hybrid communication according to embodiments and examples described herein.

Example 1 includes an apparatus comprising one or more processors to generate measurement matrices for a plurality of edge devices in a federated learning system, transmit the matrices to the plurality of edge devices, receive sampled trained model update data from the plurality of edge devices and reconstruct the sampled trained model update data using the measurement matrices to generate the trained model update data.

Example 2 includes the subject matter of Example 1, wherein a measurement matrix is unique to an associated edge device.

Example 3 includes the subject matter of any of Examples 1 and 2, wherein the measurement matrix is used at an edge device as a compressive-sensing measurement matrix.

Example 4 includes the subject matter of any of Examples 1-3, wherein the one or more processors further to aggregate the trained model update data to generate a unified model.

Example 5 includes the subject matter of any of Examples 1-4, wherein the one or more processors further to transmit the unified model to the plurality of edge devices.

Example 6 includes an apparatus comprising one or more processors to receive a model, train the model using a machine learning algorithm to generate trained model update data and sample the data using a measurement matrix to generate sampled trained model update data.

Example 7 includes the subject matter of Example 6, wherein the measurement matrix comprises a sampling matrix.

Example 8 includes the subject matter of any of Examples 6 and 7, wherein the sampling matrix is applied to the trained model update data according to a compressed sensing process.

Example 9 includes the subject matter of any of Examples 6-8, wherein the one or more processors further to receive the measurement matrix.

Example 10 includes the subject matter of any of Examples 6-9, wherein the one or more processors further to transmit the sampled trained model update data to a server.

Example 11 includes a method comprising generating measurement matrices for a plurality of edge devices in a federated learning system, transmitting the matrices to the plurality of edge devices; receive sampled trained model update data from the plurality of edge devices and reconstructing the sampled trained model update data using the measurement matrices to generate the trained model update data.

Example 12 includes the subject matter of Example 11, wherein a measurement matrix is unique to an associated edge device.

Example 13 includes the subject matter of any of Examples 11 and 12, wherein the measurement matrix is used at an edge device as a compressive-sensing measurement matrix.

Example 14 includes the subject matter of any of Examples 11-13, further compressing aggregating the trained model update data to generate a unified model.

Example 15 includes the subject matter of any of Examples 11-14, method of claim 14, further compressing transmitting the unified model to the plurality of edge devices.

Example 16 includes at least one computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to receive a model, train the model using a machine learning algorithm to generate trained model update data and sample the data using a measurement matrix to generate sampled trained model update data.

Example 17 includes the subject matter of Example 16, wherein the measurement matrix comprises a sampling matrix.

Example 18 includes the subject matter of any of Examples 16 and 17, wherein the sampling matrix is applied to the trained model update data according to a compressed sensing process.

Example 19 includes the subject matter of any of Examples 16-18, having instructions stored thereon, which when executed by one or more processors, further cause the processors to receive the measurement matrix.

Example 20 includes the subject matter of any of Examples 16-19, having instructions stored thereon, which when executed by one or more processors, further cause the processors to transmit the sampled trained model update data to a server.

Example 21 includes at least one computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to generate measurement matrices for a plurality of edge devices in a federated learning system, transmit the matrices to the plurality of edge devices; receive sampled trained model update data from the plurality of edge devices and reconstruct the sampled trained model update data using the measurement matrices to generate the trained model update data.

Example 22 includes the subject matter of Example 21, wherein a measurement matrix is unique to an associated edge device.

Example 23 includes the subject matter of any of Examples 21 and 22, wherein the measurement matrix is used at an edge device as a compressive-sensing measurement matrix.

Example 24 includes the subject matter of any of Examples 21-23, having instructions stored thereon, which when executed by one or more processors, further cause the processors to aggregate the trained model update data to generate a unified model.

Example 25 includes the subject matter of any of Examples 21-24, having instructions stored thereon, which when executed by one or more processors, further cause the processors to transmit the unified model to the plurality of edge devices.

The above Detailed Description includes references to the accompanying drawings, which form a part of the Detailed Description. The drawings show, by way of illustration, specific embodiments that may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements in addition to those shown or described. However, also contemplated are examples that include the elements shown or described. Moreover, also contemplated are examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

Publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) are supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In addition, “a set of” includes one or more elements. In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended; that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” “third,” etc. are used merely as labels, and are not intended to suggest a numerical order for their objects.

The terms “logic instructions” as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and examples are not limited in this respect.

The terms “computer readable medium” as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and examples are not limited in this respect.

The term “logic” as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and examples are not limited in this respect.

Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.

In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular examples, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.

Reference in the specification to “one example” or “some examples” means that a particular feature, structure, or characteristic described in connection with the example is included in at least an implementation. The appearances of the phrase “in one example” in various places in the specification may or may not be all referring to the same example.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with others. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. However, the claims may not set forth every feature disclosed herein as embodiments may feature a subset of said features. Further, embodiments may include fewer features than those disclosed in a particular example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the embodiments disclosed herein is to be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Although examples have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

FEDERATED LEARNING MECHANISM

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