Patent Application
20100327932
I. Field
The present disclosure relates generally to electronics, and more specifically to a feedback system for an electronics device.
II. Background
A circuit in an electronics device may be designed to perform a particular function such as amplification, filtering, frequency conversion, etc. It may be desirable for the circuit to have a linear function, so that an output signal is linearly related to an input signal. However, the circuit typically has some nonlinearity. The output signal would then include distortion components generated by the nonlinearity of the circuit. The distortion components may degrade performance. It may be desirable to mitigate the deleterious effects of the nonlinearity of the circuit in order to improve performance.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs.
A feedback system with improved stability is described herein. The feedback system may be used to mitigate nonlinearity of various types of circuit. The feedback system may also be used for various electronics devices such as wireless communication devices, cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, broadcast receivers, Bluetooth devices, consumer electronics devices, etc. For clarity, the use of the feedback system to improve linearity of a radio frequency (RF) transmitter in a wireless communication device is described below.
A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency converted between baseband and RF in multiple stages, e.g., from baseband to an intermediate frequency (IF) in one stage, and then from IF to RF in another stage for a transmitter. In the direct-conversion architecture, a signal is frequency converted between baseband and RF in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or may have different requirements. In the exemplary design shown in
In the transmit path, digital processor 110 processes data to be transmitted and provides inphase (I) and quadrature (Q) baseband signals to transmitter 120. Within transmitter 120, lowpass filters 122a and 122b filter the I and Q baseband signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp) 124a and 124b amplify the signals from lowpass filters 122a and 122b, respectively, and provide I and Q amplified signals. An upconverter 130 receives the I and Q amplified signals and I and Q local oscillator (LO) signals from an LO signal generator 156. Within upconverter 130, a mixer 132a upconverts the I amplified signal with the I LO signal, a mixer 132b upconverts the Q amplified signal with the Q LO signal, and a summer 134 sums the outputs of mixers 132a and 132b and provides an upconverted signal. A power amplifier (PA) 140 amplifies the upconverted signal to obtain the desired output power level and provides an output RF signal. Power amplifier 140 may include a driver amplifier, one or more power amplifier stages, etc. A filter 142 filters the output RF signal to remove images caused by the frequency upconversion as well as noise in a receive frequency band and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 150 and transmitted via an antenna 152.
In the receive path, antenna 152 receives signals transmitted by base stations and/or other transmitter stations and provides an input RF signal, which is routed through duplexer or switch 150 and provided to receiver 160. Receiver 160 processes (e.g., amplifies, downconverts, and filters) the input RF signal and provides I and Q input baseband signals to digital processor 110. The details of receiver 160 are not shown in
LO signal generator 156 generates the I and Q LO signals used by upconverter 130 for frequency upconversion. A phase locked loop (PLL) 154 receives timing information from digital processor 110 and generates control signals used to adjust the frequency and/or phase of the LO signals provided by LO signal generator 156.
Digital processor 110 may include various processing units for data transmission and reception and other functions. Memory 112 may store program codes and data for wireless device 100. Digital processor 110 and memory 112 may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.
It is desirable for transmitter 120 to have a linear function so that the output RF signal is linearly related to the I and Q baseband signals. However, the circuits in transmitter 120 typically have some nonlinearity. For example, power amplifier 140, mixers 132a and 132b, amplifiers 124a and 124, and/or other circuits in transmitter 120 may have some nonlinearity. The nonlinearity may distort the output RF signal from transmitter 120 and may degrade performance.
In forward path 222, summer 226a receives and subtracts an I feedback signal FI(t) from the I input signal and provides an I compensated signal CI(t) to upconverter 230. Similarly, summer 226b receives and subtracts a Q feedback signal FQ(t) from the Q input signal and provides a Q compensated signal CQ (t) to upconverter 230. Within upconverter 230, a mixer 232a upconverts the I compensated signal with an I LO signal, a mixer 232b upconverts the Q compensated signal with a Q LO signal, and a summer 234 sums the outputs of mixers 232a and 232b and provides an upconverted signal. Power amplifier 240 amplifies the upconverted signal and provides the output RF signal.
In feedback path 224, feedback circuit 242 provides a portion of the output RF signal from power amplifier 240 as a feedback RF signal Z(t) to downconverter 250. Feedback circuit 242 has a gain of β, which is less than one. The feedback RF signal is thus an attenuated version of the output RF signal. Within downconverter 250, a mixer 252a downconverts the feedback RF signal with the I LO signal used for upconverter 230, and mixer 252b downconverts the feedback RF signal with the Q LO signal used for upconverter 230. The outputs of mixers 252a and 252b include signal components at the sum and difference frequencies. Lowpass filter 254a filters the output of mixer 252a to attenuate the signal component at the sum frequency and provides the I feedback signal comprising mostly the signal component at the difference frequency. Similarly, lowpass filter 254b filters the output of mixer 252b and provides the Q feedback signal.
When the feedback loop is closed, as shown in
The feedback in transmitter 220 is referred to as Cartesian feedback since I and Q feedback components in Cartesian coordinate are subtracted from I and Q signal components in the forward path. Ideally, the I feedback component should be aligned in phase with the I signal component, and the Q feedback component should be aligned in phase with the Q signal component. However, in a practical implementation, delays of upconverter 230, power amplifier 240, and/or other effects may result in a phase shift of φ in the output RF signal. The phase shift may also be referred to as an RF phase shift, a phase rotation, a phase offset, a delay, etc. The phase shift may be relatively large and may also be unknown or difficult to characterize, e.g., due to the presence of circuits such as RF resonators having a sharp phase transition at the resonant frequency.
The output RF signal with the phase shift may be expressed as:
Y(t)=A·[XI(t)·cos(ωt+φ)+XQ(t)·sin(ωt+φ)], Eq (1)
where A is the gain of upconverter 230 and power amplifier 240,
ω is the frequency of the I and Q LO signals, and
cos(ωt) is the I LO signal and sin(ωt) is the Q LO signal.
The phase shift may affect the stability of the feedback system. In particular, as the phase shift approaches π/2 or 180°, the feedback becomes positive, and the loop becomes unstable. It is thus desirable to account for the phase shift in order to improve the stability of the feedback system.
In an aspect, phase shift compensation may be applied in a feedback path of a feedback system to improve stability and possibly obtain other benefits. The phase shift compensation may attempt to correct for the phase shift so that the I and Q feedback components are approximately aligned in phase with the I and Q signal components, respectively.
Phase shift compensator 360 receives the I and Q feedback signals from lowpass filters 354a and 354b, rotates the I and Q feedback signals to compensate for the phase shift in the forward path, and provides an I rotated feedback signal RI(t) and a Q rotated feedback signal RQ (t). Summer 326a subtracts the I rotated feedback signal from an I input signal and provides an I compensated signal to upconverter 330. Similarly, summer 326b subtracts the Q rotated feedback signal from a Q input signal and provides a Q compensated signal to upconverter 330. A phase shift estimator 370 receives the I and Q input signals and the I feedback signal, estimates the phase shift based on the received signals, and provides an I phase estimate signal PI(t) and a Q phase estimate signal PQ (t). Phase shift estimator 370 estimates the phase shift by using the I and Q input signals as a phase reference. The I and Q phase estimate signals comprise I and Q components of the phase shift, as described below.
In the exemplary design shown in
In the exemplary design shown in
The I and Q feedback signals from lowpass filters 354a and 354b may be expressed as:
Equations (2) and (3) assume that the signal component at the sum frequency is removed by lowpass filters 354. For simplicity, much of the description herein assumes no estimation error, and equal signs (instead of approximate signs) are used in most of the equations herein.
Within phase shift estimator 370, an MI(t) signal from mixer 372a and an MQ (t) signal from mixer 372b may be expressed as:
The I and Q input signals may be assumed to be uncorrelated. Integrator/filter 374a filters the cross product component XI(t)·XQ(t)·sin(φ) in the signal from mixer 372a and provides the desired component XI2(t)·cos(φ). Similarly, integrator/filter 374b filters the cross product component XI(t)·XQ(t)·cos(φ) in the signal from mixer 372b and provides the desired component XQ2(t)·sin(φ). The I and Q phase estimate signals from integrators/filters 374a and 374b may then be expressed as:
P
I(t)=K·cos(φ), and Eq (6)
P
Q(t)=K·sin(φ), Eq (7)
where K=A·β·G/2 and G=avg {XI2 (t)}=avg {XQ2(t)}.
As shown in equations (6) and (7), the I and Q phase estimate signals are indicative of the phase shift φ. Phase shift compensator 360 is a complex multiplier that rotates a complex feedback signal comprising the FI(t) and FQ (t) signals by the phase shift φ and provides a complex rotated feedback signal comprising the RI(t) and RQ(t) signals. The I and Q rotated feedback signals may be expressed as:
As shown in equations (8) and (9), the I and Q rotated feedback signals may be scaled versions of the I and Q input signals, respectively, if the estimate of the phase shift is reasonably accurate. The phase shift compensation may thus remove or reduce the phase shift so that stability of the Cartesian feedback system may be improved.
As noted above, mixers 372a and 372b within phase shift estimator 370 may be implemented with mixers or multipliers since only the relative phase between the I feedback signal and the I and Q input signals is of interest. Multipliers 362a to 362d within phase shift compensator 360 should be implemented with multipliers (and not mixers) since (i) the amplitude of the I and Q feedback signals carries the desired amplitude in the I and Q rotated feedback signals and (ii) the amplitude of the I and Q phase estimate signals carries the desired phase shift information.
Within phase shift estimator 380, mixers 382a and 382b mix the I feedback signal with the I and Q input signals, respectively. Mixers 382c and 382d mix the Q feedback signal with the I and Q input signals, respectively. A summer 384a sums the outputs of mixers 382a and 382d. A summer 384b subtracts the output of mixer 382c from the output of mixer 382b. An integrator/filter 386a integrates or filters the output of summer 384a and provides the I phase estimate signal. Similarly, an integrator/filter 386b integrates or filters the output of summer 384b and provides the Q phase estimate signal. Mixers 382a to 382d may also be implemented with multipliers or some other circuits.
Phase shift estimator 380 includes mixers 382a and 382b that provide the I and Q signals shown in equations (4) and (5). Phase shift estimator 380 further includes mixers 382c and 382d that provide I and Q signals comprising inverted cross product components. Summer 384a cancels the cross product component XI(t)·XQ(t)·sin(φ) from mixers 382a and 382d and provides the desired component. Similarly, summer 384b cancels the cross product component XI(t)·XQ(t)·cos(φ) from mixers 382b and 382c and provides the desired component. An SI(t) signal from summer 384a and an SQ(t) signal from summer 384b may be expressed as:
As shown in equations (10) and (11), the SI(t) and SQ (t) signals from summers 384a and 384b include only the desired components, with the cross product components being canceled. Canceling the cross product components may improve the estimate of the phase shift, especially when the I and Q input signals are not totally uncorrelated.
System 600 includes a feed-forward path 632 from the input signal to summer 616. System 600 also includes a forward path 634 from the combined signal to the output signal. Forward path 634 includes only plant 620 in
A transfer function for system 600 may be expressed as:
As shown in equation (12), the desired transfer function for system 600 and the desired closed-loop characteristics of feedback loop 640 may be obtained by selecting the proper transfer function F for loop filter 614 and the proper transfer function M for model 610.
System 600 may implement Cartesian feedback to linearize an RF transmitter or a power amplifier represented by plant 620. As discussed above, a problem with Cartesian feedback is that phase shift due to plant 620 may cause coupling between the I and Q components, which may then reduce stability margins and may eventually lead to instability. The phase shift may be adaptively estimated and corrected as described below.
An advantage of the structure shown in
System 602 includes feed-forward path 632 from the input signal to summer 616. System 602 also includes a forward path 636 that includes phase/gain compensator 618 and plant 620. System 600 further includes a feedback loop 642, which is formed from the output signal Y through summer 612, loop filter 614, summer 616, phase/gain compensator 618, and plant 620. Feedback loop 642 thus includes forward path 636.
System 604 includes feed-forward path 632 and forward path 634. System 604 further includes a feedback loop 644, which is formed from the output signal Y through phase/gain compensator 618, summer 612, loop filter 614, summer 616, and plant 620. Feedback loop 642 thus includes forward path 634.
In general, phase/gain compensator 618 may be placed anywhere within the feedback loop. The placement of phase/gain compensator 618 may be dependent on various considerations such as implementation complexity, performance, etc.
System 606 includes feed-forward path 632 and forward path 634. System 606 further includes a feedback loop 646, which is formed from the output signal Y through summer 612, phase/gain compensator 618, loop filter 614, summer 616, and plant 620. Feedback loop 646 thus includes forward path 634.
For the exemplary designs shown in
In one exemplary design, the complex value k may be adaptively determined based on the error signal E from summer 612 and the input signal X, as follows:
where γ is an adaptation factor that determines the rate of convergence of the complex value k to a final value, and “*” denotes a complex conjugate.
In the exemplary design shown in equation (14), the complex value k may be obtained by computing the product of the complex conjugate of the input signal X and the error signal E, scaling the product with the adaptation factor, and integrating the scaled product. A condition for stability of the adaptive algorithm is that the transfer function P/(1+F P) is strictly positive real (SPR).
In another exemplary design, the complex value k may be adaptively determined based on the error signal E from summer 612 and the output signal Y from plant 620, as follows:
The exemplary designs shown in equations (14) and (16) have similar form, with equation (14) using the input signal X and equation (16) using the output signal Y. It can be shown that adaptive algorithms using equations (14) and (16) can converge to a complex value having a phase that is equal to but opposite of the phase shift of the plant.
The complex value k may also be estimated with various other adaptive algorithms known in the art. Furthermore, variations of these adaptive algorithms may also be used. For example, integration may be performed with respect to a positive-definite kernel. An example of a positive-definite kernel is exp(−α·t), with α>0. This kernel may replace integration with 1/(s+α).
The adaptation to obtain the complex value k may be performed in digital domain (e.g., with fixed or floating point arithmetic) or in analog domain (e.g., with analog circuits). For a digital implementation, the number of bits for one or more variables may be limited in order to reduce computational complexity. For example, the error signal, the input signal, and/or the output signal may be limited to a predetermined number of bits. For both digital and analog implementations, a single bit may be used to represent the sign (e.g., + or −) of a given signal, e.g., the input signal or the output signal. In general, a limited number of bits may be used for one or both of the two signals (e.g., E and X, or E and Y) used to derive the complex value.
In the forward path, a complex multiplier 820 is coupled between summer 616 and plant 620. Complex multiplier 820 multiplies the combined signal from summer 616 with the complex value k to rotate the phase of the combined signal and possibly adjust the amplitude of the combined signal. Complex multiplier 820 provides the compensated signal to plant 620.
An adaptive algorithm to determine the complex value k can converge if the feedback loop is initially stable. In one exemplary design, initial stability may be ensured based on some prior knowledge of the phase shift of plant 620. This prior knowledge of the phase shift may be obtained from factory calibration, from the phase obtained from the last time the algorithm was operated, from a phase measured in an open loop manner, etc. An initial phase corresponding to the prior knowledge of the phase shift may be applied at the output of integrator/filter 818. In another exemplary design, different initial phase values may be applied, one value at a time, until a converged complex value k is detected. This exemplary design may be used for the very first time that the algorithm is executed. The phase from the converged complex value may be stored for use the next time the algorithm is executed.
In an exemplary design, a desired transfer function (e.g., a desired gain) for plant 620 may be applied to model 610. The adaptive algorithm may then be operated to determine the complex value k. In another exemplary design, model 610 may be omitted by using a transfer function of 1.
In one exemplary design, the entire complex value is applied in the feedback loop, e.g., with a complex multiplier as shown in
In the feed-forward path, an I baseband signal (fin) and a Q baseband signal (Qin) are provided summers 916a and 916b, respectively. Summer 916a sums the I baseband signal and an I filtered error signal from a loop filter 914 and provides an I combined signal. Similarly, a summer 916b sums the Q baseband signal and a Q filtered error signal from loop filter 914 and provides a Q combined signal. Loop filter 914 may correspond to loop filter 614 in
In the feedback path, a feedback circuit 948 receives I and Q target signals from a model 910 and the output RF signal and generates the I and Q filtered error signals. Feedback circuit 948 includes real summers 912a and 912b, loop filter 914, and a downconverter 950. Within feedback circuit 948, the output RF signal from power amplifier 940 is downconverted from RF to baseband by downconverter 950. Within downconverter 950, the output RF signal is downconverted by a mixer 952a with the I LO signal and further filtered by a lowpass filter 954a to obtain an I feedback signal. The output RF signal is also downconverted by a mixer 952b with the Q LO signal and further filtered by a lowpass filter 954b to obtain a Q feedback signal. The I and Q LO signals used for upconverter 930 are also used for downconverter 950 (possibly with buffering not shown in
In an exemplary design, an apparatus (e.g., a wireless device, an IC, etc.) may comprise a feedback system that may include a forward path and a feedback path, e.g., as shown in
In an exemplary design, the first circuit(s) in the forward path may comprise a complex summer, an upconverter, and a power amplifier, e.g., as shown in
In an exemplary design, the second circuit(s) in the feedback path may comprise a downconverter, a filter, and a phase shift compensator, e.g., as shown in
The feedback system may further comprise a phase shift estimator to estimate the phase shift. The phase shift estimator may receive the input signal and I and/or Q component of the feedback signal and may provide the phase estimate signal. In an exemplary design, the phase shift estimator may comprise first and second mixers and first and second filters. The first mixer (e.g., mixer 372a in
In another exemplary design, the phase shift estimator may further comprise third and fourth mixers and first and second summers. The third mixer (e.g., mixer 382c in
In another exemplary design, an apparatus may comprise a feedback system that may include a forward path and a feedback loop, e.g., as shown in
In an exemplary design, the second circuit(s) in the feedback loop may comprise first and second summers, a loop filter, and a phase/gain compensator. The first summer may subtract a version (e.g., a downconverted version) of the output signal from a version of the input signal and may provide the error signal. The loop filter may filter the error signal to obtain a filtered error signal. The second summer may sum the filtered error signal with the input signal and may provide the combined signal.
The phase/gain compensator may perform phase rotation to remove at least part of the phase shift and may be located in the forward path (e.g., as shown in
The feedback system may further comprise a model circuit that may implement a target function for the first circuit(s). The model circuit may receive the input signal and provide a target signal. The error signal may be generated based on the target signal and the output signal.
The feedback system with phase compensation described herein may be implemented on one or more ICs, analog ICs, RF ICs (RFICs), mixed-signal ICs, application specific integrated circuits (ASICs), printed circuit boards (PCBs), electronics devices, etc. The feedback system with phase compensation may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.
An apparatus implementing the feedback system with phase compensation described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
