Claims
- 1. An apparatus for high speed storage of data at designated locations within an array of locations in memory comprising
- memory means having a plurality of storage sites for storing the data, wherein each storage site corresponds to a different one of the locations in the array of locations, and wherein the storage sites are addressable in blocks of storage sites, each block having a unique address, and further wherein each storage site within a an addressed block of storage sites can be individually enabled to store data when that block of storage sites is being addressed, wherein the memory means responds at a memory write access rate to an addressing of a block of storage sites for writing data therein, and responds at a write enable rate to an enabling of a storage site for writing data therein, the write enable rate being greater than the memory write access rate;
- address generator means coupled to the memory means for addressing blocks of storage sites which contain the designated locations and for enabling storage sites within the addressed blocks which correspond to the designated locations, wherein the address generator means are controllable to enable the storage sites at a rate of operation corresponding to either the memory write access rate or the write enable rate; and
- control means coupled to the address generator means for controlling the rate of operation of the address generator means, wherein the control means controls the address generator means to operate at the memory write access rate for a predetermined period of time whenever the address generator means addresses a new block of storage sites, and controls the address generator means to operate at the write enable rate whenever the address generator means enables storage sites within a block of storage sites which is currently being addressed, so that the data are stored in the memory means at the highest rate at which the memory means is capable of responding.
- 2. The apparatus of claim 1, wherein the address generator means comprise
- addressing means for generating addresses for the designated locations into which the data are to be stored, wherein the addressing means operates at the rate of operation selected by the control means; and
- means responsive to the designated location addresses for interpreting each designated location address so as to provide the address of the block in which is located the storage site corresponding to the designated location address and to designate the storage site within the block which is to be enabled.
- 3. The apparatus of claim 2, wherein the addressing means include a vector address generator which implements a Bresenham vector generator algorithm.
- 4. The apparatus of claim 1, wherein the memory means include a plurality of random access memories, each of which has a data line and a write enable line, and each of which contains a plurality of addressable storage sites for storing data provided on the data line upon receipt of an address and a write enable signal, and
- further wherein data and addresses are provided to the plurality of random access memories in common but write enable signals are applied individually,
- so that for each address applied to the plurality of random access memories a single storage site in each of the plurality of random access memories is addressed, and the addressed storage sites from each of the plurality of random access memories form the block of storage sites corresponding to the applied address, and
- so that data are written into only those addressed storage sites located in the ones of the plurality of random access memories which also received a write enable signal.
- 5. The apparatus of claim 1, wherein the memory means stores data for display on a raster scanning display so that the data are arranged in the memory means according to scan lines and the data corresponding to each scan line are stored in a plurality of blocks of storage sites, and wherein each address provided by the address generator means includes a scan line address, an address of a block within the addressed scan line, and a designation of the storage site within the addressed block which is to receive the data, and
- further wherein the control means is responsive to the scan line address and to the storage site designation such that the control means selects the memory write access rate of operation for the address generator means whenever a new scan line address or a storage site at either end of the addressed block are specified, and
- such that the control means selects the write enable rate of operation for the address generator means whenever a storage site within the addressed block is specified.
- 6. The apparatus of claim 2, wherein the addressing means operates at the write enable rate and is responsive to a delay signal so that upon receipt of a delay signal the addressing means delays operation for a period of time corresponding to the length of the delay signal, and further wherein the control means controls the address generator means to operate at the memory write access rate by applying the delay signal to the addressing means, which delay signal has a length in time which corresponds to the memory write access rate.
- 7. The apparatus of claim 1, wherein the memory means stores data for display on a raster scanning display so that the data stored therein are arranged according to scan lines in which data corresponding to each scan line are stored in a plurality of blocks of storage sites, and wherein address information including starting address parameters and displacement parameters, are received from a user, and further wherein the address generator means comprise
- vector generator means responsive to the displacement parameters for generating vector control signals at the write enable rate including an increment/decrement scan line signal for addressing different scan lines, and an increment decrement storage site signal for addressing different storage sites in a scan line; and
- presettable counter means responsive to the starting address parameters, the increment/decrement scan line signal, and the increment/decrement storage site signal, for providing the scan line address, the block address and for enabling the storage sites, wherein the presettable counter means modifies the starting address parameters in accordance with the incresent/decrement scan line signal and the increment/decrement storage site signal to provide the scan line address, the block address and to enable the storage sites.
- 8. The apparatus of claim 7, wherein each block of storage sites has boundaries located at the first storage site and the last storage site in the block, and further wherein the control means comprise
- means coupled to the vector generator means for detecting the presence of the increment/decrement scan line signal, including first means for generating a first delay signal whenever the presence of the increcent/decrement scan line signal is detected;
- means coupled to the presettable counter means for determining when a storage site which is located at the boundary of a block is being enabled, including means for generating a second delay signal whenever a storage site located at the boundary of a block is being enabled,
- wherein the vector generator means are responsive to the first and second delay signals such that the vector generator means operates at the memory write access rate whenever the first or second delay signals are generated.
BRIEF SUMMARY OF THE INVENTION
This is a continuation of application Ser. No. 515,946, filed July 20, 1983, now abandoned.
1. Technical Field
The present invention is, in general, directed to writing information into a random access memory and, more particularly, to a method and apparatus for writing a vector of data into a random access memory at high speed.
2. Background Art
In computer graphics systems, an image is produced on a visual display screen. The information by which this visual image is generated is stored in a screen refresh random access memory on a one-to-one or pixel-to-storage site basis. That is, for each pixel of the visual image display, there is a corresponding storage site in the random access memory (RAM) which contains data corresponding to and describing the visual information of that pixel. In order to display the information from the screen refresh RAM, the data from the screen refresh RAM are periodically read out on a line-by-line basis and displayed on a line-by-line basis in the visual display of the system. Typical of these displays are raster scanning devices such as high density television monitors which have a large number of horizontially displayed scan lines.
In order to write information into the screen refresh RAM, an X and a Y address are supplied to the RAM, along with the data to be written thereby. A write enable signal is supplied to the RAM to write the data into the addressed storage site. This process must be repeated for each storage site into which data are to be written. This entails supplying a different address for each different storage site being written into.
It is well-known that the speed at which these write operations can occur is limited by the RAM access time; i.e., the amount of time that the address and data are required to be present before the RAM can accurately respond to the information. It is also well-known that the speed by which data can be written into the RAM is limited by the speed at which the addressing of the RAM occurs.
The speed with which data can be written into a screen refresh RAM has a direct impact upon the performance of a graphics display system. For example, when extensive images are sought to be written into the screen refresh RAM, there will be a substantial time delay during which the write operation is being executed. In turn, this slows the operation of the entire system, as well as detracts from the operation of the system as a tool which assists in a design or display process.
The foregoing problems of previous apparatus for writing data into a screen refresh RAM are overcome by the present invention of a method and apparatus for writing data into a screen refresh RAM at high speed, including a random access memory having a plurality of storage sites wherein the storage sites are addressable in blocks at a memory access rate. The storage sites within an accessed addressable block can be individually enabled at a write enable rate to receive data. An address generator provides the addressing for each block which is to be written into and the enable signal for the particular storage site within the accessed addressable block which is to receive the data. The rate of operation of the address generator is selectable between the memory access rate and the write enable rate. A control means is coupled to the address generator for selecting the rate of operation of the address generator according to the nature of the addresses being supplied by the address generator. Whenever addresses are supplied by the address generator for accessing a new addressable block, the control means cause the address generator to operate at the memory access rate for a predetermined period of time. After the predetermined period of time, the control means cause the address generator to resume operation at the write enable rate.
With the present invention the screen RAM is required to be addressed less frequently than the screen refresh RAM apparatus of the prior art. As used herein, a RAM access entails the application of an address on the RAM address lines, the receipt of or output of data on the RAM data lines, and the application of a write or a read enable signal on the RAM enable line. The RAM enable operation entails the application of the write or read enable signal to the RAM, it being assumed that the address and input data remain unchanged. Typically, the period of time required for a RAM access, such as a write operation, is longer than the period of time required for the RAM to be enabled, such as a write enable. Thus, with the above structure, a large proportion of the writing into or reading out of the storage sites in the RAM can be accomplished by enabling the appropriate storage site in the RAM. The number of storage sites within each block affect how frequently a RAM access operation will be required. Since the write enable signal is typically shorter than the RAM access time period, data can be written into the RAM at a higher speed for storage sites within a block. Thus, when the system is writing information within a block, the vector generator can operate at a speed which is comparable to the write enable speed requirement. When the storage site to be written into crosses a boundary between blocks or lies within a new block, the control means causes the address generator to slow down for a time period which satisfies the RAM access timing requirements. Thereafter, the control means permits the address generator to resume operation at the higher rate.
In order to implement the organization of storage sites into blocks in the preferred embodiment, a plurality of random access memories are addressed in common and receive data in common; however, each random access memory is supplied individually with a write enable signal. Thus, for a particular address, the corresponding storage site in each RAM for all of the RAMs collectively represent the block of storage sites corresponding to the address. When a write enable signal is supplied to a particular RAM, the data present on the data lines are written into that enabled RAM only, and only at the applied address.
In the preferred embodiment, the control means are implemented by circuitry which monitors the Y address for any changes therein, and the X address for any addresses which correspond to the end points of a block of storage sites. Upon the occurrence of either a change in the Y address or the addressing of an end point of a block, the circuitry supplies a delay signal or an inhibit signal to the address generator.
It is, therefore, an object of the present invention to provide a method and apparatus for writing data into a screen refresh RAM at high speed, wherein the screen refresh RAM includes storage sites which are accessable in addressable blocks, and wherein storage sites in an addressable block are individually enabled, and wherein addresses and write enable signals are supplied to the screen refresh RAM at a rate corresponding to the write enable rate of the screen refresh RAM, and further wherein circuitry is provided which slows the operation of the address generator for a predetermined period of time whenever a storage site within a different addressable block is being accessed.
It is another object of the present invention to provide a method and apparatus for writing data into a screen refresh RAM at high speed wherein storage sites within the refresh RAM are arranged in addressable blocks, and storage sites within an accessed addressable block can be enabled individually, and further wherein data are written into storage sites located within a given block at a rate corresponding to the write enable rate of the screen refresh RAM by operating an address generator at the write enable rate, and further wherein the operation of the address generator is slowed to the memory access rate of the screen refresh RAM whenever the next storage site to be written into is located in a different block of storage sites.
These and other objectives, features and advantages of the present invention will be more readily understood upon consideration of the following detailed description of the present invention, taken in conjunction with the accompanying drawings.
US Referenced Citations (8)
Continuations (1)
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515946 |
Jul 1983 |
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Patent Grant
4646262
