Embodiments of the present disclosure relate to memory devices and fabrication methods thereof, and specifically relates to ferroelectric memory devices and fabrication methods thereof.
The demand for a non-volatile memory that has low operational voltage, low power consumption, and high-speed operation suitable for various electronic equipment, such as portable terminals and integrated circuit (IC) cards, has increased. Ferroelectric memory, such as ferroelectric RAM (FeRAM or FRAM), uses a ferroelectric material layer to achieve non-volatility. A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge and thus, can switch polarity in an electric field. Ferroelectric memory's advantages include low power consumption, fast write performance, and great maximum read/write endurance.
Embodiments of ferroelectric memory devices and fabrication methods thereof are disclosed herein.
In one aspect, a memory device is disclosed. The memory device includes a plurality of memory cells and a routing interconnection structure in electric contact with the plurality of memory cells. Each memory cell includes at least one first transistor, a cell interconnection structure formed over the at least one transistor and in electrical contact with the at least one transistor, the cell interconnection structure including a cell plate disposed at a top layer of the cell interconnection structure, and at least one capacitor electrically coupled to the at least one first transistor through the cell interconnection structure. Each capacitor includes a first electrode, a second electrode surrounding at least a portion of the first electrode, the second electrode electrically contacting the cell plate, and a ferroelectric layer disposed between the first electrode and the second electrode. The routing interconnection structure includes a first conductive layer, and a first via structure disposed on the first conductive layer. The first via structure is in electrical contact with the first electrode through a second conductive layer. The first conductive layer is beneath the second conductive layer.
In some embodiments, the second conductive layer is disposed on and in direct contact with the first electrode. In some embodiments, the second conductive layer is disposed on and in electric contact with the first electrode through a second via structure. In some embodiments, a first height of the at least one capacitor is equal to or less than a second height of a stack of the first via structure and the second conductive layer.
In some embodiments, the memory device further includes a periphery circuit configured to control operations of the plurality of memory cells. The periphery circuit includes at least one second transistor, and a periphery interconnection structure electrically coupled to the at least one second transistor. A third conductive layer of the periphery interconnection structure is in electric contact with the first conductive layer.
In some embodiments, the third conductive layer and the first conductive layer are extended and directly connected to each other.
In another aspect, a memory device is disclosed. The memory device includes a plurality of memory cells, and a dummy memory cell. Each memory cell includes at least one first transistor, a cell interconnection structure formed over the at least one transistor and in electrical contact with the at least one transistor, the cell interconnection structure including a cell plate disposed at a top layer of the cell interconnection structure, and at least one capacitor electrically coupled to the at least one first transistor through the cell interconnection structure. Each capacitor includes a first electrode, a second electrode surrounding at least a portion of the first electrode, the second electrode electrically contacting the cell plate, and a ferroelectric layer disposed between the first electrode and the second electrode. The dummy memory cell includes at least one second transistor, a first conductive layer disposed above the at least one second transistor, and a first via structure disposed on the first conductive layer. The first via structure is in electrical contact with the first electrode through a second conductive layer. The first conductive layer is beneath the second conductive layer.
In some embodiments, a first region of the first via structure is within a second region of the dummy memory cell in a plan view of the memory device. In some embodiments, the second conductive layer is disposed on and in direct contact with the first electrode. In some embodiments, the second conductive layer is disposed on and in electric contact with the first electrode through a second via structure. In some embodiments, a first height of the at least one capacitor is equal to or less than a second height of a stack of the first via structure and the second conductive layer.
In some embodiments, the memory device further includes a periphery circuit configured to control operations of the plurality of memory cells. The periphery circuit includes at least one third transistor, and a periphery interconnection structure electrically coupled to the at least one third transistor. A third conductive layer of the periphery interconnection structure is in electric contact with the first conductive layer.
In some embodiments, top surfaces of the third conductive layer and the first conductive layer are flush with each other. In some embodiments, the third conductive layer and the first conductive layer are extended and directly connected to each other.
In still another aspect, a method for forming a ferroelectric memory cell is disclosed. A semiconductor structure is formed over a substrate, the semiconductor structure including a cell region, a dummy cell region, and a periphery region. A first interconnection structure is formed over the cell region, a second interconnection structure is formed over the dummy cell region, and a third interconnection structure is formed over the periphery region. The second interconnection structure is in electrical contact with the third interconnection structure. A dielectric layer is formed over the first interconnection structure, the second interconnection structure, and the third interconnection structure. A capacitor is formed in the dielectric layer above the first interconnection structure, and a via structure is formed in the dielectric layer above the second interconnection structure. The capacitor and the via structure are electrically connected through a first conductive layer.
In some embodiments, the capacitor includes a first electrode, a second electrode surrounding at least a portion of the first electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. The conductive layer is in direct contact with the first electrode.
In some embodiments, the first conductive layer is formed over a plurality of capacitors in direct contact with a plurality of first electrodes of the plurality of capacitors, and is formed over the via structure in direct contact with the via structure.
In some embodiments, a cell plate is formed on a topmost layer of the first interconnection structure, and a second conductive layer is formed on a topmost layer of the second interconnection structure. Top surfaces of the cell plate and the second conductive layer are flush with each other.
In some embodiments, the dummy cell region is outside an edge of the cell region in a plan view of the semiconductor structure. In some embodiments, a first height of the capacitor is equal to or less than a second height of a stack of the via structure and the first conductive layer.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.
The present disclosure will be described with reference to the accompanying drawings.
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.
As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).
As used herein, a “side surface” can generally refer to a surface on the exterior of an object. For example, depending on the embodiment, a side surface can be a sidewall along a horizontal direction (e.g., the x-direction) or a top/bottom surface along a vertical direction (e.g., the z-direction). As used herein, a recess refers to an open space between two boundaries. For example, depending on the embodiment, a recess can be located between two surfaces that are not coplanar with each other, e.g., having a staggered configuration.
A memory cell array of the ferroelectric memory device may include a number of bit lines and a number of word lines extending to cross with each other, and a number of memory cells may be arranged in a matrix at positions corresponding to the respective crossings of the lines. Each memory cell may include at least one memory cell transistor, in which the gate electrode of the memory cell transistor may receive a signal from the word line, and at least one ferroelectric capacitor interposed between the source region of the memory cell transistor and a cell plate line. The ferroelectric capacitor has a residual polarization characteristic to generate positive or negative residual polarizations depending on the high/low relationship between the voltage applied to the ferroelectric capacitor from the bit line via the memory cell transistor and the voltage applied to the ferroelectric capacitor from the cell plate line. Hence, one limitation of the ferroelectric memory device fabrication is the capacitance of the ferroelectric capacitor. Various embodiments in accordance with the present disclosure provide ferroelectric memory devices and fabrication methods thereof that can increase the capacitance of the ferroelectric capacitor.
Ferroelectric memory device 100 includes at least one memory cell 102 and at least one routing interconnection structure 104. Memory cell 102 includes at least one transistor 106, and an interconnection structure 108 disposed on transistor 106. In some embodiments, interconnection structure 108 may include one or more than one interconnection layers, as shown in
A conductive plate 110 is formed over interconnection structure 108, or at the topmost layer of interconnection structure 108. In some embodiments, conductive plate 110 may be the cell landing island of ferroelectric memory device 100. At least one capacitor 112 is formed on conductive plate 110. Ferroelectric memory device 100 may include a plurality of memory cell 102, and each memory cell 102 may be the storage element of ferroelectric memory device 100, and may include various designs and configurations.
Capacitor 112 is electrically coupled to transistor 106 through interconnection structure 108 and conductive plate 110. Capacitor 112 includes an electrode 114, and an electrode 116 surrounding at least a portion of electrode 114. In some embodiments, electrode 116 electrically contacts conductive plate 110. In some embodiments, electrode 116 directly contacts conductive plate 110. A ferroelectric layer 118 is disposed between electrode 114 and electrode 116.
Ferroelectric layer 118 may include oxygen and one or more ferroelectric metals. The ferroelectric metals may include, but not limited to, zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), or other suitable materials. In some embodiments, ferroelectric layer 118 may include oxygen and two or more ferroelectric metals. In some embodiments, ferroelectric layer 118 may include oxygen and a non-metal material such as silicon (Si). Optionally, ferroelectric layer 118 may also include a plurality of dopants formed as a part of the crystal structures. In some embodiments, the dopants compensate for the defects formed during the crystallization of the ferroelectric oxide material to improve the film quality of ferroelectric layer 118. In some embodiments, the dopants are different from the ferroelectric metals in the ferroelectric oxide material and include one or more dopants from one or more of Hf, Zr, Ti, Al, Si, hydrogen (H), oxygen (O), vanadium (V), niobium (Nb), tantalum (Ta), yttrium (Y), and/or lanthanum (La).
Routing interconnection structure 104 may include a conductive layer 120, and a via structure 122, as shown in
As shown in
It is understood that conductive layer 124 may further electrically connect other conductive layers beneath conductive layer 120 based on various applications when more than one stack of conductive layer and via structure are applied to form routing interconnection structure 104.
By electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, the routing path may be designed through conductive layer, e.g., layer Mn, beneath the topmost conductive layer, e.g., layer Mn+1. Furthermore, by electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, capacitor 112 may be formed between the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, and electrode 114 can have a routing path through conductive layer 124, via structure 122, and conductive layer 120.
Typically, the topmost metal structure, including via structure 122, of routing interconnection structure 104 or the periphery circuit has the largest thickness among other metal structures. When forming capacitor 112 in the area corresponding to the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, capacitor 112 may have a larger cell area and enough charge for memory sensing. Capacitor 112 is, therefore, may be disposed in the area corresponding to one single metal structure layer instead of occupying multiple layers of metal structure. By using this structure, the manufacturing process may be simplified, and the reliability of the memory cells may also be improved.
Ferroelectric memory device 200 includes at least one memory cell 102 and at least one dummy memory cell 128. Memory cell 102 may include at least one transistor 106, and interconnection structure 108 may be disposed on transistor 106, as discussed above. Conductive plate 110 is formed over interconnection structure 108, or at the topmost layer of interconnection structure 108. In some embodiments, conductive plate 110 may be the cell landing island of ferroelectric memory device 200. Capacitor 112 is formed on conductive plate 110. Ferroelectric memory device 200 may include a plurality of memory cell 102, and each memory cell 102 may be the storage element of ferroelectric memory device 200, and may include various designs and configurations.
Capacitor 112 is electrically coupled to transistor 106 through interconnection structure 108 and conductive plate 110. Capacitor 112 may include electrode 114, and electrode 116 surrounding at least a portion of electrode 114. In some embodiments, electrode 116 electrically contacts conductive plate 110. In some embodiments, electrode 116 directly contacts conductive plate 110. Ferroelectric layer 118 is disposed between electrode 114 and electrode 116.
Generally, a memory cell array of a semiconductor memory may include a plurality of memory cells arranged in a matrix and wirings (word lines and bit lines) for connecting those memory cells to a word decoder, a sense amplifier, and the like. In the memory cell array, elements and wirings are arranged with higher density, as compared with those in circuits near the memory cell array. In other words, the layout density of the elements and wirings on the inside of the memory cell array is different from that on the outside thereof. Thus, the shapes of the elements and wirings in an inner region of the memory cell array may be different from those in an outer peripheral region because of halation or the like in a fabrication process. Such a difference in the shapes may cause a short failure and a disconnection failure, thus reducing the yield. In order to make the shapes of the elements and wirings in the inner region of the memory cell array the same as those in the outer peripheral region so as to increase the yield, dummy memory cells and/or dummy wirings may be formed in the outer peripheral region of the memory cell array.
Dummy memory cell 128 may include at least one transistor 127, and an interconnection structure 126 may be disposed on transistor 127. Conductive layer 120 may be disposed above transistor 127. In some embodiments, dummy memory cell 128 may have conductive layer 120 electrically connected to interconnection structure 126. In some embodiments, conductive layer 120 may be electrically isolated from interconnection structure 126, as shown in
Since conductive layer 120 and via structure 122 are formed above the region of dummy memory cell 128, the region of conductive layer 120 and via structure 122 is within the region of dummy memory cell 128 in a plan view of ferroelectric memory device 200. In other words, conductive layer 120 and via structure 122 overlaps the region of dummy memory cell 128 in the plan view of ferroelectric memory device 200. In some embodiments, the region of via structure 122 is within the region of dummy memory cell 128 in a plan view of ferroelectric memory device 200. In other words, via structure 122 overlaps the region of dummy memory cell 128 in the plan view of ferroelectric memory device 200. Via structure 122 is disposed on conductive layer 120. Via structure 122 and electrode 114 are in electrical contact through a conductive layer 124. One conductive layer and one via structure are shown in
As shown in
It is understood that conductive layer 124 may further electrically connect other conductive layers beneath conductive layer 120 based on various applications when more than one stack of conductive layer and via structure are formed above dummy memory cell 128.
By electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, the conductive layer(s) and via(s) above dummy memory cell 128 may be used for the routing path. Since via structure 122 and conductive layer 120 are formed within the dummy cell region (in the plan view), the routing path will not occupy extra area of ferroelectric memory device 200, and the size of ferroelectric memory device 200 will not be affected. In addition, the routing path may be designed through conductive layer, e.g., layer Mn, beneath the topmost conductive layer, e.g., layer Mn+1, and the manufacturing process of layer Mn is already required when forming memory cell 102; therefore, no extra process or mask will be added.
Furthermore, by electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, capacitor 112 may be formed between the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, and electrode 114 can have a routing path through conductive layer 124, via structure 122, and conductive layer 120.
Typically, the topmost metal structure, including via structure 122 has the largest thickness among other metal structures. When forming capacitor 112 in the area corresponding to the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, capacitor 112 may have a larger cell area and enough charge for memory sensing. Capacitor 112 is, therefore, may be disposed in the area corresponding to one single metal structure layer instead of occupying multiple layers of metal structure. By using this structure, the manufacturing process may be simplified, and the reliability of the memory cells may also be improved.
Periphery circuit 130 is configured to control operations of memory cell 102. Periphery circuit 130 may include at least one transistor 131, and an interconnection structure 132 electrically coupled to transistor 131. In some embodiments, interconnection structure 132 may include one or more than one interconnection layers, as shown in
As shown in
It is understood that even though the topmost conductive layer (conductive plate 134) in interconnection structure 132 is shown to connect conductive layer 120 in
Various embodiments in
In another example, as shown in
In a further example,
Via structures 1404 and 1406 may be located on the bottom edge of each memory cell region 1402 between each memory cell region 1402 and each periphery circuit 1408, as shown in
As shown in
As shown in
The semiconductor structure may include transistors 106, 127, and 131, as shown in
As shown in
In some embodiments, dummy memory cell 128 may be located in the dummy cell region outside the edge of the cell region in a plan view of ferroelectric memory device 400. In some embodiments, conductive plate 110 may be located above interconnection structure 108. In some embodiments, conductive plate 110 may be the topmost conductive layer of interconnection structure 108. In some embodiments, another interconnection structure may be formed above dummy memory cell 128, and conductive layer 120 may be the topmost conductive layer of this interconnection structure. In some embodiments, conductive plate 110 and conductive layer 120 are the same conductive layer located beneath conductive layer 124. In some embodiments, conductive plate 110 and conductive layer 120 are formed in the same process. In some embodiments, conductive plate 110 and conductive layer 120 may include the same material. In some embodiments, the top surfaces of conductive plate 110 and conductive layer 120 may be flush with each other.
As shown in
In some embodiments, dielectric layer 404 may include an interlayered dielectric (ILD) layer, such as SiOx or SiNx. In some embodiments, capacitor 112 is formed in dielectric layer 404 before the formation of via structure 122. In some embodiments, via structure 122 is formed in dielectric layer 404 before the formation of capacitor 112. In some embodiments, capacitor 112 and via structure 122 are formed in dielectric layer 404 during the same manufacturing processes. Capacitor 112 may include electrode 114, and electrode 116 surrounding at least a portion of electrode 114. In some embodiments, electrode 116 electrically contacts conductive plate 110. In some embodiments, electrode 116 directly contacts conductive plate 110. Ferroelectric layer 118 is disposed between electrode 114 and electrode 116. In some embodiments, the height of capacitor 112 is less than or equal to the height of via structure 122. In some embodiments, the height of capacitor 112 is less than the height of a stack of via structure 122 and conductive layer 124.
Electrode 116, ferroelectric layer 118, and electrode 114 are sequentially formed in dielectric layer 404, and electrode 116 electrically contacts conductive plates 110. In some embodiments, electrode 114 and electrode 116 may include TiN, titanium silicon nitride (TiSiNx), titanium aluminum nitride (TiAlNx), titanium carbon nitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbon nitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxides (TCO), iridium oxide (IrOx), or other suitable materials. In some embodiments, electrode 114 and electrode 116 may include the same material(s). In some embodiments, electrode 114 and electrode 116 may include different materials.
In some embodiments, electrode 114 and electrode 116 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition, pulsed laser deposition (PLD), or other suitable processes. In some embodiments, electrode 114 and electrode 116 may have a thickness between about 2 nm and about 50 nm. In some embodiments, electrode 114 and electrode 116 may have the same thickness. In some embodiments, electrode 114 and electrode 116 may have different thicknesses.
In some embodiments, ferroelectric layer 118 may include a ferroelectric oxide material. The ferroelectric oxide may be doped with a plurality of dopants, which can improve ferroelectric film crystallization. For example, the dopants may provide elasticity during the crystallization of the doped ferroelectric layer, reducing the number of defects formed in the ferroelectric film crystallization, and improving high-K ferroelectric phase formation. It is understood that in some embodiments, ferroelectric layer 118 may include a multi-layer structure.
In some embodiments, ferroelectric layer 118 may include a ferroelectric composite oxide. In some embodiments, ferroelectric layer 118 may include oxygen and one or more ferroelectric metals. The ferroelectric metals can include, but not limited to, zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), or other suitable materials. In some embodiments, ferroelectric layer 118 may include oxygen and two or more ferroelectric metals. In some embodiments, ferroelectric layer 118 may include oxygen and a non-metal material such as silicon (Si).
Optionally, ferroelectric layer 118 may also include a plurality of dopants formed as a part of the crystal structures. In some embodiments, the dopants compensate for the defects formed during the crystallization of the ferroelectric oxide material to improve the film quality of ferroelectric layer 118. In some embodiments, the dopants are different from the ferroelectric metals in the ferroelectric oxide material and include one or more dopants from one or more of Hf, Zr, Ti, Al, Si, hydrogen (H), oxygen (O), vanadium (V), niobium (Nb), tantalum (Ta), yttrium (Y), and/or lanthanum (La).
As shown in
By electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, the routing path may be designed through conductive layer, e.g., layer Mn, beneath the topmost conductive layer, e.g., layer Mn+1. Furthermore, by electrically connecting conductive layer 124 and conductive layer 120 through via structure 122, capacitor 112 may be formed between the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, and electrode 114 can have a routing path through conductive layer 124, via structure 122, and conductive layer 120.
Typically, the topmost metal structure, including via structure 122, of routing interconnection structure 104 or the periphery circuit has the largest thickness among other metal structures. When forming capacitor 112 in the area corresponding to the topmost conductive layer, e.g., layer Mn+1, and the penultimate conductive layer, e.g., layer Mn, capacitor 112 may have a larger cell area and enough charge for memory sensing. Capacitor 112 is, therefore, may be disposed in the area corresponding to one single metal structure layer instead of occupying multiple layers of metal structure. By using this structure, the manufacturing process may be simplified, and the reliability of the memory cells may also be improved.
The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
This application is a continuation of International Application No. PCT/CN2021/117074, filed on Sep. 8, 2021, which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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Parent | PCT/CN2021/117074 | Sep 2021 | WO |
Child | 18595968 | US |